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Searched refs:reg_offset (Results 1 – 25 of 28) sorted by relevance

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/NextBSD/sys/dev/drm2/i915/
HDintel_iic.c233 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_read() local
237 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_read()
249 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & in gmbus_xfer_read()
257 val = I915_READ(GMBUS3 + reg_offset); in gmbus_xfer_read()
270 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_write() local
281 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer_write()
282 I915_WRITE(GMBUS1 + reg_offset, in gmbus_xfer_write()
296 I915_WRITE(GMBUS3 + reg_offset, val); in gmbus_xfer_write()
299 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) & in gmbus_xfer_write()
325 int reg_offset = dev_priv->gpio_mmio_base; in gmbus_xfer_index_read() local
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/NextBSD/contrib/gdb/gdb/
HDia64-fbsd-tdep.c39 static int reg_offset[462] = { variable
109 ofs = reg_offset[regno]; in ia64_fbsd_regcache_collect()
133 ofs = reg_offset[regno]; in ia64_fbsd_regcache_supply()
142 bsp += *((uint64_t*)((char *)regs + reg_offset[IA64_BSPSTORE_REGNUM])); in ia64_fbsd_regcache_supply()
HDamd64-nat.c58 int *reg_offset = amd64_native_gregset64_reg_offset; in amd64_native_gregset_reg_offset() local
65 reg_offset = amd64_native_gregset32_reg_offset; in amd64_native_gregset_reg_offset()
73 return reg_offset[regnum]; in amd64_native_gregset_reg_offset()
HDamd64fbsd-nat.c58 static int reg_offset[] = variable
158 amd64_native_gregset64_reg_offset = reg_offset; in _initialize_amd64fbsd_nat()
HDi386bsd-nat.c70 static int reg_offset[] = variable
98 #define REG_ADDR(regset, regno) ((char *) (regset) + reg_offset[regno])
115 return (reg_offset[regno] == -1); in cannot_fetch_register()
HDmips-tdep.c294 int reg_offset = 0; in mips_xfer_register() local
301 reg_offset = register_size (current_gdbarch, reg_num) - length; in mips_xfer_register()
304 reg_offset = 0; in mips_xfer_register()
307 reg_offset = 0; in mips_xfer_register()
315 reg_num, reg_offset, buf_offset, length); in mips_xfer_register()
324 regcache_cooked_read_part (regcache, reg_num, reg_offset, length, in mips_xfer_register()
327 regcache_cooked_write_part (regcache, reg_num, reg_offset, length, in mips_xfer_register()
1498 long reg_offset; in mips_mdebug_frame_cache() local
1518 reg_offset = PROC_REG_OFFSET (proc_desc); in mips_mdebug_frame_cache()
1573 CORE_ADDR reg_position = (cache->base + reg_offset); in mips_mdebug_frame_cache()
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HDi386gnu-nat.c51 static int reg_offset[] = variable
59 #define REG_ADDR(state, regnum) ((char *)(state) + reg_offset[regnum])
HDvalops.c656 int reg_offset; in value_assign() local
665 for (reg_offset = value_reg, offset = 0; in value_assign()
666 offset + DEPRECATED_REGISTER_RAW_SIZE (reg_offset) <= VALUE_OFFSET (toval); in value_assign()
667 reg_offset++); in value_assign()
682 for (regno = reg_offset, amount_copied = 0; in value_assign()
699 for (regno = reg_offset, amount_copied = 0; in value_assign()
/NextBSD/contrib/gcc/
HDpostreload.c1171 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; variable
1248 rtx new_src = gen_int_mode (INTVAL (src) - reg_offset[regno], in reload_cse_move2add()
1262 if (INTVAL (src) == reg_offset [regno]) in reload_cse_move2add()
1280 && ((reg_offset[regno] in reload_cse_move2add()
1302 reg_offset[regno] = INTVAL (src); in reload_cse_move2add()
1334 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; in reload_cse_move2add()
1335 HOST_WIDE_INT regno_offset = reg_offset[regno]; in reload_cse_move2add()
1364 reg_offset[regno] = in reload_cse_move2add()
1488 offset = reg_offset[REGNO (XEXP (src, 1))]; in move2add_note_store()
1497 offset = reg_offset[REGNO (base_reg)]; in move2add_note_store()
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HDlocal-alloc.c217 static char *reg_offset; variable
325 reg_offset[regno] = 0; in alloc_qty()
379 reg_offset = XNEWVEC (char, max_regno); in local_alloc()
444 free (reg_offset); in local_alloc()
1730 reg_renumber[i] = qty[q].phys_reg + reg_offset[i]; in block_alloc()
2023 reg_offset[sreg] = reg_offset[ureg] + offset; in combine_regs()
2041 reg_offset[i] -= offset; in combine_regs()
/NextBSD/sys/dev/drm2/radeon/
HDni.c1291 u32 reg_offset, wb_offset; in cayman_dma_resume() local
1303 reg_offset = DMA0_REGISTER_OFFSET; in cayman_dma_resume()
1307 reg_offset = DMA1_REGISTER_OFFSET; in cayman_dma_resume()
1311 WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
1312 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); in cayman_dma_resume()
1320 WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); in cayman_dma_resume()
1323 WREG32(DMA_RB_RPTR + reg_offset, 0); in cayman_dma_resume()
1324 WREG32(DMA_RB_WPTR + reg_offset, 0); in cayman_dma_resume()
1327 WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, in cayman_dma_resume()
1329 WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, in cayman_dma_resume()
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HDsi.c925 u32 reg_offset, gb_tile_moden, split_equal_to_row_size; in si_tiling_mode_table_init() local
942 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { in si_tiling_mode_table_init()
943 switch (reg_offset) { in si_tiling_mode_table_init()
1178 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in si_tiling_mode_table_init()
1181 for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) { in si_tiling_mode_table_init()
1182 switch (reg_offset) { in si_tiling_mode_table_init()
1417 WREG32(GB_TILE_MODE0 + (reg_offset * 4), gb_tile_moden); in si_tiling_mode_table_init()
/NextBSD/sys/dev/ixgbe/
HDixgbe_mbx.c597 u32 reg_offset = (vf_number < 32) ? 0 : 1; in ixgbe_check_for_rst_pf() local
606 vflre = IXGBE_READ_REG(hw, IXGBE_VFLRE(reg_offset)); in ixgbe_check_for_rst_pf()
611 vflre = IXGBE_READ_REG(hw, IXGBE_VFLREC(reg_offset)); in ixgbe_check_for_rst_pf()
619 IXGBE_WRITE_REG(hw, IXGBE_VFLREC(reg_offset), (1 << vf_shift)); in ixgbe_check_for_rst_pf()
/NextBSD/sys/contrib/alpine-hal/
HDal_hal_pcie.h832 unsigned int reg_offset);
848 unsigned int reg_offset,
HDal_hal_pcie.c2186 unsigned int reg_offset) in al_pcie_local_cfg_space_read() argument
2191 data = al_reg_read32(&regs->core_space[pcie_pf->pf_num].config_header[reg_offset]); in al_pcie_local_cfg_space_read()
2200 unsigned int reg_offset, in al_pcie_local_cfg_space_write() argument
2208 uint32_t *offset = &regs->core_space[pf_num].config_header[reg_offset]; in al_pcie_local_cfg_space_write()
/NextBSD/contrib/llvm/tools/lldb/source/Expression/
HDDWARFExpression.cpp520 int64_t reg_offset = m_data.GetSLEB128(&offset); in DumpLocation() local
528 s->Printf("[%s%+" PRIi64 "]", reg_info.name, reg_offset); in DumpLocation()
533 s->Printf("[%s%+" PRIi64 "]", reg_info.alt_name, reg_offset); in DumpLocation()
538 s->Printf("DW_OP_breg%i(0x%" PRIx64 ")", reg_num, reg_offset); in DumpLocation()
571 int64_t reg_offset = m_data.GetSLEB128(&offset); in DumpLocation() local
579 s->Printf("[%s%+" PRIi64 "]", reg_info.name, reg_offset); in DumpLocation()
584 s->Printf("[%s%+" PRIi64 "]", reg_info.alt_name, reg_offset); in DumpLocation()
589 s->Printf("DW_OP_bregx(reg=%" PRIu32 ",offset=%" PRIi64 ")", reg_num, reg_offset); in DumpLocation()
/NextBSD/contrib/llvm/tools/lldb/source/Plugins/Process/gdb-remote/
HDProcessGDBRemote.cpp537 uint32_t reg_offset = 0; in BuildDynamicRegisterInfo() local
561 reg_offset, // offset in BuildDynamicRegisterInfo()
592 if (reg_offset != offset) in BuildDynamicRegisterInfo()
594 reg_offset = offset; in BuildDynamicRegisterInfo()
659 reg_info.byte_offset = reg_offset; in BuildDynamicRegisterInfo()
661 reg_offset += reg_info.byte_size; in BuildDynamicRegisterInfo()
4145 uint32_t reg_offset = 0; in ParseRegisters() local
4147 …ldElementWithName("reg", [&target_info, &dyn_reg_info, &prev_reg_num, &reg_offset](const XMLNode &… in ParseRegisters()
4160 reg_offset, // offset in ParseRegisters()
4174 …nvalidate_regs, &encoding_set, &format_set, &reg_info, &prev_reg_num, &reg_offset](const llvm::Str… in ParseRegisters()
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/NextBSD/contrib/gdb/
HDFREEBSD-diffs198 +static int reg_offset[462] = {
268 + ofs = reg_offset[regno];
282 + ofs = reg_offset[regno];
287 + IA64_BSP_REGNUM in the reg_offset array above is that of the
291 + bsp += *((uint64_t*)((char *)regs + reg_offset[IA64_BSPSTORE_REGNUM]));
/NextBSD/sys/dev/e1000/
HDe1000_82575.c2260 u32 reg_val, reg_offset; in e1000_vmdq_set_anti_spoofing_pf() local
2264 reg_offset = E1000_DTXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2268 reg_offset = E1000_TXSWC; in e1000_vmdq_set_anti_spoofing_pf()
2274 reg_val = E1000_READ_REG(hw, reg_offset); in e1000_vmdq_set_anti_spoofing_pf()
2286 E1000_WRITE_REG(hw, reg_offset, reg_val); in e1000_vmdq_set_anti_spoofing_pf()
/NextBSD/contrib/gcc/config/mips/
HDmips.c480 unsigned int reg_offset; member
3793 info->reg_offset = (mips_abi == ABI_EABI && info->fpr_p in mips_arg_info()
3799 info->reg_offset += info->reg_offset & 1; in mips_arg_info()
3806 max_regs = MAX_ARGS_IN_REGISTERS - info->reg_offset; in mips_arg_info()
3834 cum->num_gprs = info.reg_offset + info.reg_words; in function_arg_advance()
3868 if (info.reg_offset == MAX_ARGS_IN_REGISTERS) in function_arg()
3921 reg = gen_rtx_REG (DFmode, FP_ARG_FIRST + info.reg_offset + i); in function_arg()
3923 reg = gen_rtx_REG (DImode, GP_ARG_FIRST + info.reg_offset + i); in function_arg()
3947 reg = FP_ARG_FIRST + info.reg_offset; in function_arg()
3969 return gen_rtx_REG (mode, GP_ARG_FIRST + info.reg_offset); in function_arg()
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/NextBSD/sys/dev/bxe/
HDbxe.c8399 int reg_offset; in bxe_attn_int_deasserted2() local
8472 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : in bxe_attn_int_deasserted2()
8475 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted2()
8477 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted2()
8490 int reg_offset; in bxe_attn_int_deasserted1() local
8503 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : in bxe_attn_int_deasserted1()
8506 val = REG_RD(sc, reg_offset); in bxe_attn_int_deasserted1()
8508 REG_WR(sc, reg_offset, val); in bxe_attn_int_deasserted1()
8521 int reg_offset; in bxe_attn_int_deasserted0() local
8524 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : in bxe_attn_int_deasserted0()
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HDecore_sp.c852 uint32_t reg_offset = ECORE_PORT_ID(sc) ? NIG_REG_LLH1_FUNC_MEM : in ecore_set_mac_in_nig() local
866 reg_offset += 8*index; in ecore_set_mac_in_nig()
872 ECORE_REG_WR_DMAE_LEN(sc, reg_offset, wb_data, 2); in ecore_set_mac_in_nig()
/NextBSD/contrib/binutils/gas/config/
HDtc-score.c163 unsigned long reg_offset; member
5899 cur_proc_ptr->reg_offset = off; in s_score_mask()
6001 cur_proc_ptr->reg_offset = 0xdeadbeaf; in s_score_ent()
6124 (cur_proc_ptr->reg_offset == 0xdeadbeaf) || in s_score_end()
6141 md_number_to_chars (fragp + 4, (valueT) cur_proc_ptr->reg_offset, 4); in s_score_end()
HDtc-mips.c14667 unsigned long reg_offset; member
14902 md_number_to_chars (fragp + 4, cur_proc_ptr->reg_offset, 4); in s_mips_end()
15042 cur_proc_ptr->reg_offset = off; in s_mips_mask()
/NextBSD/contrib/gcc/config/arm/
HDarm.c14224 int reg_offset = REGNO (offset); in thumb_load_double_from_address() local
14231 reg_dest + 1, reg_base, reg_offset); in thumb_load_double_from_address()

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