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Searched refs:regVal (Results 1 – 5 of 5) sorted by relevance

/NextBSD/sys/dev/ath/ath_hal/ar9002/
HDar9285_diversity.c64 int regVal; in ar9285SetAntennaSwitch() local
86 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9285SetAntennaSwitch()
87 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); in ar9285SetAntennaSwitch()
91 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); in ar9285SetAntennaSwitch()
96 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285SetAntennaSwitch()
97 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9285SetAntennaSwitch()
98 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); in ar9285SetAntennaSwitch()
99 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); in ar9285SetAntennaSwitch()
105 regVal |= SM(HAL_ANT_DIV_COMB_LNA2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285SetAntennaSwitch()
106 regVal |= SM(HAL_ANT_DIV_COMB_LNA1, AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9285SetAntennaSwitch()
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HDar9285_btcoex.c47 u_int32_t regVal; in ar9285BTCoexAntennaDiversity() local
105 regVal = OS_REG_READ(ah, AR_PHY_MULTICHAIN_GAIN_CTL); in ar9285BTCoexAntennaDiversity()
106 regVal &= (~(AR_PHY_9285_ANT_DIV_CTL_ALL)); in ar9285BTCoexAntennaDiversity()
111 regVal &= (~(AR_PHY_9285_FAST_DIV_BIAS)); in ar9285BTCoexAntennaDiversity()
113 regVal |= SM(ant_div_control1, AR_PHY_9285_ANT_DIV_CTL); in ar9285BTCoexAntennaDiversity()
114 regVal |= SM(ant_div_control2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9285BTCoexAntennaDiversity()
115 regVal |= SM((ant_div_control2 >> 2), AR_PHY_9285_ANT_DIV_MAIN_LNACONF); in ar9285BTCoexAntennaDiversity()
116 regVal |= SM((ant_div_control1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); in ar9285BTCoexAntennaDiversity()
117 regVal |= SM((ant_div_control1 >> 2), AR_PHY_9285_ANT_DIV_MAIN_GAINTB); in ar9285BTCoexAntennaDiversity()
118 OS_REG_WRITE(ah, AR_PHY_MULTICHAIN_GAIN_CTL, regVal); in ar9285BTCoexAntennaDiversity()
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HDar9285_cal.c51 uint32_t regVal; in ar9285_hw_pa_cal() local
74 regVal = OS_REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
75 regVal &= (~(0x1)); in ar9285_hw_pa_cal()
76 OS_REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
77 regVal = OS_REG_READ(ah, 0x9808); in ar9285_hw_pa_cal()
78 regVal |= (0x1 << 27); in ar9285_hw_pa_cal()
79 OS_REG_WRITE(ah, 0x9808, regVal); in ar9285_hw_pa_cal()
102 regVal = OS_REG_READ(ah, 0x7834); in ar9285_hw_pa_cal()
103 regVal |= (1 << (19 + i)); in ar9285_hw_pa_cal()
104 OS_REG_WRITE(ah, 0x7834, regVal); in ar9285_hw_pa_cal()
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/NextBSD/sys/dev/pms/RefTisa/sallsdk/spc/
HDsahw.c574 bit32 regVal; in siChipResetV() local
579 regVal = ossaHwRegReadExt(agRoot,PCIBAR0 ,V_SoftResetRegister ); in siChipResetV()
581 SA_DBG1(("siChipResetV: signature %X V_SoftResetRegister %X\n",signature,regVal)); in siChipResetV()
585 SA_DBG1(("siChipResetV: SPC_SOFT_RESET_SIGNATURE 0x%X\n",regVal)); in siChipResetV()
586 regVal = SPCv_Reset_Write_NormalReset; in siChipResetV()
590 SA_DBG1(("siChipResetV: SPCv load HDA 0x%X\n",regVal)); in siChipResetV()
591 regVal = SPCv_Reset_Write_SoftResetHDA; in siChipResetV()
595 SA_DBG1(("siChipResetV: Invalid SIGNATURE 0x%X regVal 0x%X a\n",signature ,regVal)); in siChipResetV()
596 regVal = 1; in siChipResetV()
600 ossaHwRegWriteExt(agRoot, PCIBAR0, V_SoftResetRegister, regVal); /* siChipResetV */ in siChipResetV()
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/NextBSD/sys/arm/xscale/ixp425/
HDixp425_npe.c224 uint32_t ctxtNum, uint32_t *regVal);
226 uint32_t regAddr, uint32_t regVal,
681 uint32_t regVal = bp->ctxtRegEntry[i].value; in npe_load_stateinfo() local
709 if (npe_ctx_reg_write(sc, cNum, reg, regVal, verify) != 0) { in npe_load_stateinfo()
833 uint32_t regVal; in npe_cpu_reset() local
920 regVal = ixNpeDlCtxtRegResetValues[ctxtReg]; in npe_cpu_reset()
922 regVal, TRUE); in npe_cpu_reset()
1215 uint32_t ctxtNum, uint32_t *regVal) in npe_logical_reg_read() argument
1250 *regVal = npe_reg_read(sc, IX_NPEDL_REG_OFFSET_EXDATA); in npe_logical_reg_read()
1253 *regVal = (*regVal >> (IX_NPEDL_REG_SIZE_WORD - regSize)) & mask; in npe_logical_reg_read()
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