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Searched refs:rclk (Results 1 – 25 of 54) sorted by relevance

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/NextBSD/sys/dev/sio/
HDsio_puc.c68 uintptr_t rclk; in sio_puc_attach() local
71 &rclk) != 0) in sio_puc_attach()
72 rclk = DEFAULT_RCLK; in sio_puc_attach()
73 return (sioattach(dev, 0, rclk)); in sio_puc_attach()
80 uintptr_t rclk, type; in sio_puc_probe() local
90 if (BUS_READ_IVAR(parent, dev, PUC_IVAR_CLOCK, &rclk)) in sio_puc_probe()
91 rclk = DEFAULT_RCLK; in sio_puc_probe()
95 error = sioprobe(dev, 0, rclk, 1); in sio_puc_probe()
HDsio.c239 u_long rclk; member
260 static u_int siodivisor(u_long rclk, speed_t speed);
421 sioprobe(dev, xrid, rclk, noprobe) in sioprobe() argument
424 u_long rclk;
460 if (rclk == 0)
461 rclk = DEFAULT_RCLK;
462 com->rclk = rclk;
599 divisor = siodivisor(rclk, SIO_TEST_SPEED);
868 sioattach(dev, xrid, rclk) in sioattach() argument
871 u_long rclk;
[all …]
HDsiovar.h62 int sioattach(device_t dev, int xrid, u_long rclk);
64 int sioprobe(device_t dev, int xrid, u_long rclk, int noprobe);
/NextBSD/sys/arm/xscale/ixp425/
HDuart_bus_ixp425.c72 u_int rclk; in uart_ixp425_probe() local
76 if (resource_int_value("uart", unit, "rclk", &rclk)) in uart_ixp425_probe()
77 rclk = IXP425_UART_FREQ; in uart_ixp425_probe()
79 device_printf(dev, "rclk %u\n", rclk); in uart_ixp425_probe()
81 return uart_bus_probe(dev, 0, rclk, 0, 0); in uart_ixp425_probe()
/NextBSD/sys/dev/uart/
HDuart_bus_puc.c70 uintptr_t rclk, type; in uart_puc_probe() local
82 if (BUS_READ_IVAR(parent, dev, PUC_IVAR_CLOCK, &rclk)) in uart_puc_probe()
83 rclk = 0; in uart_puc_probe()
84 return (uart_bus_probe(dev, 0, rclk, 0, 0)); in uart_puc_probe()
HDuart_cpu_fdt.c135 pcell_t shift, br, rclk; in uart_cpu_getdev() local
182 if ((err = uart_fdt_get_clock(node, &rclk)) != 0) in uart_cpu_getdev()
190 rclk = 0; in uart_cpu_getdev()
210 di->bas.rclk = (u_int)rclk; in uart_cpu_getdev()
HDuart_dev_quicc.c58 quicc_divisor(int rclk, int baudrate) in quicc_divisor() argument
65 divisor = rclk / baudrate / 16; in quicc_divisor()
72 act_baud = rclk / (((divisor >> 1) + 1) << ((divisor & 1) ? 8 : 4)); in quicc_divisor()
92 divisor = quicc_divisor(bas->rclk, baudrate); in quicc_param()
129 if (bas->rclk == 0) in quicc_setup()
130 bas->rclk = DEFAULT_RCLK; in quicc_setup()
362 baudrate = bas->rclk / (brg * 16); in quicc_bus_ioctl()
HDuart_dev_msm.c154 if (bas->rclk == 0) in msm_init()
155 bas->rclk = DEF_CLK; in msm_init()
157 KASSERT(bas->rclk != 0, ("msm_init: Invalid rclk")); in msm_init()
437 if (sc->sc_bas.rclk == 0) in msm_bus_param()
438 sc->sc_bas.rclk = DEF_CLK; in msm_bus_param()
440 KASSERT(sc->sc_bas.rclk != 0, ("msm_init: Invalid rclk")); in msm_bus_param()
HDuart_cpu_powerpc.c189 if (OF_getprop(input, "clock-frequency", &di->bas.rclk, in uart_cpu_getdev()
190 sizeof(di->bas.rclk)) == -1) in uart_cpu_getdev()
191 di->bas.rclk = 230400; in uart_cpu_getdev()
HDuart_dev_z8530.c73 z8530_divisor(int rclk, int baudrate) in z8530_divisor() argument
80 divisor = (rclk + baudrate) / (baudrate << 1) - 2; in z8530_divisor()
83 act_baud = rclk / 2 / (divisor + 2); in z8530_divisor()
128 divisor = z8530_divisor(bas->rclk, baudrate); in z8530_param()
162 if (bas->rclk == 0) in z8530_setup()
163 bas->rclk = DEFAULT_RCLK; in z8530_setup()
411 baudrate = bas->rclk / 2 / (divisor + 2); in z8530_bus_ioctl()
HDuart_dev_ns8250.c116 return (16000000 * divisor / bas->rclk); in ns8250_delay()
117 return (16000 * divisor / (bas->rclk / 1000)); in ns8250_delay()
121 ns8250_divisor(int rclk, int baudrate) in ns8250_divisor() argument
129 divisor = (rclk / (baudrate << 3) + 1) >> 1; in ns8250_divisor()
132 actual_baud = rclk / (divisor << 4); in ns8250_divisor()
230 divisor = ns8250_divisor(bas->rclk, baudrate); in ns8250_param()
293 if (bas->rclk == 0) in ns8250_init()
294 bas->rclk = DEFAULT_RCLK; in ns8250_init()
612 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; in ns8250_bus_ioctl()
HDuart_dev_sab82532.c65 return (16000000 * divisor / bas->rclk); in sab82532_delay()
69 sab82532_divisor(int rclk, int baudrate) in sab82532_divisor() argument
77 divisor = (rclk / (baudrate << 3) + 1) >> 1; in sab82532_divisor()
87 act_baud = rclk / (act_div << 4); in sab82532_divisor()
149 divisor = sab82532_divisor(bas->rclk, baudrate); in sab82532_param()
201 if (bas->rclk == 0) in sab82532_init()
202 bas->rclk = DEFAULT_RCLK; in sab82532_init()
HDuart_core.c441 uart_bus_probe(device_t dev, int regshft, int rclk, int rid, int chan) in uart_bus_probe() argument
499 sc->sc_bas.rclk = (rclk == 0) ? sc->sc_class->uc_rclk : rclk; in uart_bus_probe()
506 sysdev->bas.rclk = sc->sc_bas.rclk; in uart_bus_probe()
HDuart_bus_pci.c71 int rclk; member
198 result = uart_bus_probe(dev, id->regshft, id->rclk, id->rid, 0); in uart_pci_probe()
HDuart_dev_lpc.c92 return (16000000 / (bas->rclk * x / y)); in lpc_ns8250_delay()
96 lpc_ns8250_divisor(int rclk, int baudrate, int *x, int *y) in lpc_ns8250_divisor() argument
232 lpc_ns8250_divisor(bas->rclk, baudrate, &xdiv, &ydiv); in lpc_ns8250_param()
305 if (bas->rclk == 0) in lpc_ns8250_init()
306 bas->rclk = DEFAULT_RCLK; in lpc_ns8250_init()
619 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; in lpc_ns8250_bus_ioctl()
HDuart_subr.c234 di->bas.rclk = 0; in uart_getenv()
274 di->bas.rclk = uart_parse_long(&spec); in uart_getenv()
/NextBSD/sys/dev/scc/
HDscc_bfe_quicc.c50 uintptr_t devtype, rclk; in scc_quicc_probe() local
65 if (BUS_READ_IVAR(parent, dev, QUICC_IVAR_BRGCLK, &rclk)) in scc_quicc_probe()
66 rclk = 0; in scc_quicc_probe()
67 return (scc_bfe_probe(dev, 0, rclk, 0)); in scc_quicc_probe()
HDscc_bfe.h44 u_int rclk; member
143 int scc_bfe_probe(device_t dev, u_int regshft, u_int rclk, u_int rid);
HDscc_core.c350 scc_bfe_probe(device_t dev, u_int regshft, u_int rclk, u_int rid) in scc_bfe_probe() argument
400 sc->sc_bas.rclk = rclk; in scc_bfe_probe()
480 *result = sc->sc_bas.rclk; in scc_bus_read_ivar()
/NextBSD/sys/arm/samsung/exynos/
HDexynos_uart.c125 brd = sscomspeed(baudrate, bas->rclk); in exynos4210_uart_param()
152 if (bas->rclk == 0) in exynos4210_init()
153 bas->rclk = DEF_CLK; in exynos4210_init()
155 KASSERT(bas->rclk != 0, ("exynos4210_init: Invalid rclk")); in exynos4210_init()
306 if (sc->sc_bas.rclk == 0) in exynos4210_bus_param()
307 sc->sc_bas.rclk = DEF_CLK; in exynos4210_bus_param()
309 KASSERT(sc->sc_bas.rclk != 0, ("exynos4210_init: Invalid rclk")); in exynos4210_bus_param()
/NextBSD/sys/arm/amlogic/aml8726/
HDuart_dev_aml8726.c83 aml8726_uart_divisor(int rclk, int baudrate) in aml8726_uart_divisor() argument
92 divisor = ((rclk << 1) + baudrate) / (baudrate << 1); in aml8726_uart_divisor()
95 actual_baud = rclk / divisor; in aml8726_uart_divisor()
150 if (baudrate > 0 && bas->rclk != 0) { in aml8726_uart_param()
151 divisor = aml8726_uart_divisor(bas->rclk / 4, baudrate) - 1; in aml8726_uart_param()
379 bas->rclk = aml8726_uart_bus_clk(ofw_bus_get_node(sc->sc_dev)); in aml8726_uart_bus_attach()
381 if (bas->rclk == 0) { in aml8726_uart_bus_attach()
523 baudrate = bas->rclk / 4 / (divisor + 1); in aml8726_uart_bus_ioctl()
/NextBSD/sys/mips/cavium/
HDuart_dev_oct16550.c123 if(!bas->rclk) in oct16550_delay()
128 return (16000000 * divisor / bas->rclk); in oct16550_delay()
129 return (16000 * divisor / (bas->rclk / 1000)); in oct16550_delay()
134 oct16550_divisor (int rclk, int baudrate) in oct16550_divisor() argument
142 divisor = (rclk / (baudrate << 3) + 1) >> 1; in oct16550_divisor()
145 actual_baud = rclk / (divisor << 4); in oct16550_divisor()
243 divisor = oct16550_divisor(bas->rclk, baudrate); in oct16550_param()
584 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; in oct16550_bus_ioctl()
664 bas->rclk = uart_oct16550_class.uc_rclk = cvmx_clock_get_rate(CVMX_CLOCK_SCLK); in oct16550_bus_probe()
/NextBSD/sys/pc98/cbus/
HDsio.c321 u_long rclk; member
348 static u_int siodivisor(u_long rclk, speed_t speed);
598 u_long rclk; member
754 sioprobe(dev, xrid, rclk, noprobe) in sioprobe() argument
757 u_long rclk;
831 if (!IS_8251(iod.if_type) && rclk == 0)
832 rclk = if_16550a_type[iod.if_type & 0x0f].rclk;
834 if (rclk == 0)
835 rclk = DEFAULT_RCLK;
837 com->rclk = rclk;
[all …]
/NextBSD/sys/arm/conf/
HDCAMBRIA.hints21 #hint.uart.1.rclk=1843200
26 #hint.uart.2.rclk=1843200
/NextBSD/sys/arm/xscale/pxa/
HDuart_cpu_pxa.c60 di->bas.rclk = PXA2X0_COM_FREQ; in uart_cpu_getdev()

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