1 /*- 2 * Redistribution and use in source and binary forms, with or without 3 * modification, are permitted provided that the following conditions 4 * are met: 5 * 1. Redistributions of source code must retain all copyright 6 * notices, this list of conditions and the following disclaimer. 7 * 2. The names of the authors may not be used to endorse or promote products 8 * derived from this software without specific prior written permission 9 * 10 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 12 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 13 * IN NO EVENT SHALL THE AUTHORS BE LIABLE FOR ANY DIRECT, INDIRECT, 14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 16 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 17 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 20 * 21 * $FreeBSD$ 22 */ 23 /* Definitions for WaveLAN driver */ 24 25 #ifndef _IF_WL_H 26 #define _IF_WL_H 27 28 #define STATUS_TRIES 15000 29 30 #define N_FD 100 31 #define N_RBD 100 32 #define N_TBD 72 33 #define RCVBUFSIZE 540 34 #define I82586NULL 0xffff 35 36 #define DSF_RUNNING 1 37 38 #define MOD_ENAL 1 39 #define MOD_PROM 2 40 41 typedef struct { 42 rbd_t r; 43 char rbd_pad[2]; 44 char rbuffer[RCVBUFSIZE]; 45 } ru_t; 46 47 /* Board 64k RAM layout. Offsets from 0x0000 */ 48 49 #define OFFSET_RU 0x0000 /* 0x64 * fd_t = 0x898 */ 50 #define OFFSET_RBD 0x0900 /* 0x64 * ru_t = 0xd7a0 */ 51 #define OFFSET_CU 0xe0a0 /* 0x100 */ 52 #define OFFSET_TBD 0xe1a0 /* 0x48 * tbd_t = 0x240 */ 53 #define OFFSET_TBUF 0xe3e0 /* 0x1bfe */ 54 #define OFFSET_SCB 0xffde /* 0x1 * scb_t = 0x10 */ 55 #define OFFSET_ISCP 0xffee /* 0x1 * iscp_t = 0x8 */ 56 #define OFFSET_SCP 0xfff6 /* 0x1 * scp_t = 0xa */ 57 58 /* WaveLAN host interface definitions */ 59 60 #define HACR 0x0 /* Host Adapter Command Register */ 61 #define HASR 0x0 /* Host Adapter Status Register */ 62 #define MMCR 0x2 /* Modem Management Ctrl Register */ 63 #define PIOR0 0x4 /* Program I/O Address Register 0 */ 64 #define PIOP0 0x6 /* Program I/O Port 0 */ 65 #define PIOR1 0x8 /* Program I/O Address Register 1 */ 66 #define PIOP1 0xa /* Program I/O Port 1 */ 67 #define PIOR2 0xc /* Program I/O Address Register 2 */ 68 #define PIOP2 0xe /* Program I/O Port 2 */ 69 70 /* Program I/O Mode Register values */ 71 72 #define STATIC_PIO 0 /* Mode 1: static mode */ 73 #define AUTOINCR_PIO 1 /* Mode 2: auto increment mode */ 74 #define AUTODECR_PIO 2 /* Mode 3: auto decrement mode */ 75 #define PARAM_ACCESS_PIO 3 /* Mode 4: LAN parameter access mode */ 76 #define PIO_MASK 3 /* register mask */ 77 #define PIOM(cmd,piono) ((u_short)cmd << 10 << (piono * 2)) 78 79 /* Host Adapter status register definitions */ 80 81 #define HASR_INTR 0x0001 /* Interrupt request from 82586 */ 82 #define HASR_MMC_INTR 0x0002 /* Interrupt request from MMC */ 83 #define HASR_MMC_BUSY 0x0004 /* MMC busy indication */ 84 #define HASR_PARA_BUSY 0x0008 /* LAN parameter storage area busy */ 85 86 /* Host Adapter command register definitions */ 87 88 #define HACR_RESET 0x0001 /* Reset board */ 89 #define HACR_CA 0x0002 /* Set Channel Attention for 82586 */ 90 #define HACR_16BITS 0x0004 /* 1==16 bits operation, 0==8 bits */ 91 #define HACR_OUT1 0x0008 /* General purpose output pin */ 92 #define HACR_OUT2 0x0010 /* General purpose output pin */ 93 #define HACR_MASK_82586 0x0020 /* Mask 82586 interrupts, 1==unmask */ 94 #define HACR_MASK_MMC 0x0040 /* Mask MMC interrupts, 1==unmask */ 95 #define HACR_INTR_CLEN 0x0080 /* interrupt status clear enable */ 96 97 #define HACR_DEFAULT (HACR_OUT1 | HACR_OUT2 | HACR_16BITS | PIOM(STATIC_PIO, 0) | PIOM(AUTOINCR_PIO, 1) | PIOM(PARAM_ACCESS_PIO, 2)) 98 #define HACR_INTRON (HACR_MASK_82586 | HACR_MASK_MMC | HACR_INTR_CLEN) 99 100 #define WL_READ_1(sc, reg) bus_read_1((sc)->res_ioport, (reg)) 101 #define WL_READ_2(sc, reg) bus_read_2((sc)->res_ioport, (reg)) 102 #define WL_READ_MULTI_2(sc, reg, buf, len) \ 103 bus_read_multi_2((sc)->res_ioport, (reg), (uint16_t *)(buf), (len)) 104 #define WL_WRITE_1(sc, reg, val) \ 105 bus_write_1((sc)->res_ioport, (reg), (val)) 106 #define WL_WRITE_2(sc, reg, val) \ 107 bus_write_2((sc)->res_ioport, (reg), (val)) 108 #define WL_WRITE_MULTI_2(sc, reg, buf, len) \ 109 bus_write_multi_2((sc)->res_ioport, (reg), (uint16_t *)(buf), (len)) 110 111 #define CMD(sc) \ 112 { \ 113 WL_WRITE_2(sc, HACR, sc->hacr); \ 114 /* delay for 50 us, might only be needed sometimes */ \ 115 DELAY(DELAYCONST); \ 116 } 117 118 /* macro for setting the channel attention bit. No delays here since 119 * it is used in critical sections 120 */ 121 #define SET_CHAN_ATTN(sc) \ 122 { \ 123 WL_WRITE_2(sc, HACR, sc->hacr | HACR_CA); \ 124 } 125 126 127 #define MMC_WRITE(cmd,val) \ 128 while (WL_READ_2(sc, HASR) & HASR_MMC_BUSY) ; \ 129 WL_WRITE_2(sc, MMCR, \ 130 (u_short)(((u_short)(val) << 8) | ((cmd) << 1) | 1)) 131 132 #endif /* _IF_WL_H */ 133 134