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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCScheduleE5500.td178 2>, // 2 micro-ops
184 2>, // 2 micro-ops
198 2>, // 2 micro-ops
204 2>, // 2 micro-ops
214 2>, // 2 micro-ops
230 2>, // 2 micro-ops
236 2>, // 2 micro-ops
243 2>, // 2 micro-ops
250 2>, // 2 micro-ops
260 2>, // 2 micro-ops
[all …]
HDPPCScheduleE500mc.td149 2>, // 2 micro-ops
155 2>, // 2 micro-ops
165 2>, // 2 micro-ops
181 2>, // 2 micro-ops
193 2>, // 2 micro-ops
200 2>, // 2 micro-ops
313 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
/NextBSD/contrib/llvm/tools/clang/lib/Basic/
HDVersionTuple.cpp60 unsigned major = 0, minor = 0, micro = 0, build = 0; in tryParse() local
83 if (parseInt(input, micro)) return true; in tryParse()
86 *this = VersionTuple(major, minor, micro); in tryParse()
98 *this = VersionTuple(major, minor, micro, build); in tryParse()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64SchedA57WriteRes.td19 // 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes.
24 // Define Generic 1 micro-op types
55 // Define Generic 2 micro-op types
178 // Define Generic 3 micro-op types
249 // Define Generic 4 micro-op types
316 // Define Generic 5 micro-op types
360 // Define Generic 6 micro-op types
407 // Define Generic 7 micro-op types
444 // Define Generic 8 micro-op types
470 // Define Generic 9 micro-op types
[all …]
HDAArch64SchedCyclone.td16 let IssueWidth = 6; // 6 micro-ops are dispatched per cycle.
103 // A single nop micro-op (uX).
107 // The move is replaced by a single nop micro-op.
116 // Move GPR is a register rename and single nop micro-op.
150 // ADD with shifted register operand is a single micro-op that
171 // EXTR Shifts a pair of registers and requires two micro-ops.
172 // The second micro-op is delayed, as modeled by ReadExtrHi.
250 // Read the (unshifted) base register Xn in the second micro-op one cycle later.
265 // LDP high register write is fused with the load, but a nop micro-op remains.
278 // Branches take a single micro-op.
[all …]
HDAArch64SchedA57.td19 // schedule micro-ops so that all three decoded each cycle are successfully
26 let MicroOpBufferSize = 128; // 128 micro-op re-order buffer
38 // micro-ops wait for their operands and then issue out-of-order.
40 def A57UnitB : ProcResource<1>; // Type B micro-ops
41 def A57UnitI : ProcResource<2>; // Type I micro-ops
42 def A57UnitM : ProcResource<1>; // Type M micro-ops
43 def A57UnitL : ProcResource<1>; // Type L micro-ops
44 def A57UnitS : ProcResource<1>; // Type S micro-ops
45 def A57UnitX : ProcResource<1>; // Type X micro-ops
46 def A57UnitW : ProcResource<1>; // Type W micro-ops
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86SchedSandyBridge.td16 // All x86 instructions are modeled as a single micro-op, and SB can decode 4
18 // FIXME: Identify instructions that aren't a single fused micro-op.
34 // Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
50 // Many micro-ops are capable of issuing on multiple ports.
68 // Instructions with folded loads are usually micro-fused, so they only appear
69 // as two micro-ops when queued in the reservation station.
HDX86ScheduleSLM.td16 // All x86 instructions are modeled as a single micro-op, and SLM can decode 2
34 // Silvermont has 5 reservation stations for micro-ops
42 // Many micro-ops are capable of issuing on multiple ports.
55 // Instructions with folded loads are usually micro-fused, so they only appear
56 // as two micro-ops when queued in the reservation station.
HDX86ScheduleBtVer2.td17 // All x86 instructions are modeled as a single micro-op, and btver2 can
33 // Jaguar can issue up to 6 micro-ops in one cycle
73 // Instructions with folded loads are usually micro-fused, so they only appear
74 // as two micro-ops when dispatched by the schedulers.
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSchedule.td78 int IssueWidth = -1; // Max micro-ops that may be scheduled per cycle.
81 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
82 int LoopMicroOpBufferSize = -1; // Max micro-ops that can be buffered for
143 // differently. Here we refer to stage between decoding into micro-ops
268 // By default, each SchedWrite takes one micro-op, which is counted
270 // write multiple registers with a single micro-op, the subtarget
271 // should define one of the writes to be zero micro-ops. If a
272 // subtarget requires multiple micro-ops to write a single result, it
277 // operands. The scheduler assumes that all micro-ops must be
278 // dispatched in the same cycle. These micro-ops may be required to
HDTargetItinerary.td86 // NumMicroOps represents the number of micro-operations that each instruction
88 // instruction can decode into variable number of micro-ops and it must be
/NextBSD/sys/dev/isp/
HDispvar.h713 #define ISP_FW_NEWER_THAN(i, major, minor, micro) \ argument
714 (ISP_FW_REVX((i)->isp_fwrev) > ISP_FW_REV(major, minor, micro))
715 #define ISP_FW_OLDER_THAN(i, major, minor, micro) \ argument
716 (ISP_FW_REVX((i)->isp_fwrev) < ISP_FW_REV(major, minor, micro))
/NextBSD/contrib/bsnmp/
HDFREEBSD-upgrade3 This is the Begemot micro-SNMP daemon. It is the base for the ILMI daemon
/NextBSD/sys/gnu/dts/arm/
HDsun7i-a20-olinuxino-micro.dts25 compatible = "olimex,a20-olinuxino-micro", "allwinner,sun7i-a20";
230 label = "a20-olinuxino-micro:green:usr";
HDsun5i-a13-olinuxino-micro.dts58 compatible = "olimex,a13-olinuxino-micro", "allwinner,sun5i-a13";
142 label = "a13-olinuxino-micro:green:power";
HDsun5i-a10s-olinuxino-micro.dts60 compatible = "olimex,a10s-olinuxino-micro", "allwinner,sun5i-a10s";
237 label = "a10s-olinuxino-micro:green:usr";
/NextBSD/contrib/subversion/subversion/libsvn_subr/
HDsysinfo.c911 unsigned int major, minor, micro, nano; in file_version_number() local
933 micro = (info.dwFileVersionLS >> 16) & 0xFFFF; in file_version_number()
938 if (!micro) in file_version_number()
941 return apr_psprintf(pool, "%u.%u.%u", major, minor, micro); in file_version_number()
943 return apr_psprintf(pool, "%u.%u.%u.%u", major, minor, micro, nano); in file_version_number()
/NextBSD/contrib/tcsh/nls/greek/
HDset245 42 Tο wakeup flag του αριθ. ομάδας micro-tasking έγινε set
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMSchedule.td24 // and one cycle after the result in Rn is available. The micro-ops can execute
26 // To model this, we need to express that we need to dispatch two micro-ops,
50 // NumMicroOps = 2; // Dispatch 2 micro-ops.
/NextBSD/contrib/tcsh/nls/german/
HDset245 42 micro-tasking group-no wakeup flag set
/NextBSD/contrib/tcsh/nls/russian/
HDset245 42 micro-tasking group-no wakeup flag set
/NextBSD/contrib/tcsh/nls/ukrainian/
HDset245 42 micro-tasking group-no wakeup flag set
/NextBSD/sys/mips/nlm/
HDfiles.xlp19 # Network driver and micro-core code
/NextBSD/contrib/ncurses/include/
HDCaps.aix4243 cr_cancels_micro_mode crxm bool YB - - ----- using cr turns off micro mode
299 micro_col_size mcs num Yf - - ----- character step size when in micro mode
300 micro_line_size mls num Yg - - ----- line step size when in micro mode
749 enter_micro_mode smicm str ZJ - - ----- Start micro-motion mode
759 exit_micro_mode rmicm str ZT - - ----- End micro-motion mode
764 micro_column_address mhpa str ZY - - ----- Like column_address in micro mode
765 micro_down mcud1 str ZZ - - ----- Like cursor_down in micro mode
766 micro_left mcub1 str Za - - ----- Like cursor_left in micro mode
767 micro_right mcuf1 str Zb - - ----- Like cursor_right in micro mode
768 micro_row_address mvpa str Zc - - ----- Like row_address #1 in micro mode
[all …]
/NextBSD/contrib/tcsh/nls/C/
HDset245 42 micro-tasking group-no wakeup flag set

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