1 /*-
2 * ----------------------------------------------------------------------------
3 * "THE BEER-WARE LICENSE" (Revision 42):
4 * <phk@FreeBSD.org> wrote this file. As long as you retain this notice you
5 * can do whatever you want with this stuff. If we meet some day, and you think
6 * this stuff is worth it, you can buy me a beer in return. Poul-Henning Kamp
7 * ----------------------------------------------------------------------------
8 */
9
10 /*
11 * Driver for Siemens reference design card "Easy321-R1".
12 *
13 * This card contains a FALC54 E1/T1 framer and a MUNICH32X 32-channel HDLC
14 * controller.
15 *
16 * The driver supports E1 mode with up to 31 channels. We send CRC4 but don't
17 * check it coming in.
18 *
19 * The FALC54 and MUNICH32X have far too many registers and weird modes for
20 * comfort, so I have not bothered typing it all into a "fooreg.h" file,
21 * you will (badly!) need the documentation anyway if you want to mess with
22 * this gadget.
23 */
24
25 #include <sys/cdefs.h>
26 __FBSDID("$FreeBSD$");
27
28 /*
29 * Stuff to describe the MUNIC32X and FALC54 chips.
30 */
31
32 #define M32_CHAN 32 /* We have 32 channels */
33 #define M32_TS 32 /* We have 32 timeslots */
34
35 #define NG_MN_NODE_TYPE "mn"
36
37 #include <sys/param.h>
38 #include <sys/kernel.h>
39 #include <sys/sysctl.h>
40 #include <sys/bus.h>
41 #include <sys/mbuf.h>
42 #include <sys/systm.h>
43 #include <sys/malloc.h>
44
45 #include <dev/pci/pcireg.h>
46 #include <dev/pci/pcivar.h>
47 #include "pci_if.h"
48
49 #include <machine/bus.h>
50 #include <machine/resource.h>
51
52 #include <sys/rman.h>
53
54 #include <vm/vm.h>
55 #include <vm/pmap.h>
56
57 #include <netgraph/ng_message.h>
58 #include <netgraph/netgraph.h>
59
60
61 static int mn_maxlatency = 1000;
62 SYSCTL_INT(_debug, OID_AUTO, mn_maxlatency, CTLFLAG_RW,
63 &mn_maxlatency, 0,
64 "The number of milliseconds a packet is allowed to spend in the output queue. "
65 "If the output queue is longer than this number of milliseconds when the packet "
66 "arrives for output, the packet will be dropped."
67 );
68
69 #ifndef NMN
70 /* Most machines don't support more than 4 busmaster PCI slots, if even that many */
71 #define NMN 4
72 #endif
73
74 /* From: PEB 20321 data sheet, p187, table 22 */
75 struct m32xreg {
76 u_int32_t conf, cmd, stat, imask;
77 u_int32_t fill10, piqba, piql, fill1c;
78 u_int32_t mode1, mode2, ccba, txpoll;
79 u_int32_t tiqba, tiql, riqba, riql;
80 u_int32_t lconf, lccba, fill48, ltran;
81 u_int32_t ltiqba, ltiql, lriqba, lriql;
82 u_int32_t lreg0, lreg1, lreg2, lreg3;
83 u_int32_t lreg4, lreg5, lre6, lstat;
84 u_int32_t gpdir, gpdata, gpod, fill8c;
85 u_int32_t ssccon, sscbr, ssctb, sscrb;
86 u_int32_t ssccse, sscim, fillab, fillac;
87 u_int32_t iomcon1, iomcon2, iomstat, fillbc;
88 u_int32_t iomcit0, iomcit1, iomcir0, iomcir1;
89 u_int32_t iomtmo, iomrmo, filld8, filldc;
90 u_int32_t mbcmd, mbdata1, mbdata2, mbdata3;
91 u_int32_t mbdata4, mbdata5, mbdata6, mbdata7;
92 };
93
94 /* From: PEB 2254 data sheet, p80, table 10 */
95 struct f54wreg {
96 u_int16_t xfifo;
97 u_int8_t cmdr, mode, rah1, rah2, ral1, ral2;
98 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
99 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
100 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
101 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
102 u_int8_t test1, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr3;
103 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
104 u_int8_t lim2, fill39[7];
105 u_int8_t fill40[8];
106 u_int8_t fill48[8];
107 u_int8_t fill50[8];
108 u_int8_t fill58[8];
109 u_int8_t dec, fill61, test2, fill63[5];
110 u_int8_t fill68[8];
111 u_int8_t xs[16];
112 };
113
114 /* From: PEB 2254 data sheet, p117, table 10 */
115 struct f54rreg {
116 u_int16_t rfifo;
117 u_int8_t fill2, mode, rah1, rah2, ral1, ral2;
118 u_int8_t ipc, ccr1, ccr3, pre, rtr1, rtr2, rtr3, rtr4;
119 u_int8_t ttr1, ttr2, ttr3, ttr4, imr0, imr1, imr2, imr3;
120 u_int8_t imr4, fill19, fmr0, fmr1, fmr2, loop, xsw, xsp;
121 u_int8_t xc0, xc1, rc0, rc1, xpm0, xpm1, xpm2, tswm;
122 u_int8_t test, idle, xsa4, xsa5, xsa6, xsa7, xsa8, fmr13;
123 u_int8_t icb1, icb2, icb3, icb4, lim0, lim1, pcd, pcr;
124 u_int8_t lim2, fill39[7];
125 u_int8_t fill40[8];
126 u_int8_t fill48[4], frs0, frs1, rsw, rsp;
127 u_int16_t fec, cvc, cec1, ebc;
128 u_int16_t cec2, cec3;
129 u_int8_t rsa4, rsa5, rsa6, rsa7;
130 u_int8_t rsa8, rsa6s, tsr0, tsr1, sis, rsis;
131 u_int16_t rbc;
132 u_int8_t isr0, isr1, isr2, isr3, fill6c, fill6d, gis, vstr;
133 u_int8_t rs[16];
134 };
135
136 /* Transmit & receive descriptors */
137 struct trxd {
138 u_int32_t flags;
139 vm_offset_t next;
140 vm_offset_t data;
141 u_int32_t status; /* only used for receive */
142 struct mbuf *m; /* software use only */
143 struct trxd *vnext; /* software use only */
144 };
145
146 /* Channel specification */
147 struct cspec {
148 u_int32_t flags;
149 vm_offset_t rdesc;
150 vm_offset_t tdesc;
151 u_int32_t itbs;
152 };
153
154 struct m32_mem {
155 vm_offset_t csa;
156 u_int32_t ccb;
157 u_int32_t reserve1[2];
158 u_int32_t ts[M32_TS];
159 struct cspec cs[M32_CHAN];
160 vm_offset_t crxd[M32_CHAN];
161 vm_offset_t ctxd[M32_CHAN];
162 };
163
164 struct mn_softc;
165 struct sockaddr;
166 struct rtentry;
167
168 static int mn_probe(device_t self);
169 static int mn_attach(device_t self);
170 static void mn_create_channel(struct mn_softc *sc, int chan);
171 static int mn_reset(struct mn_softc *sc);
172 static struct trxd * mn_alloc_desc(void);
173 static void mn_free_desc(struct trxd *dp);
174 static void mn_intr(void *xsc);
175 static u_int32_t mn_parse_ts(const char *s, int *nbit);
176 #ifdef notyet
177 static void m32_dump(struct mn_softc *sc);
178 static void f54_dump(struct mn_softc *sc);
179 static void mn_fmt_ts(char *p, u_int32_t ts);
180 #endif /* notyet */
181 static void f54_init(struct mn_softc *sc);
182
183 static ng_constructor_t ngmn_constructor;
184 static ng_rcvmsg_t ngmn_rcvmsg;
185 static ng_shutdown_t ngmn_shutdown;
186 static ng_newhook_t ngmn_newhook;
187 static ng_connect_t ngmn_connect;
188 static ng_rcvdata_t ngmn_rcvdata;
189 static ng_disconnect_t ngmn_disconnect;
190
191 static struct ng_type mntypestruct = {
192 .version = NG_ABI_VERSION,
193 .name = NG_MN_NODE_TYPE,
194 .constructor = ngmn_constructor,
195 .rcvmsg = ngmn_rcvmsg,
196 .shutdown = ngmn_shutdown,
197 .newhook = ngmn_newhook,
198 .connect = ngmn_connect,
199 .rcvdata = ngmn_rcvdata,
200 .disconnect = ngmn_disconnect,
201 };
202
203 static MALLOC_DEFINE(M_MN, "mn", "Mx driver related");
204
205 #define NIQB 64
206
207 struct schan {
208 enum {DOWN, UP} state;
209 struct mn_softc *sc;
210 int chan;
211 u_int32_t ts;
212 char name[8];
213 struct trxd *r1, *rl;
214 struct trxd *x1, *xl;
215 hook_p hook;
216
217 time_t last_recv;
218 time_t last_rxerr;
219 time_t last_xmit;
220
221 u_long rx_error;
222
223 u_long short_error;
224 u_long crc_error;
225 u_long dribble_error;
226 u_long long_error;
227 u_long abort_error;
228 u_long overflow_error;
229
230 int last_error;
231 int prev_error;
232
233 u_long tx_pending;
234 u_long tx_limit;
235 };
236
237 enum framing {WHOKNOWS, E1, E1U, T1, T1U};
238
239 struct mn_softc {
240 int unit;
241 device_t dev;
242 struct resource *irq;
243 void *intrhand;
244 enum framing framing;
245 int nhooks;
246 void *m0v, *m1v;
247 vm_offset_t m0p, m1p;
248 struct m32xreg *m32x;
249 struct f54wreg *f54w;
250 struct f54rreg *f54r;
251 struct m32_mem m32_mem;
252 u_int32_t tiqb[NIQB];
253 u_int32_t riqb[NIQB];
254 u_int32_t piqb[NIQB];
255 u_int32_t ltiqb[NIQB];
256 u_int32_t lriqb[NIQB];
257 char name[8];
258 u_int32_t falc_irq, falc_state, framer_state;
259 struct schan *ch[M32_CHAN];
260 char nodename[NG_NODESIZ];
261 node_p node;
262
263 u_long cnt_fec;
264 u_long cnt_cvc;
265 u_long cnt_cec1;
266 u_long cnt_ebc;
267 u_long cnt_cec2;
268 u_long cnt_cec3;
269 u_long cnt_rbc;
270 };
271
272 static int
ngmn_constructor(node_p node)273 ngmn_constructor(node_p node)
274 {
275
276 return (EINVAL);
277 }
278
279 static int
ngmn_shutdown(node_p nodep)280 ngmn_shutdown(node_p nodep)
281 {
282
283 return (EINVAL);
284 }
285
286 static void
ngmn_config(node_p node,char * set,char * ret)287 ngmn_config(node_p node, char *set, char *ret)
288 {
289 struct mn_softc *sc;
290 enum framing wframing;
291
292 sc = NG_NODE_PRIVATE(node);
293
294 if (set != NULL) {
295 if (!strncmp(set, "line ", 5)) {
296 wframing = sc->framing;
297 if (!strcmp(set, "line e1")) {
298 wframing = E1;
299 } else if (!strcmp(set, "line e1u")) {
300 wframing = E1U;
301 } else {
302 strcat(ret, "ENOGROK\n");
303 return;
304 }
305 if (wframing == sc->framing)
306 return;
307 if (sc->nhooks > 0) {
308 sprintf(ret, "Cannot change line when %d hooks open\n", sc->nhooks);
309 return;
310 }
311 sc->framing = wframing;
312 #if 1
313 f54_init(sc);
314 #else
315 mn_reset(sc);
316 #endif
317 } else {
318 printf("%s CONFIG SET [%s]\n", sc->nodename, set);
319 strcat(ret, "ENOGROK\n");
320 return;
321 }
322 }
323
324 }
325
326 static int
ngmn_rcvmsg(node_p node,item_p item,hook_p lasthook)327 ngmn_rcvmsg(node_p node, item_p item, hook_p lasthook)
328 {
329 struct mn_softc *sc;
330 struct ng_mesg *resp = NULL;
331 struct schan *sch;
332 char *s, *r;
333 int pos, i;
334 struct ng_mesg *msg;
335
336 NGI_GET_MSG(item, msg);
337 sc = NG_NODE_PRIVATE(node);
338
339 if (msg->header.typecookie != NGM_GENERIC_COOKIE) {
340 NG_FREE_ITEM(item);
341 NG_FREE_MSG(msg);
342 return (EINVAL);
343 }
344
345 if (msg->header.cmd != NGM_TEXT_CONFIG &&
346 msg->header.cmd != NGM_TEXT_STATUS) {
347 NG_FREE_ITEM(item);
348 NG_FREE_MSG(msg);
349 return (EINVAL);
350 }
351
352 NG_MKRESPONSE(resp, msg, sizeof(struct ng_mesg) + NG_TEXTRESPONSE,
353 M_NOWAIT);
354 if (resp == NULL) {
355 NG_FREE_ITEM(item);
356 NG_FREE_MSG(msg);
357 return (ENOMEM);
358 }
359
360 if (msg->header.arglen)
361 s = (char *)msg->data;
362 else
363 s = NULL;
364 r = (char *)resp->data;
365 *r = '\0';
366
367 if (msg->header.cmd == NGM_TEXT_CONFIG) {
368 ngmn_config(node, s, r);
369 resp->header.arglen = strlen(r) + 1;
370 NG_RESPOND_MSG(i, node, item, resp);
371 NG_FREE_MSG(msg);
372 return (0);
373 }
374 pos = 0;
375 pos += sprintf(pos + r,"Framer status %b;\n", sc->framer_state, "\20"
376 "\40LOS\37AIS\36LFA\35RRA"
377 "\34AUXP\33NMF\32LMFA\31frs0.0"
378 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
379 "\24TS16LFA\23frs1.2\22XLS\21XLO"
380 "\20RS1\17rsw.6\16RRA\15RY0"
381 "\14RY1\13RY2\12RY3\11RY4"
382 "\10SI1\7SI2\6rsp.5\5rsp.4"
383 "\4rsp.3\3RSIF\2RS13\1RS15");
384 pos += sprintf(pos + r," Framing errors: %lu", sc->cnt_fec);
385 pos += sprintf(pos + r," Code Violations: %lu\n", sc->cnt_cvc);
386
387 pos += sprintf(pos + r," Falc State %b;\n", sc->falc_state, "\20"
388 "\40LOS\37AIS\36LFA\35RRA"
389 "\34AUXP\33NMF\32LMFA\31frs0.0"
390 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS"
391 "\24TS16LFA\23frs1.2\22XLS\21XLO"
392 "\20RS1\17rsw.6\16RRA\15RY0"
393 "\14RY1\13RY2\12RY3\11RY4"
394 "\10SI1\7SI2\6rsp.5\5rsp.4"
395 "\4rsp.3\3RSIF\2RS13\1RS15");
396 pos += sprintf(pos + r, " Falc IRQ %b\n", sc->falc_irq, "\20"
397 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
398 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
399 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
400 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
401 for (i = 0; i < M32_CHAN; i++) {
402 if (!sc->ch[i])
403 continue;
404 sch = sc->ch[i];
405
406 pos += sprintf(r + pos, " Chan %d <%s> ",
407 i, NG_HOOK_NAME(sch->hook));
408
409 pos += sprintf(r + pos, " Last Rx: ");
410 if (sch->last_recv)
411 pos += sprintf(r + pos, "%lu s",
412 (unsigned long)(time_second - sch->last_recv));
413 else
414 pos += sprintf(r + pos, "never");
415
416 pos += sprintf(r + pos, ", last RxErr: ");
417 if (sch->last_rxerr)
418 pos += sprintf(r + pos, "%lu s",
419 (unsigned long)(time_second - sch->last_rxerr));
420 else
421 pos += sprintf(r + pos, "never");
422
423 pos += sprintf(r + pos, ", last Tx: ");
424 if (sch->last_xmit)
425 pos += sprintf(r + pos, "%lu s\n",
426 (unsigned long)(time_second - sch->last_xmit));
427 else
428 pos += sprintf(r + pos, "never\n");
429
430 pos += sprintf(r + pos, " RX error(s) %lu", sch->rx_error);
431 pos += sprintf(r + pos, " Short: %lu", sch->short_error);
432 pos += sprintf(r + pos, " CRC: %lu", sch->crc_error);
433 pos += sprintf(r + pos, " Mod8: %lu", sch->dribble_error);
434 pos += sprintf(r + pos, " Long: %lu", sch->long_error);
435 pos += sprintf(r + pos, " Abort: %lu", sch->abort_error);
436 pos += sprintf(r + pos, " Overflow: %lu\n", sch->overflow_error);
437
438 pos += sprintf(r + pos, " Last error: %b Prev error: %b\n",
439 sch->last_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN",
440 sch->prev_error, "\20\7SHORT\5CRC\4MOD8\3LONG\2ABORT\1OVERRUN");
441 pos += sprintf(r + pos, " Xmit bytes pending %ld\n",
442 sch->tx_pending);
443 }
444 resp->header.arglen = pos + 1;
445
446 /* Take care of synchronous response, if any */
447 NG_RESPOND_MSG(i, node, item, resp);
448 NG_FREE_MSG(msg);
449 return (0);
450 }
451
452 static int
ngmn_newhook(node_p node,hook_p hook,const char * name)453 ngmn_newhook(node_p node, hook_p hook, const char *name)
454 {
455 u_int32_t ts, chan;
456 struct mn_softc *sc;
457 int nbit;
458
459 sc = NG_NODE_PRIVATE(node);
460
461 if (name[0] != 't' || name[1] != 's')
462 return (EINVAL);
463
464 ts = mn_parse_ts(name + 2, &nbit);
465 printf("%d bits %x\n", nbit, ts);
466 if (sc->framing == E1 && (ts & 1))
467 return (EINVAL);
468 if (sc->framing == E1U && nbit != 32)
469 return (EINVAL);
470 if (ts == 0)
471 return (EINVAL);
472 if (sc->framing == E1)
473 chan = ffs(ts) - 1;
474 else
475 chan = 1;
476 if (!sc->ch[chan])
477 mn_create_channel(sc, chan);
478 else if (sc->ch[chan]->state == UP)
479 return (EBUSY);
480 sc->ch[chan]->ts = ts;
481 sc->ch[chan]->hook = hook;
482 sc->ch[chan]->tx_limit = nbit * 8;
483 NG_HOOK_SET_PRIVATE(hook, sc->ch[chan]);
484 sc->nhooks++;
485 return(0);
486 }
487
488
489 static struct trxd *mn_desc_free;
490
491 static struct trxd *
mn_alloc_desc(void)492 mn_alloc_desc(void)
493 {
494 struct trxd *dp;
495
496 dp = mn_desc_free;
497 if (dp)
498 mn_desc_free = dp->vnext;
499 else
500 dp = (struct trxd *)malloc(sizeof *dp, M_MN, M_NOWAIT);
501 return (dp);
502 }
503
504 static void
mn_free_desc(struct trxd * dp)505 mn_free_desc(struct trxd *dp)
506 {
507 dp->vnext = mn_desc_free;
508 mn_desc_free = dp;
509 }
510
511 static u_int32_t
mn_parse_ts(const char * s,int * nbit)512 mn_parse_ts(const char *s, int *nbit)
513 {
514 unsigned r;
515 int i, j;
516 char *p;
517
518 r = 0;
519 j = -1;
520 *nbit = 0;
521 while(*s) {
522 i = strtol(s, &p, 0);
523 if (i < 0 || i > 31)
524 return (0);
525 while (j != -1 && j < i) {
526 r |= 1 << j++;
527 (*nbit)++;
528 }
529 j = -1;
530 r |= 1 << i;
531 (*nbit)++;
532 if (*p == ',') {
533 s = p + 1;
534 continue;
535 } else if (*p == '-') {
536 j = i + 1;
537 s = p + 1;
538 continue;
539 } else if (!*p) {
540 break;
541 } else {
542 return (0);
543 }
544 }
545 return (r);
546 }
547
548 #ifdef notyet
549 static void
mn_fmt_ts(char * p,u_int32_t ts)550 mn_fmt_ts(char *p, u_int32_t ts)
551 {
552 char *s;
553 int j;
554
555 s = "";
556 ts &= 0xffffffff;
557 for (j = 0; j < 32; j++) {
558 if (!(ts & (1 << j)))
559 continue;
560 sprintf(p, "%s%d", s, j);
561 p += strlen(p);
562 s = ",";
563 if (!(ts & (1 << (j+1))))
564 continue;
565 for (; j < 32; j++)
566 if (!(ts & (1 << (j+1))))
567 break;
568 sprintf(p, "-%d", j);
569 p += strlen(p);
570 s = ",";
571 }
572 }
573 #endif /* notyet */
574
575 /*
576 * OUTPUT
577 */
578
579 static int
ngmn_rcvdata(hook_p hook,item_p item)580 ngmn_rcvdata(hook_p hook, item_p item)
581 {
582 struct mbuf *m2;
583 struct trxd *dp, *dp2;
584 struct schan *sch;
585 struct mn_softc *sc;
586 int chan, pitch, len;
587 struct mbuf *m;
588
589 sch = NG_HOOK_PRIVATE(hook);
590 sc = sch->sc;
591 chan = sch->chan;
592
593 if (sch->state != UP) {
594 NG_FREE_ITEM(item);
595 return (0);
596 }
597 NGI_GET_M(item, m);
598 if (sch->tx_pending + m->m_pkthdr.len > sch->tx_limit * mn_maxlatency) {
599 NG_FREE_M(m);
600 NG_FREE_ITEM(item);
601 return (0);
602 }
603 NG_FREE_ITEM(item);
604 pitch = 0;
605 m2 = m;
606 dp2 = sc->ch[chan]->xl;
607 len = m->m_pkthdr.len;
608 while (len) {
609 dp = mn_alloc_desc();
610 if (!dp) {
611 pitch++;
612 m_freem(m);
613 sc->ch[chan]->xl = dp2;
614 dp = dp2->vnext;
615 while (dp) {
616 dp2 = dp->vnext;
617 mn_free_desc(dp);
618 dp = dp2;
619 }
620 sc->ch[chan]->xl->vnext = 0;
621 break;
622 }
623 dp->data = vtophys(m2->m_data);
624 dp->flags = m2->m_len << 16;
625 dp->flags += 1;
626 len -= m2->m_len;
627 dp->next = vtophys(dp);
628 dp->vnext = 0;
629 sc->ch[chan]->xl->next = vtophys(dp);
630 sc->ch[chan]->xl->vnext = dp;
631 sc->ch[chan]->xl = dp;
632 if (!len) {
633 dp->m = m;
634 dp->flags |= 0xc0000000;
635 dp2->flags &= ~0x40000000;
636 } else {
637 dp->m = 0;
638 m2 = m2->m_next;
639 }
640 }
641 if (pitch)
642 printf("%s%d: Short on mem, pitched %d packets\n",
643 sc->name, chan, pitch);
644 else {
645 #if 0
646 printf("%d = %d + %d (%p)\n",
647 sch->tx_pending + m->m_pkthdr.len,
648 sch->tx_pending , m->m_pkthdr.len, m);
649 #endif
650 sch->tx_pending += m->m_pkthdr.len;
651 sc->m32x->txpoll &= ~(1 << chan);
652 }
653 return (0);
654 }
655
656 /*
657 * OPEN
658 */
659 static int
ngmn_connect(hook_p hook)660 ngmn_connect(hook_p hook)
661 {
662 int i, nts, chan;
663 struct trxd *dp, *dp2;
664 struct mbuf *m;
665 struct mn_softc *sc;
666 struct schan *sch;
667 u_int32_t u;
668
669 sch = NG_HOOK_PRIVATE(hook);
670 chan = sch->chan;
671 sc = sch->sc;
672
673 if (sch->state == UP)
674 return (0);
675 sch->state = UP;
676
677 /* Count and configure the timeslots for this channel */
678 for (nts = i = 0; i < 32; i++)
679 if (sch->ts & (1 << i)) {
680 sc->m32_mem.ts[i] = 0x00ff00ff |
681 (chan << 24) | (chan << 8);
682 nts++;
683 }
684
685 /* Init the receiver & xmitter to HDLC */
686 sc->m32_mem.cs[chan].flags = 0x80e90006;
687 /* Allocate two buffers per timeslot */
688 if (nts == 32)
689 sc->m32_mem.cs[chan].itbs = 63;
690 else
691 sc->m32_mem.cs[chan].itbs = nts * 2;
692
693 /* Setup a transmit chain with one descriptor */
694 /* XXX: we actually send a 1 byte packet */
695 dp = mn_alloc_desc();
696 MGETHDR(m, M_WAITOK, MT_DATA);
697 m->m_pkthdr.len = 0;
698 dp->m = m;
699 dp->flags = 0xc0000000 + (1 << 16);
700 dp->next = vtophys(dp);
701 dp->vnext = 0;
702 dp->data = vtophys(sc->name);
703 sc->m32_mem.cs[chan].tdesc = vtophys(dp);
704 sc->ch[chan]->x1 = dp;
705 sc->ch[chan]->xl = dp;
706
707 /* Setup a receive chain with 5 + NTS descriptors */
708
709 dp = mn_alloc_desc();
710 m = NULL;
711 MGETHDR(m, M_WAITOK, MT_DATA);
712 MCLGET(m, M_WAITOK);
713 dp->m = m;
714 dp->data = vtophys(m->m_data);
715 dp->flags = 0x40000000;
716 dp->flags += 1600 << 16;
717 dp->next = vtophys(dp);
718 dp->vnext = 0;
719 sc->ch[chan]->rl = dp;
720
721 for (i = 0; i < (nts + 10); i++) {
722 dp2 = dp;
723 dp = mn_alloc_desc();
724 m = NULL;
725 MGETHDR(m, M_WAITOK, MT_DATA);
726 MCLGET(m, M_WAITOK);
727 dp->m = m;
728 dp->data = vtophys(m->m_data);
729 dp->flags = 0x00000000;
730 dp->flags += 1600 << 16;
731 dp->next = vtophys(dp2);
732 dp->vnext = dp2;
733 }
734 sc->m32_mem.cs[chan].rdesc = vtophys(dp);
735 sc->ch[chan]->r1 = dp;
736
737 /* Initialize this channel */
738 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
739 sc->m32x->cmd = 0x1;
740 DELAY(1000);
741 u = sc->m32x->stat;
742 if (!(u & 1))
743 printf("%s: init chan %d stat %08x\n", sc->name, chan, u);
744 sc->m32x->stat = 1;
745 /* probably not at splnet, force outward queueing */
746 NG_HOOK_FORCE_QUEUE(NG_HOOK_PEER(hook));
747
748 return (0);
749 }
750
751 /*
752 * CLOSE
753 */
754 static int
ngmn_disconnect(hook_p hook)755 ngmn_disconnect(hook_p hook)
756 {
757 int chan, i;
758 struct mn_softc *sc;
759 struct schan *sch;
760 struct trxd *dp, *dp2;
761 u_int32_t u;
762
763 sch = NG_HOOK_PRIVATE(hook);
764 chan = sch->chan;
765 sc = sch->sc;
766
767 if (sch->state == DOWN)
768 return (0);
769 sch->state = DOWN;
770
771 /* Set receiver & transmitter off */
772 sc->m32_mem.cs[chan].flags = 0x80920006;
773 sc->m32_mem.cs[chan].itbs = 0;
774
775 /* free the timeslots */
776 for (i = 0; i < 32; i++)
777 if (sc->ch[chan]->ts & (1 << i))
778 sc->m32_mem.ts[i] = 0x20002000;
779
780 /* Initialize this channel */
781 sc->m32_mem.ccb = 0x00008000 + (chan << 8);
782 sc->m32x->cmd = 0x1;
783 DELAY(30);
784 u = sc->m32x->stat;
785 if (!(u & 1))
786 printf("%s: zap chan %d stat %08x\n", sc->name, chan, u);
787 sc->m32x->stat = 1;
788
789 /* Free all receive descriptors and mbufs */
790 for (dp = sc->ch[chan]->r1; dp ; dp = dp2) {
791 if (dp->m)
792 m_freem(dp->m);
793 sc->ch[chan]->r1 = dp2 = dp->vnext;
794 mn_free_desc(dp);
795 }
796
797 /* Free all transmit descriptors and mbufs */
798 for (dp = sc->ch[chan]->x1; dp ; dp = dp2) {
799 if (dp->m) {
800 sc->ch[chan]->tx_pending -= dp->m->m_pkthdr.len;
801 m_freem(dp->m);
802 }
803 sc->ch[chan]->x1 = dp2 = dp->vnext;
804 mn_free_desc(dp);
805 }
806 sc->nhooks--;
807 return(0);
808 }
809
810 /*
811 * Create a new channel.
812 */
813 static void
mn_create_channel(struct mn_softc * sc,int chan)814 mn_create_channel(struct mn_softc *sc, int chan)
815 {
816 struct schan *sch;
817
818 sch = sc->ch[chan] = (struct schan *)malloc(sizeof *sc->ch[chan],
819 M_MN, M_WAITOK | M_ZERO);
820 sch->sc = sc;
821 sch->state = DOWN;
822 sch->chan = chan;
823 sprintf(sch->name, "%s%d", sc->name, chan);
824 return;
825 }
826
827 #ifdef notyet
828 /*
829 * Dump Munich32x state
830 */
831 static void
m32_dump(struct mn_softc * sc)832 m32_dump(struct mn_softc *sc)
833 {
834 u_int32_t *tp4;
835 int i, j;
836
837 printf("mn%d: MUNICH32X dump\n", sc->unit);
838 tp4 = (u_int32_t *)sc->m0v;
839 for(j = 0; j < 64; j += 8) {
840 printf("%02x", j * sizeof *tp4);
841 for(i = 0; i < 8; i++)
842 printf(" %08x", tp4[i+j]);
843 printf("\n");
844 }
845 for(j = 0; j < M32_CHAN; j++) {
846 if (!sc->ch[j])
847 continue;
848 printf("CH%d: state %d ts %08x",
849 j, sc->ch[j]->state, sc->ch[j]->ts);
850 printf(" %08x %08x %08x %08x %08x %08x\n",
851 sc->m32_mem.cs[j].flags,
852 sc->m32_mem.cs[j].rdesc,
853 sc->m32_mem.cs[j].tdesc,
854 sc->m32_mem.cs[j].itbs,
855 sc->m32_mem.crxd[j],
856 sc->m32_mem.ctxd[j] );
857 }
858 }
859
860 /*
861 * Dump Falch54 state
862 */
863 static void
f54_dump(struct mn_softc * sc)864 f54_dump(struct mn_softc *sc)
865 {
866 u_int8_t *tp1;
867 int i, j;
868
869 printf("%s: FALC54 dump\n", sc->name);
870 tp1 = (u_int8_t *)sc->m1v;
871 for(j = 0; j < 128; j += 16) {
872 printf("%s: %02x |", sc->name, j * sizeof *tp1);
873 for(i = 0; i < 16; i++)
874 printf(" %02x", tp1[i+j]);
875 printf("\n");
876 }
877 }
878 #endif /* notyet */
879
880 /*
881 * Init Munich32x
882 */
883 static void
m32_init(struct mn_softc * sc)884 m32_init(struct mn_softc *sc)
885 {
886
887 sc->m32x->conf = 0x00000000;
888 sc->m32x->mode1 = 0x81048000 + 1600; /* XXX: temp */
889 #if 1
890 sc->m32x->mode2 = 0x00000081;
891 sc->m32x->txpoll = 0xffffffff;
892 #elif 1
893 sc->m32x->mode2 = 0x00000081;
894 sc->m32x->txpoll = 0xffffffff;
895 #else
896 sc->m32x->mode2 = 0x00000101;
897 #endif
898 sc->m32x->lconf = 0x6060009B;
899 sc->m32x->imask = 0x00000000;
900 }
901
902 /*
903 * Init the Falc54
904 */
905 static void
f54_init(struct mn_softc * sc)906 f54_init(struct mn_softc *sc)
907 {
908 sc->f54w->ipc = 0x07;
909
910 sc->f54w->xpm0 = 0xbd;
911 sc->f54w->xpm1 = 0x03;
912 sc->f54w->xpm2 = 0x00;
913
914 sc->f54w->imr0 = 0x18; /* RMB, CASC */
915 sc->f54w->imr1 = 0x08; /* XMB */
916 sc->f54w->imr2 = 0x00;
917 sc->f54w->imr3 = 0x38; /* LMFA16, AIS16, RA16 */
918 sc->f54w->imr4 = 0x00;
919
920 sc->f54w->fmr0 = 0xf0; /* X: HDB3, R: HDB3 */
921 sc->f54w->fmr1 = 0x0e; /* Send CRC4, 2Mbit, ECM */
922 if (sc->framing == E1)
923 sc->f54w->fmr2 = 0x03; /* Auto Rem-Alarm, Auto resync */
924 else if (sc->framing == E1U)
925 sc->f54w->fmr2 = 0x33; /* dais, rtm, Auto Rem-Alarm, Auto resync */
926
927 sc->f54w->lim1 = 0xb0; /* XCLK=8kHz, .62V threshold */
928 sc->f54w->pcd = 0x0a;
929 sc->f54w->pcr = 0x15;
930 sc->f54w->xsw = 0x9f; /* fmr4 */
931 if (sc->framing == E1)
932 sc->f54w->xsp = 0x1c; /* fmr5 */
933 else if (sc->framing == E1U)
934 sc->f54w->xsp = 0x3c; /* tt0, fmr5 */
935 sc->f54w->xc0 = 0x07;
936 sc->f54w->xc1 = 0x3d;
937 sc->f54w->rc0 = 0x05;
938 sc->f54w->rc1 = 0x00;
939 sc->f54w->cmdr = 0x51;
940 }
941
942 static int
mn_reset(struct mn_softc * sc)943 mn_reset(struct mn_softc *sc)
944 {
945 u_int32_t u;
946 int i;
947
948 sc->m32x->ccba = vtophys(&sc->m32_mem.csa);
949 sc->m32_mem.csa = vtophys(&sc->m32_mem.ccb);
950
951 bzero(sc->tiqb, sizeof sc->tiqb);
952 sc->m32x->tiqba = vtophys(&sc->tiqb);
953 sc->m32x->tiql = NIQB / 16 - 1;
954
955 bzero(sc->riqb, sizeof sc->riqb);
956 sc->m32x->riqba = vtophys(&sc->riqb);
957 sc->m32x->riql = NIQB / 16 - 1;
958
959 bzero(sc->ltiqb, sizeof sc->ltiqb);
960 sc->m32x->ltiqba = vtophys(&sc->ltiqb);
961 sc->m32x->ltiql = NIQB / 16 - 1;
962
963 bzero(sc->lriqb, sizeof sc->lriqb);
964 sc->m32x->lriqba = vtophys(&sc->lriqb);
965 sc->m32x->lriql = NIQB / 16 - 1;
966
967 bzero(sc->piqb, sizeof sc->piqb);
968 sc->m32x->piqba = vtophys(&sc->piqb);
969 sc->m32x->piql = NIQB / 16 - 1;
970
971 m32_init(sc);
972 f54_init(sc);
973
974 u = sc->m32x->stat;
975 sc->m32x->stat = u;
976 sc->m32_mem.ccb = 0x4;
977 sc->m32x->cmd = 0x1;
978 DELAY(1000);
979 u = sc->m32x->stat;
980 sc->m32x->stat = u;
981
982 /* set all timeslots to known state */
983 for (i = 0; i < 32; i++)
984 sc->m32_mem.ts[i] = 0x20002000;
985
986 if (!(u & 1)) {
987 printf(
988 "mn%d: WARNING: Controller failed the PCI bus-master test.\n"
989 "mn%d: WARNING: Use a PCI slot which can support bus-master cards.\n",
990 sc->unit, sc->unit);
991 return (0);
992 }
993 return (1);
994 }
995
996 /*
997 * FALC54 interrupt handling
998 */
999 static void
f54_intr(struct mn_softc * sc)1000 f54_intr(struct mn_softc *sc)
1001 {
1002 unsigned g, u, s;
1003
1004 g = sc->f54r->gis;
1005 u = sc->f54r->isr0 << 24;
1006 u |= sc->f54r->isr1 << 16;
1007 u |= sc->f54r->isr2 << 8;
1008 u |= sc->f54r->isr3;
1009 sc->falc_irq = u;
1010 /* don't chat about the 1 sec heart beat */
1011 if (u & ~0x40) {
1012 #if 0
1013 printf("%s*: FALC54 IRQ GIS:%02x %b\n", sc->name, g, u, "\20"
1014 "\40RME\37RFS\36T8MS\35RMB\34CASC\33CRC4\32SA6SC\31RPF"
1015 "\30b27\27RDO\26ALLS\25XDU\24XMB\23b22\22XLSC\21XPR"
1016 "\20FAR\17LFA\16MFAR\15T400MS\14AIS\13LOS\12RAR\11RA"
1017 "\10ES\7SEC\6LMFA16\5AIS16\4RA16\3API\2SLN\1SLP");
1018 #endif
1019 s = sc->f54r->frs0 << 24;
1020 s |= sc->f54r->frs1 << 16;
1021 s |= sc->f54r->rsw << 8;
1022 s |= sc->f54r->rsp;
1023 sc->falc_state = s;
1024
1025 s &= ~0x01844038; /* undefined or static bits */
1026 s &= ~0x00009fc7; /* bits we don't care about */
1027 s &= ~0x00780000; /* XXX: TS16 related */
1028 s &= ~0x06000000; /* XXX: Multiframe related */
1029 #if 0
1030 printf("%s*: FALC54 Status %b\n", sc->name, s, "\20"
1031 "\40LOS\37AIS\36LFA\35RRA\34AUXP\33NMF\32LMFA\31frs0.0"
1032 "\30frs1.7\27TS16RA\26TS16LOS\25TS16AIS\24TS16LFA\23frs1.2\22XLS\21XLO"
1033 "\20RS1\17rsw.6\16RRA\15RY0\14RY1\13RY2\12RY3\11RY4"
1034 "\10SI1\7SI2\6rsp.5\5rsp.4\4rsp.3\3RSIF\2RS13\1RS15");
1035 #endif
1036 if (s != sc->framer_state) {
1037 #if 0
1038 for (i = 0; i < M32_CHAN; i++) {
1039 if (!sc->ch[i])
1040 continue;
1041 sp = &sc->ch[i]->ifsppp;
1042 if (!(SP2IFP(sp)->if_flags & IFF_UP))
1043 continue;
1044 if (s)
1045 timeout((timeout_t *)sp->pp_down, sp, 1 * hz);
1046 else
1047 timeout((timeout_t *)sp->pp_up, sp, 1 * hz);
1048 }
1049 #endif
1050 sc->framer_state = s;
1051 }
1052 }
1053 /* Once per second check error counters */
1054 /* XXX: not clear if this is actually ok */
1055 if (!(u & 0x40))
1056 return;
1057 sc->cnt_fec += sc->f54r->fec;
1058 sc->cnt_cvc += sc->f54r->cvc;
1059 sc->cnt_cec1 += sc->f54r->cec1;
1060 sc->cnt_ebc += sc->f54r->ebc;
1061 sc->cnt_cec2 += sc->f54r->cec2;
1062 sc->cnt_cec3 += sc->f54r->cec3;
1063 sc->cnt_rbc += sc->f54r->rbc;
1064 }
1065
1066 /*
1067 * Transmit interrupt for one channel
1068 */
1069 static void
mn_tx_intr(struct mn_softc * sc,u_int32_t vector)1070 mn_tx_intr(struct mn_softc *sc, u_int32_t vector)
1071 {
1072 u_int32_t chan;
1073 struct trxd *dp;
1074 struct mbuf *m;
1075
1076 chan = vector & 0x1f;
1077 if (!sc->ch[chan])
1078 return;
1079 if (sc->ch[chan]->state != UP) {
1080 printf("%s: tx_intr when not UP\n", sc->name);
1081 return;
1082 }
1083 for (;;) {
1084 dp = sc->ch[chan]->x1;
1085 if (vtophys(dp) == sc->m32_mem.ctxd[chan])
1086 return;
1087 m = dp->m;
1088 if (m) {
1089 #if 0
1090 printf("%d = %d - %d (%p)\n",
1091 sc->ch[chan]->tx_pending - m->m_pkthdr.len,
1092 sc->ch[chan]->tx_pending , m->m_pkthdr.len, m);
1093 #endif
1094 sc->ch[chan]->tx_pending -= m->m_pkthdr.len;
1095 m_freem(m);
1096 }
1097 sc->ch[chan]->last_xmit = time_second;
1098 sc->ch[chan]->x1 = dp->vnext;
1099 mn_free_desc(dp);
1100 }
1101 }
1102
1103 /*
1104 * Receive interrupt for one channel
1105 */
1106 static void
mn_rx_intr(struct mn_softc * sc,u_int32_t vector)1107 mn_rx_intr(struct mn_softc *sc, u_int32_t vector)
1108 {
1109 u_int32_t chan, err;
1110 struct trxd *dp;
1111 struct mbuf *m;
1112 struct schan *sch;
1113
1114 chan = vector & 0x1f;
1115 if (!sc->ch[chan])
1116 return;
1117 sch = sc->ch[chan];
1118 if (sch->state != UP) {
1119 printf("%s: rx_intr when not UP\n", sc->name);
1120 return;
1121 }
1122 vector &= ~0x1f;
1123 if (vector == 0x30000b00)
1124 sch->rx_error++;
1125 for (;;) {
1126 dp = sch->r1;
1127 if (vtophys(dp) == sc->m32_mem.crxd[chan])
1128 return;
1129 m = dp->m;
1130 dp->m = 0;
1131 m->m_pkthdr.len = m->m_len = (dp->status >> 16) & 0x1fff;
1132 err = (dp->status >> 8) & 0xff;
1133 if (!err) {
1134 int error;
1135 NG_SEND_DATA_ONLY(error, sch->hook, m);
1136 sch->last_recv = time_second;
1137 /* we could be down by now... */
1138 if (sch->state != UP)
1139 return;
1140 } else if (err & 0x40) {
1141 sch->short_error++;
1142 } else if (err & 0x10) {
1143 sch->crc_error++;
1144 } else if (err & 0x08) {
1145 sch->dribble_error++;
1146 } else if (err & 0x04) {
1147 sch->long_error++;
1148 } else if (err & 0x02) {
1149 sch->abort_error++;
1150 } else if (err & 0x01) {
1151 sch->overflow_error++;
1152 }
1153 if (err) {
1154 sch->last_rxerr = time_second;
1155 sch->prev_error = sch->last_error;
1156 sch->last_error = err;
1157 }
1158
1159 sc->ch[chan]->r1 = dp->vnext;
1160
1161 /* Replenish desc + mbuf supplies */
1162 if (!m) {
1163 MGETHDR(m, M_NOWAIT, MT_DATA);
1164 if (m == NULL) {
1165 mn_free_desc(dp);
1166 return; /* ENOBUFS */
1167 }
1168 if (!(MCLGET(m, M_NOWAIT))) {
1169 mn_free_desc(dp);
1170 m_freem(m);
1171 return; /* ENOBUFS */
1172 }
1173 }
1174 dp->m = m;
1175 dp->data = vtophys(m->m_data);
1176 dp->flags = 0x40000000;
1177 dp->flags += 1600 << 16;
1178 dp->next = vtophys(dp);
1179 dp->vnext = 0;
1180 sc->ch[chan]->rl->next = vtophys(dp);
1181 sc->ch[chan]->rl->vnext = dp;
1182 sc->ch[chan]->rl->flags &= ~0x40000000;
1183 sc->ch[chan]->rl = dp;
1184 }
1185 }
1186
1187
1188 /*
1189 * Interupt handler
1190 */
1191
1192 static void
mn_intr(void * xsc)1193 mn_intr(void *xsc)
1194 {
1195 struct mn_softc *sc;
1196 u_int32_t stat, lstat, u;
1197 int i, j;
1198
1199 sc = xsc;
1200 stat = sc->m32x->stat;
1201 lstat = sc->m32x->lstat;
1202 #if 0
1203 if (!stat && !(lstat & 2))
1204 return;
1205 #endif
1206
1207 if (stat & ~0xc200) {
1208 printf("%s: I stat=%08x lstat=%08x\n", sc->name, stat, lstat);
1209 }
1210
1211 if ((stat & 0x200) || (lstat & 2))
1212 f54_intr(sc);
1213
1214 for (j = i = 0; i < 64; i ++) {
1215 u = sc->riqb[i];
1216 if (u) {
1217 sc->riqb[i] = 0;
1218 mn_rx_intr(sc, u);
1219 if ((u & ~0x1f) == 0x30000800 || (u & ~0x1f) == 0x30000b00)
1220 continue;
1221 u &= ~0x30000400; /* bits we don't care about */
1222 if ((u & ~0x1f) == 0x00000900)
1223 continue;
1224 if (!(u & ~0x1f))
1225 continue;
1226 if (!j)
1227 printf("%s*: RIQB:", sc->name);
1228 printf(" [%d]=%08x", i, u);
1229 j++;
1230 }
1231 }
1232 if (j)
1233 printf("\n");
1234
1235 for (j = i = 0; i < 64; i ++) {
1236 u = sc->tiqb[i];
1237 if (u) {
1238 sc->tiqb[i] = 0;
1239 mn_tx_intr(sc, u);
1240 if ((u & ~0x1f) == 0x20000800)
1241 continue;
1242 u &= ~0x20000000; /* bits we don't care about */
1243 if (!u)
1244 continue;
1245 if (!j)
1246 printf("%s*: TIQB:", sc->name);
1247 printf(" [%d]=%08x", i, u);
1248 j++;
1249 }
1250 }
1251 if (j)
1252 printf("\n");
1253 sc->m32x->stat = stat;
1254 }
1255
1256 /*
1257 * PCI initialization stuff
1258 */
1259
1260 static int
mn_probe(device_t self)1261 mn_probe (device_t self)
1262 {
1263 u_int id = pci_get_devid(self);
1264
1265 if (sizeof (struct m32xreg) != 256) {
1266 printf("MN: sizeof(struct m32xreg) = %zd, should have been 256\n", sizeof (struct m32xreg));
1267 return (ENXIO);
1268 }
1269 if (sizeof (struct f54rreg) != 128) {
1270 printf("MN: sizeof(struct f54rreg) = %zd, should have been 128\n", sizeof (struct f54rreg));
1271 return (ENXIO);
1272 }
1273 if (sizeof (struct f54wreg) != 128) {
1274 printf("MN: sizeof(struct f54wreg) = %zd, should have been 128\n", sizeof (struct f54wreg));
1275 return (ENXIO);
1276 }
1277
1278 if (id != 0x2101110a)
1279 return (ENXIO);
1280
1281 device_set_desc_copy(self, "Munich32X E1/T1 HDLC Controller");
1282 return (BUS_PROBE_DEFAULT);
1283 }
1284
1285 static int
mn_attach(device_t self)1286 mn_attach (device_t self)
1287 {
1288 struct mn_softc *sc;
1289 u_int32_t u;
1290 u_int32_t ver;
1291 static int once;
1292 int rid, error;
1293 struct resource *res;
1294
1295 if (!once) {
1296 if (ng_newtype(&mntypestruct))
1297 printf("ng_newtype failed\n");
1298 once++;
1299 }
1300
1301 sc = (struct mn_softc *)malloc(sizeof *sc, M_MN, M_WAITOK | M_ZERO);
1302 device_set_softc(self, sc);
1303
1304 sc->dev = self;
1305 sc->unit = device_get_unit(self);
1306 sc->framing = E1;
1307 sprintf(sc->name, "mn%d", sc->unit);
1308
1309 rid = PCIR_BAR(0);
1310 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1311 if (res == NULL) {
1312 device_printf(self, "Could not map memory\n");
1313 free(sc, M_MN);
1314 return ENXIO;
1315 }
1316 sc->m0v = rman_get_virtual(res);
1317 sc->m0p = rman_get_start(res);
1318
1319 rid = PCIR_BAR(1);
1320 res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid, RF_ACTIVE);
1321 if (res == NULL) {
1322 device_printf(self, "Could not map memory\n");
1323 free(sc, M_MN);
1324 return ENXIO;
1325 }
1326 sc->m1v = rman_get_virtual(res);
1327 sc->m1p = rman_get_start(res);
1328
1329 /* Allocate interrupt */
1330 rid = 0;
1331 sc->irq = bus_alloc_resource_any(self, SYS_RES_IRQ, &rid,
1332 RF_SHAREABLE | RF_ACTIVE);
1333
1334 if (sc->irq == NULL) {
1335 printf("couldn't map interrupt\n");
1336 free(sc, M_MN);
1337 return(ENXIO);
1338 }
1339
1340 error = bus_setup_intr(self, sc->irq, INTR_TYPE_NET, NULL, mn_intr, sc, &sc->intrhand);
1341
1342 if (error) {
1343 printf("couldn't set up irq\n");
1344 free(sc, M_MN);
1345 return(ENXIO);
1346 }
1347
1348 u = pci_read_config(self, PCIR_COMMAND, 2);
1349 printf("%x\n", u);
1350 pci_write_config(self, PCIR_COMMAND, u | PCIM_CMD_PERRESPEN | PCIM_CMD_BUSMASTEREN, 2);
1351 #if 0
1352 pci_write_config(self, PCIR_COMMAND, 0x02800046, 4);
1353 #endif
1354 u = pci_read_config(self, PCIR_COMMAND, 1);
1355 printf("%x\n", u);
1356
1357 ver = pci_get_revid(self);
1358
1359 sc->m32x = (struct m32xreg *) sc->m0v;
1360 sc->f54w = (struct f54wreg *) sc->m1v;
1361 sc->f54r = (struct f54rreg *) sc->m1v;
1362
1363 /* We must reset before poking at FALC54 registers */
1364 u = mn_reset(sc);
1365 if (!u)
1366 return (0);
1367
1368 printf("mn%d: Munich32X", sc->unit);
1369 switch (ver) {
1370 case 0x13:
1371 printf(" Rev 2.2");
1372 break;
1373 default:
1374 printf(" Rev 0x%x\n", ver);
1375 }
1376 printf(", Falc54");
1377 switch (sc->f54r->vstr) {
1378 case 0:
1379 printf(" Rev < 1.3\n");
1380 break;
1381 case 1:
1382 printf(" Rev 1.3\n");
1383 break;
1384 case 2:
1385 printf(" Rev 1.4\n");
1386 break;
1387 case 0x10:
1388 printf("-LH Rev 1.1\n");
1389 break;
1390 case 0x13:
1391 printf("-LH Rev 1.3\n");
1392 break;
1393 default:
1394 printf(" Rev 0x%x\n", sc->f54r->vstr);
1395 }
1396
1397 if (ng_make_node_common(&mntypestruct, &sc->node) != 0) {
1398 printf("ng_make_node_common failed\n");
1399 return (0);
1400 }
1401 NG_NODE_SET_PRIVATE(sc->node, sc);
1402 sprintf(sc->nodename, "%s%d", NG_MN_NODE_TYPE, sc->unit);
1403 if (ng_name_node(sc->node, sc->nodename)) {
1404 NG_NODE_UNREF(sc->node);
1405 return (0);
1406 }
1407
1408 return (0);
1409 }
1410
1411
1412 static device_method_t mn_methods[] = {
1413 /* Device interface */
1414 DEVMETHOD(device_probe, mn_probe),
1415 DEVMETHOD(device_attach, mn_attach),
1416 DEVMETHOD(device_suspend, bus_generic_suspend),
1417 DEVMETHOD(device_resume, bus_generic_resume),
1418 DEVMETHOD(device_shutdown, bus_generic_shutdown),
1419
1420 DEVMETHOD_END
1421 };
1422
1423 static driver_t mn_driver = {
1424 "mn",
1425 mn_methods,
1426 0
1427 };
1428
1429 static devclass_t mn_devclass;
1430
1431 DRIVER_MODULE(mn, pci, mn_driver, mn_devclass, 0, 0);
1432