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Searched refs:mayLoad (Results 1 – 25 of 95) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonIsetDx.td42 let Defs = [R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAc…
53 …= [R30, P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedFalse = 1, mayLoad = 1, accessSize =…
106 let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
148 let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
164 let isCodeGenOnly = 1, mayLoad = 1, accessSize = WordAccess, hasNewValue = 1, opNewValue = 0 in
211 let Defs = [PC, R31, R29, R30], Uses = [R30, P0], isCodeGenOnly = 1, isPredicated = 1, mayLoad = 1,…
303 let isCodeGenOnly = 1, mayLoad = 1, accessSize = HalfWordAccess, hasNewValue = 1, opNewValue = 0 in
422 let isCodeGenOnly = 1, mayLoad = 1, accessSize = ByteAccess, hasNewValue = 1, opNewValue = 0 in
452 let Uses = [R29], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWordAccess in
560 let Defs = [PC, R31, R29, R30], Uses = [R30], isCodeGenOnly = 1, mayLoad = 1, accessSize = DoubleWo…
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HDHexagonInstrFormats.td195 let mayLoad = 1 in
200 let mayLoad = 1 in
215 let mayLoad = 1 in
391 let mayLoad = 1 in
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIInstrFormats.td96 let mayLoad = 0;
228 let mayLoad = 0;
239 let mayLoad = 0;
253 let mayLoad = 0;
266 let mayLoad = 0;
278 let mayLoad = 0;
295 let mayLoad = 1;
590 let mayLoad = 1;
612 let mayLoad = 1;
HDSIInstrInfo.td1977 let mayLoad = 1, mayStore = 1 in {
1984 } // end mayLoad = 1, mayStore = 1
2018 let mayLoad = 1, mayStore = 1 in {
2025 } // end mayLoad = 1, mayStore = 1
2061 let mayStore = 1, mayLoad = 0 in {
2073 } // mayStore = 1, mayLoad = 0
2075 let mayLoad = 1, mayStore = 0 in {
2087 } // mayLoad = 1, mayStore = 0
2210 let mayStore = 1, mayLoad = 1, hasPostISelHook = 1 in {
2256 } // mayStore = 1, mayLoad = 1, hasPostISelHook = 1
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HDR600Instructions.td85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
214 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
843 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
878 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1002 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1018 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1319 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1328 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
1497 let mayLoad = 0;
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrFormats.td980 let mayLoad = 1;
987 let mayLoad = 1;
1230 let mayLoad = 1;
1249 let mayLoad = 1;
1262 let mayLoad = 1;
1278 let mayLoad = 1;
1290 let mayLoad = 1;
1301 let mayLoad = 1;
1314 let mayLoad = 1;
1366 let mayLoad = 1;
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HDSystemZInstrBuilder.h33 if (MCID.mayLoad()) in addFrameReference()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrFormats.td797 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
821 // NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
823 let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
985 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
1186 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1201 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1477 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1505 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1617 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1880 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
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HDAArch64LoadStoreOptimizer.cpp522 bool MayLoad = FirstMI->mayLoad(); in findMatchingInsn()
626 !(MI->mayLoad() && UsedRegs[MI->getOperand(0).getReg()]) && in findMatchingInsn()
637 !(FirstMI->mayLoad() && in findMatchingInsn()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrExtension.td46 let mayLoad = 1 in
72 let mayLoad = 1 in
102 let mayLoad = 1 in
112 let mayLoad = 1 in
HDX86InstrControl.td237 let mayLoad = 1 in
249 let mayLoad = 1 in
291 let mayLoad = 1 in
300 let mayLoad = 1 in
312 let mayLoad = 1 in
HDX86InstrAVX512.td490 let mayLoad = 1 in
704 let mayLoad = 1 in {
855 let mayLoad = 1 in {
884 let mayLoad = 1 in {
1080 let mayLoad = 1 in
1091 let mayLoad = 1, Constraints = "$src1 = $dst" in
1174 let mayLoad = 1 in {
1289 let mayLoad = 1 in
1312 let mayLoad = 1 in
1326 let mayLoad = 1 in
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HDX86InstrBuilder.h155 if (MCID.mayLoad())
HDX86InstrInfo.td985 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
990 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
1001 let mayLoad = 1, SchedRW = [WriteLoad] in {
1014 } // mayLoad, SchedRW
1044 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1061 let mayLoad = 1, SchedRW = [WriteLoad] in {
1068 } // mayLoad, SchedRW
1088 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1096 mayLoad = 1, hasSideEffects = 0, SchedRW = [WriteLoad] in {
1295 let mayLoad = 1 in {
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HDX86InstrFMA.td32 let mayLoad = 1, isCommutable = IsMVariantCommutable in
48 let mayLoad = 1, isCommutable = IsMVariantCommutable in
142 let mayLoad = 1, isCommutable = IsMVariantCommutable in
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMOptimizeBarriersPass.cpp41 return !(MI->mayLoad() || in CanMovePastDMB()
/NextBSD/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonShuffler.cpp199 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) in check()
258 if (HexagonMCInstrInfo::getDesc(MCII, *ID).mayLoad()) { in check()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCHazardRecognizers.cpp35 if (!MCID->mayLoad()) in isLoadAfterStore()
284 isLoad = MCID.mayLoad(); in GetInstrType()
/NextBSD/contrib/llvm/lib/CodeGen/
HDScheduleDAGInstrs.cpp469 (!MI->mayLoad() || !MI->isInvariantLoad(AA)))) in isGlobalMemoryObject()
527 if ((MIa->mayLoad() || MIa->mayStore()) && in MIsNeedChainEdge()
528 (MIb->mayLoad() || MIb->mayStore())) in MIsNeedChainEdge()
650 Dep.setLatency(((*I)->getInstr()->mayLoad()) ? LatencyToLoad : 0); in adjustChainDeps()
854 && (HasVRegDef || MI->mayLoad())) { in buildSchedGraph()
904 if (AliasChain->getInstr()->mayLoad()) in buildSchedGraph()
1009 } else if (MI->mayLoad()) { in buildSchedGraph()
HDTargetInstrInfo.cpp488 NewMI->mayLoad()) && in foldMemoryOperand()
607 if (MI->mayLoad() && !MI->isInvariantLoad(AA)) in isReallyTriviallyReMaterializableGeneric()
782 if (DefMI->mayLoad()) in defaultDefLatency()
800 return MI->mayLoad() ? 2 : 1; in getInstrLatency()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMicroMipsInstrInfo.td244 let mayLoad = 1;
251 let mayLoad = 1;
269 let mayLoad = 1;
312 let mayLoad = 1;
330 let mayLoad = 1;
347 let mayLoad = 1;
522 let mayLoad = 1;
540 let mayLoad = 1;
HDMipsDelaySlotFiller.cpp402 if (!MI.mayStore() && !MI.mayLoad()) in hasHazard()
410 SeenLoad |= MI.mayLoad(); in hasHazard()
459 HasHazard |= MI.mayLoad() || OrigSeenStore; in hasHazard_()
461 SeenNoObjLoad |= MI.mayLoad(); in hasHazard_()
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenDAGPatterns.cpp2699 bool mayLoad; member in InstAnalyzer
2704 : CDP(cdp), hasSideEffects(false), mayStore(false), mayLoad(false), in InstAnalyzer()
2718 if (hasSideEffects || mayLoad || mayStore || isVariadic) in IsNodeBitcast()
2749 if (CP.hasProperty(SDNPMayLoad)) mayLoad = true; in AnalyzeNode()
2768 if (N->NodeHasProperty(SDNPMayLoad, CDP)) mayLoad = true; in AnalyzeNode()
2775 mayLoad = true;// These may load memory. in AnalyzeNode()
2816 if (InstInfo.mayLoad != PatInfo.mayLoad && !InstInfo.mayLoad_Unset) { in InferFromPattern()
2819 if (!InstInfo.mayLoad) { in InferFromPattern()
2822 Twine(InstInfo.mayLoad)); in InferFromPattern()
2829 InstInfo.mayLoad |= PatInfo.mayLoad; in InferFromPattern()
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/NextBSD/contrib/llvm/include/llvm/MC/
HDMCInstrDesc.h350 bool mayLoad() const { return Flags & (1 << MCID::MayLoad); } in mayLoad() function
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetInstrInfo.h1254 assert(MIa && (MIa->mayLoad() || MIa->mayStore()) &&
1256 assert(MIb && (MIb->mayLoad() || MIb->mayStore()) &&

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