| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | ShrinkWrap.cpp | 206 if (UseCSR || MO.isFI() || MO.isRegMask()) { in INITIALIZE_PASS_DEPENDENCY() 207 DEBUG(dbgs() << "Use or define CSR(" << UseCSR << ") or FI(" << MO.isFI() in INITIALIZE_PASS_DEPENDENCY()
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| HD | LocalStackSlotAllocation.cpp | 309 if (MI->getOperand(i).isFI()) { in insertFrameReferenceRegisters() 347 if (!MI->getOperand(idx).isFI()) in insertFrameReferenceRegisters()
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| HD | StackSlotColoring.cpp | 151 if (!MO.isFI()) in ScanForSpillSlotRefs() 355 if (!MO.isFI()) in RewriteInstruction()
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| HD | StackColoring.cpp | 535 if (!MO.isFI()) in remapInstructions() 596 if (!MO.isFI()) in removeInvalidSlotRanges()
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| HD | RegisterScavenging.cpp | 356 while (!MI->getOperand(i).isFI()) { in getFrameIndexOperandNum()
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| HD | PrologEpilogInserter.cpp | 889 if (!MI->getOperand(i).isFI()) in replaceFrameIndices()
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | MachineOperand.h | 240 bool isFI() const { return OpKind == MO_FrameIndex; } in isFI() function 431 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && in getIndex() 527 assert((isFI() || isCPI() || isTargetIndex() || isJTI()) && in setIndex()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64DeadRegisterDefinitionsPass.cpp | 63 if (Op.isFI()) in usesFrameIndex()
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| HD | AArch64RegisterInfo.cpp | 258 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) in needsFrameBaseReg() 354 while (!MI.getOperand(i).isFI()) { in resolveFrameIndex()
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| HD | AArch64InstrInfo.cpp | 713 if (MO.isFI()) in UpdateOperandRegClass() 1184 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() && in isLoadFromStackSlot() 1207 if (MI->getOperand(0).getSubReg() == 0 && MI->getOperand(1).isFI() && in isStoreToStackSlot()
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| /NextBSD/contrib/llvm/lib/Target/BPF/ |
| HD | BPFRegisterInfo.cpp | 54 while (!MI.getOperand(i).isFI()) { in eliminateFrameIndex()
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsSEFrameLowering.cpp | 153 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandLoadCCond() 168 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandStoreCCond() 186 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandLoadACC() 211 assert(I->getOperand(0).isReg() && I->getOperand(1).isFI()); in expandStoreACC()
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| HD | MipsSEInstrInfo.cpp | 47 if ((MI->getOperand(1).isFI()) && // is a stack slot in isLoadFromStackSlot() 69 if ((MI->getOperand(1).isFI()) && // is a stack slot in isStoreToStackSlot()
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| /NextBSD/contrib/llvm/lib/Target/XCore/ |
| HD | XCoreInstrInfo.cpp | 68 if ((MI->getOperand(1).isFI()) && // is a stack slot in isLoadFromStackSlot() 90 if ((MI->getOperand(1).isFI()) && // is a stack slot in isStoreToStackSlot()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86InstrInfo.h | 136 if (MI->getOperand(Op).isFI()) return true; in isLeaMem() 148 if (MI->getOperand(Op).isFI()) return true; in isMem()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMBaseRegisterInfo.cpp | 488 for (unsigned i = 0; !MI->getOperand(i).isFI(); ++i) { in needsFrameBaseReg() 606 while (!MI.getOperand(i).isFI()) { in resolveFrameIndex() 627 while (!MI->getOperand(i).isFI()) { in isFrameOffsetLegal()
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| HD | ARMBaseInstrInfo.cpp | 988 if (MI->getOperand(1).isFI() && in isStoreToStackSlot() 1002 if (MI->getOperand(1).isFI() && in isStoreToStackSlot() 1012 if (MI->getOperand(0).isFI() && in isStoreToStackSlot() 1019 if (MI->getOperand(1).isFI() && in isStoreToStackSlot() 1179 if (MI->getOperand(1).isFI() && in isLoadFromStackSlot() 1193 if (MI->getOperand(1).isFI() && in isLoadFromStackSlot() 1203 if (MI->getOperand(1).isFI() && in isLoadFromStackSlot() 1210 if (MI->getOperand(1).isFI() && in isLoadFromStackSlot() 1791 if (MO.isFI() || MO.isCPI() || MO.isJTI()) in canFoldIntoMOVCC()
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| HD | Thumb1FrameLowering.cpp | 308 MI->getOperand(1).isFI() && in isCSRestore()
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| HD | ThumbRegisterInfo.cpp | 434 while (!MI.getOperand(i).isFI()) { in resolveFrameIndex()
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| /NextBSD/contrib/llvm/lib/Target/NVPTX/ |
| HD | NVPTXPrologEpilogPass.cpp | 62 if (!MI->getOperand(i).isFI()) in runOnMachineFunction()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcInstrInfo.cpp | 51 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() && in isLoadFromStackSlot() 72 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() && in isStoreToStackSlot()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonFrameLowering.cpp | 210 if (MO.isFI()) in needsStackFrame() 914 assert(MI->getOperand(0).isFI() && "Expect a frame index"); in replacePredRegPseudoSpillCode() 940 assert(MI->getOperand(1).isFI() && "Expect a frame index"); in replacePredRegPseudoSpillCode()
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| HD | HexagonInstrInfo.cpp | 84 if (MI->getOperand(2).isFI() && in isLoadFromStackSlot() 108 if (MI->getOperand(2).isFI() && in isStoreToStackSlot()
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| /NextBSD/contrib/llvm/lib/Target/SystemZ/ |
| HD | SystemZInstrInfo.cpp | 197 MI->getOperand(1).isFI() && in isSimpleMove() 222 !MI->getOperand(0).isFI() || in isStackSlotCopy() 224 !MI->getOperand(3).isFI() || in isStackSlotCopy()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCRegisterInfo.cpp | 993 while (!MI.getOperand(FIOperandNum).isFI()) { in resolveFrameIndex() 1018 while (!MI->getOperand(FIOperandNum).isFI()) { in isFrameOffsetLegal()
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