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/NextBSD/contrib/llvm/lib/Target/ARM/
HDARM.td34 "Enable VFP2 instructions">;
36 "Enable VFP3 instructions",
39 "Enable NEON instructions",
42 "Enable Thumb2 instructions">;
49 "Enable VFP4 instructions",
57 "Enable divide instructions">;
60 "Enable divide instructions in ARM mode">;
62 "Enable Thumb2 extract and pack instructions">;
64 "Has data barrier (dmb / dsb) instructions">;
77 "Enable support for CRC instructions">;
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/NextBSD/contrib/subversion/subversion/libsvn_fs_x/
HDreps.c175 apr_array_header_t *instructions; member
207 const instruction_t *instructions; member
400 result->instructions = apr_array_make(result_pool, 0, in svn_fs_x__reps_builder_create()
453 APR_ARRAY_PUSH(builder->instructions, instruction_t) = instruction; in add_new_text()
498 if ( builder->instructions->nelts + 2 * contents->len / MATCH_BLOCKSIZE in svn_fs_x__reps_add()
503 rep.first_instruction = (apr_uint32_t)builder->instructions->nelts; in svn_fs_x__reps_add()
555 APR_ARRAY_PUSH(builder->instructions, instruction_t) = instruction; in svn_fs_x__reps_add()
563 rep.instruction_count = (apr_uint32_t)builder->instructions->nelts in svn_fs_x__reps_add()
582 + builder->instructions->nelts * 2 in svn_fs_x__reps_estimate_size()
605 for (instruction = container->instructions + instruction_idx; in get_text()
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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagon.td41 // PredRel - Filter class used to relate non-predicated instructions with their
44 // PredNewRel - Filter class used to relate predicated instructions with their
47 // ImmRegRel - Filter class used to relate instructions having reg-reg form
50 // NewValueRel - Filter class used to relate regular store instructions with
53 // NewValueRel - Filter class used to relate load/store instructions having
58 // Generate mapping table to relate non-predicate instructions with their
68 // The key column is the unpredicated instructions.
75 // Generate mapping table to relate predicate-true instructions with their
87 // Generate mapping table to relate predicate-false instructions with their
99 // Generate mapping table to relate predicated instructions with their .new
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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86.td35 "Enable conditional move instructions">;
42 "Enable MMX instructions">;
44 "Enable SSE instructions",
49 "Enable SSE2 instructions",
52 "Enable SSE3 instructions",
55 "Enable SSSE3 instructions",
58 "Enable SSE 4.1 instructions",
61 "Enable SSE 4.2 instructions",
64 "Enable 3DNow! instructions",
67 "Enable 3DNow! Athlon instructions",
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HDX86InstrFormats.td242 // Attributes specific to X86 instructions...
407 // Templates for instructions that use a 16- or 32-bit segmented address as
427 // SI - SSE 1 & 2 scalar instructions
439 // AVX instructions have a 'v' prefix in the mnemonic
457 // AVX instructions have a 'v' prefix in the mnemonic
462 // SIi8 - SSE 1 & 2 scalar instructions - vex form available on AVX512
471 // AVX instructions have a 'v' prefix in the mnemonic
477 // PI - SSE 1 & 2 packed instructions
486 // AVX instructions have a 'v' prefix in the mnemonic
492 // MMXPI - SSE 1 & 2 packed instructions with MMX operands
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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPC.td52 "Enable 64-bit instructions">;
58 "Enable Altivec instructions">;
60 "Enable SPE instructions">;
82 "Enable the fri[mnpz] instructions">;
84 "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions">;
88 "Enable the popcnt[dw] instructions">;
92 "Enable extended divide instructions">;
100 "Enable Book E instructions",
106 "Enable E500/E500mc instructions">;
108 "Enable PPC 4xx instructions">;
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/NextBSD/contrib/gcc/config/rs6000/
HDrs6000.opt49 Use PowerPC General Purpose group optional instructions
53 Use PowerPC Graphics group optional instructions
65 Use PowerPC V2.02 floating point rounding instructions
69 Use AltiVec instructions
73 Use 4xx half-word multiply instructions
81 Generate load/store multiple instructions
85 Generate string instructions for block moves
105 Do not generate load/store with update instructions
109 Generate load/store with update instructions
113 Do not generate fused multiply/add instructions
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/NextBSD/contrib/gcc/config/mips/
HD4130.md4 ;; The processor issues each 8-byte aligned pair of instructions together,
6 ;; want two instructions to issue in parallel, we need to make sure that the
15 ;; can change the addresses of many instructions.
20 ;; through the function looking for pairs of instructions that could
32 ;; (a) dependent instructions are separated by a non-dependent
35 ;; (b) instructions that use the multiplication unit are separated
36 ;; by non-multiplication instructions; and
38 ;; (c) memory access instructions are separated by non-memory
39 ;; instructions.
41 ;; The idea is to keep conflicting instructions apart wherever possible
HDmips.opt32 Use PMC-style 'mad' instructions
40 Use Branch Likely instructions, overriding the architecture default
52 Use trap instructions to check for integer divide by zero
56 Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations
60 Use MIPS-DSP instructions
126 Generate floating-point multiply-add instructions
138 Allow the use of hardware floating-point instructions
150 Use MIPS-3D instructions
182 Do not use MIPS-3D instructions
186 Use paired-single floating-point instructions
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/NextBSD/contrib/binutils/gas/doc/
HDc-mips.texi30 * MIPS autoextend:: Directives for extending MIPS 16 bit instructions
34 generation of MIPS ASE instructions
111 set, 64-bit instructions generate a trap. Also, some 32-bit OSes only
133 provides a number of new instructions which target smartcard and
141 This tells the assembler to accept MIPS-3D instructions.
147 This tells the assembler to accept MDMX instructions.
153 This tells the assembler to accept DSP Release 1 instructions.
160 This tells the assembler to accept DSP Release 2 instructions.
166 This tells the assembler to accept MT instructions.
172 of an mfhi or mflo instruction occurs in the following two instructions.
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HDc-i386.texi67 By default, x86 GAS replaces multiple nop instructions used for
68 alignment within code sections with multi-byte nop instructions such
83 instructions. The following architectures are recognized:
109 This option only affects instructions generated by the assembler. The
116 conjunction with the @option{-march} option, only instructions
181 previous Unix assemblers. Note that instructions with more than one
201 @cindex return instructions, i386
203 @cindex return instructions, x86-64
243 Almost all instructions have the same names in AT&T and Intel format.
245 instructions need two sizes to specify them. They need a size to
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HDc-ppc.texi29 core instruction set, but including a few additional instructions at
31 instructions each variant supports, please see the chip's architecture
53 Generate code for PowerPC 440. BookE and some 405 instructions.
65 Generate code for Motorola SPE instructions.
80 Generate code for processors with AltiVec instructions.
95 Generate code Power/PowerPC common instructions.
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64.td27 "Enable Advanced SIMD instructions", [FeatureFPARMv8]>;
30 "Enable cryptographic instructions">;
33 "Enable ARMv8 CRC-32 checksum instructions">;
35 /// Cyclone has register move instructions which are "free".
39 /// Cyclone has instructions which zero registers for "free".
41 "Has zero-cycle zeroing instructions">;
48 "Support ARM v8.1a instructions", [FeatureCRC]>;
/NextBSD/usr.bin/bc/
HDbc.y100 static struct tree *instructions = NULL; variable
774 p = realloc(instructions, newsize * sizeof(*p));
776 free(instructions);
779 instructions = p;
789 instructions[current].index = CONST_STRING; in cs()
790 instructions[current].u.cstr = str; in cs()
799 instructions[current].index = ALLOC_STRING; in as()
800 instructions[current].u.astr = strdup(str); in as()
801 if (instructions[current].u.astr == NULL) in as()
816 instructions[current++].index = arg; in node()
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/NextBSD/contrib/gcc/config/arm/
HDarm1026ejs.md31 ;; instructions is "true", i.e., that all of the instructions are
60 ;; ALU instructions require three cycles to execute, and use the ALU
92 ;; Multiplication instructions loop in the execute stage until the
96 ;; The result of the "smul" and "smulw" instructions is not available
103 ;; The "smlaxy" and "smlawx" instructions require two iterations through
111 ;; The "smlalxy", "mul", and "mla" instructions require two iterations
119 ;; The "muls" and "mlas" instructions loop in the execute stage for
127 ;; Long multiply instructions that produce two registers of
130 ;; word. That fact is not modeled; instead, the instructions are
134 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
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HDarm1020e.md31 ;; instructions is "true", i.e., that all of the instructions are
60 ;; ALU instructions require three cycles to execute, and use the ALU
92 ;; Multiplication instructions loop in the execute stage until the
96 ;; The result of the "smul" and "smulw" instructions is not available
103 ;; The "smlaxy" and "smlawx" instructions require two iterations through
111 ;; The "smlalxy", "mul", and "mla" instructions require two iterations
119 ;; The "muls" and "mlas" instructions loop in the execute stage for
127 ;; Long multiply instructions that produce two registers of
130 ;; word. That fact is not modeled; instead, the instructions are
134 ;; The "umull", "umlal", "smull", and "smlal" instructions all take
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HDarm926ejs.md31 ;; instructions is "true", i.e., that all of the instructions are
52 ;; ALU instructions require three cycles to execute, and use the ALU
78 ;; Multiplication instructions loop in the execute stage until the
117 ;; The models for load/store instructions do not accurately describe
169 ;; Branch instructions are difficult to model accurately. The ARM
/NextBSD/contrib/binutils/opcodes/
HDarc-ext.c49 if (!arc_extension_map.instructions[opcode]) in arcExtMap_instName()
51 *flags = arc_extension_map.instructions[opcode]->flags; in arcExtMap_instName()
52 return arc_extension_map.instructions[opcode]->name; in arcExtMap_instName()
127 insn = arc_extension_map.instructions[i]; in cleanup_ext_map()
193 arc_extension_map.instructions[(int) opcode] = insn; in arcExtMap_add()
HDChangeLog-200697 * m68k-opc.c (m68k_opcodes): Place trap instructions before set
190 cell specific instructions. Add {st,l}x{r,l}{,l} cell specific
191 VMX instructions.
222 set, don't bother printing X. Add new iwmmxt instructions.
275 (OP_MXC): New function to handle cvt* (convert instructions) between
316 * i386-dis.c (dis386): Add support for 4 operand instructions. Add
317 support for amdfam10 SSE4a/ABM instructions. Modify all
319 prefix for non-string instructions.
369 instructions.
393 * mips-dis.c: Disassemble DSP64 instructions for MIPS64R2.
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/NextBSD/contrib/gcc/config/i386/
HDppro.md51 ;; Since the P6 CPUs execute instructions out-of-order, the most important
57 ;; - Find a less crude way to model complex instructions, in
71 ;; Simple instructions of the register-register form have only one uop.
72 ;; Load instructions are also only one uop. Store instructions decode to
73 ;; two uops, and simple read-modify instructions also take two uops.
74 ;; Simple instructions of the register-memory form have two to three uops.
75 ;; Simple read-modify-write instructions have four uops. The rules for
85 ;; in each cycle, to decode as many instructions per cycle as possible.
96 ;; Most instructions can be decoded on any of the three decoders.
122 ;; Only the irregular instructions have to be modeled here. A load
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HDpentium.md36 ;; and doesn't hurt much on MMX. (Prefixed instructions are not very
93 ;; Floating point instructions can overlap with new issue of integer
94 ;; instructions. We model only first cycle of FP pipeline, as it is
134 ;; Few common long latency instructions
147 ;; latency of these instructions and not modeling the latency
185 ;; Push and pop instructions have 1 cycle latency and special
187 ;; and call instructions.
213 ;; in FP pipeline allowing other instructions to be executed.
225 ;; Long latency FP instructions overlap with integer instructions,
239 ;; Integer instructions. Load/execute/store takes 3 cycles,
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMSA.txt7 (semantically equivalent) instructions to be used in place of the requested
14 example, two instructions might be equally valid for some given IR and one is
31 instructions will be selected instead of vshf.[bhwd]. Unlike the ilv*,
32 and pck* instructions, this is matched from MipsISD::VSHF instead of
68 In future, the compiler may choose between these three instructions
71 between the instructions and the vselect node in one place:
/NextBSD/contrib/binutils/include/opcode/
HDChangeLog-9103333 instructions.
338 (PPC_OPCODE_EFS): New opcode type for efs* instructions.
339 (PPC_OPCODE_CLASSIC): New opcode type for Classic PowerPC instructions.
400 instructions.
501 (OPCODE_IS_MEMBER): Allow instructions matching INSN_SB1
512 instructions, respectively.
644 * i386.h (i386_optab): SSE integer converison instructions have
710 * i386.h (i386_optab): Fix 64bit pushf template; Add instructions
715 * i386.h (i386_optab): Add "rex*" instructions;
716 add swapgs; disable jmp/call far direct instructions for
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/NextBSD/contrib/gcc/config/sparc/
HDsparc.opt48 Use hardware quad FP instructions
52 Do not use hardware quad fp instructions
88 Optimize tail call instructions in assembler and linker
125 ;; Generate code that uses the V8 instructions deprecated
/NextBSD/contrib/gcc/
HDparams.def89 of a function counted in internal gcc instructions (not in
90 real machine instructions) that is eligible for inlining
96 call other functions, the already inlined instructions are
102 "The maximum number of instructions in a single function eligible for inlining",
114 "The maximum number of instructions when automatically inlining",
119 "The maximum number of instructions inline function can grow to via recursive inlining",
124 "The maximum number of instructions non-inline function can grow to via recursive inlining",
149 /* The maximum number of instructions to consider when looking for an
151 number of instructions is searched, the time savings from filling
157 "The maximum number of instructions to consider to fill a delay slot",
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