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Searched refs:hasSideEffects (Results 1 – 25 of 74) sorted by relevance

123

/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonIsetDx.td15 let isCodeGenOnly = 1, hasSideEffects = 0 in
32 … isPredicated = 1, isPredicatedFalse = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
63 let isCodeGenOnly = 1, hasSideEffects = 0 in
93 let Uses = [P0], isCodeGenOnly = 1, isPredicated = 1, isPredicatedNew = 1, hasSideEffects = 0, hasN…
122 …1, isPredicated = 1, isPredicatedNew = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
132 let isCodeGenOnly = 1, hasSideEffects = 0, hasNewValue = 1, opNewValue = 0, isExtendable = 1, isExt…
180 let Defs = [P0], isCodeGenOnly = 1, hasSideEffects = 0 in
194 let isCodeGenOnly = 1, hasSideEffects = 0 in
277 … = [PC], Uses = [R31], isCodeGenOnly = 1, isBranch = 1, isIndirectBranch = 1, hasSideEffects = 0 in
287 let isCodeGenOnly = 1, hasSideEffects = 0 in
[all …]
HDHexagonInstrInfoV3.td24 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicable = 1,
39 let isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs, isPredicated = 1,
67 let isCodeGenOnly = 1, isCall = 1, hasSideEffects = 1, Defs = VolatileV3.Regs in
101 let hasSideEffects = 0, isAsmParserOnly = 1 in
109 let hasSideEffects = 0 in
193 let Defs = [USR_OVF], hasSideEffects = 0 in
216 let hasSideEffects = 0, isAsmParserOnly = 1 in
222 let Defs = [USR_OVF], hasSideEffects = 0 in
HDHexagonInstrInfo.td66 let hasSideEffects = 0, isCompare = 1, InputType = "imm", isExtendable = 1,
118 let hasSideEffects = 0, hasNewValue = 1, InputType = "reg" in
141 let hasSideEffects = 0, hasNewValue = 1 in
255 let hasSideEffects = 0, hasNewValue = 1, isCompare = 1, InputType = "reg" in
310 let hasSideEffects = 0;
349 let hasNewValue = 1, hasSideEffects = 0 in
375 let hasNewValue = 1, hasSideEffects = 0 in
454 opExtentBits = 10, InputType = "imm", hasNewValue = 1, hasSideEffects = 0 in
471 let hasSideEffects = 0 in
484 let hasSideEffects = 0, hasNewValue = 1 in
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HDHexagonInstrInfoV4.td36 let hasSideEffects = 0 in
172 let hasSideEffects = 0;
217 let hasSideEffects = 0;
293 let hasSideEffects = 0, isExtentSigned = 1, isExtendable = 1,
329 let hasSideEffects = 0, isExtendable = 1, opExtentBits = 6, opExtendable = 2 in
395 hasSideEffects = 0 in
597 let hasSideEffects = 0, addrMode = BaseRegOffset in
1006 let addrMode = BaseRegOffset, InputType = "reg", hasSideEffects = 0 in {
1140 let hasSideEffects = 0, addrMode = BaseImmOffset,
1327 let mayStore = 1, isNVStore = 1, isNewValue = 1, hasSideEffects = 0,
[all …]
HDHexagonInstrInfoV5.td108 hasSideEffects = 0, validSubTargets = HasV5SubT, isCodeGenOnly = 1 in
115 isPredicatedFalse = 1, hasSideEffects = 0, validSubTargets = HasV5SubT in
216 hasSideEffects = 0, hasNewValue = 1 in
802 let Defs = [USR_OVF], hasSideEffects = 0, hasNewValue = 1, opNewValue = 0 in
833 let hasSideEffects = 0 in
859 hasSideEffects = 0, hasNewValue = 1, opNewValue = 0,
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIInstrFormats.td98 let hasSideEffects = 0;
230 let hasSideEffects = 0;
241 let hasSideEffects = 0;
255 let hasSideEffects = 0;
268 let hasSideEffects = 0;
280 let hasSideEffects = 0;
296 let hasSideEffects = 0;
592 let hasSideEffects = 0;
615 let hasSideEffects = 0;
627 let hasSideEffects = 0;
[all …]
HDR600Instructions.td85 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
214 } // End mayLoad = 1, mayStore = 0, hasSideEffects = 0
772 let hasSideEffects = 1 in {
776 } // end hasSideEffects
843 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
878 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1002 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in {
1018 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 0
1319 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in {
1328 } // End mayLoad = 0, mayStore = 0, hasSideEffects = 1
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/NextBSD/contrib/llvm/lib/IR/
HDInlineAsm.cpp29 StringRef Constraints, bool hasSideEffects, in get() argument
31 InlineAsmKeyType Key(AsmString, Constraints, hasSideEffects, isAlignStack, in get()
38 const std::string &constraints, bool hasSideEffects, in InlineAsm() argument
42 HasSideEffects(hasSideEffects), IsAlignStack(isAlignStack), in InlineAsm()
/NextBSD/contrib/llvm/tools/clang/lib/ARCMigrate/
HDTransEmptyStatementsAndDealloc.cpp103 if (hasSideEffects(condE, Ctx)) in VisitIfStmt()
117 if (hasSideEffects(condE, Ctx)) in VisitWhileStmt()
127 if (hasSideEffects(condE, Ctx)) in VisitDoStmt()
137 if (hasSideEffects(Exp, Ctx)) in VisitObjCForCollectionStmt()
HDTransforms.h180 bool hasSideEffects(Expr *E, ASTContext &Ctx);
HDTransforms.cpp175 bool trans::hasSideEffects(Expr *E, ASTContext &Ctx) { in hasSideEffects() function in trans
192 return hasSideEffects(ME->getInstanceReceiver(), Ctx); in hasSideEffects()
/NextBSD/contrib/llvm/include/llvm/IR/
HDInlineAsm.h52 const std::string &Constraints, bool hasSideEffects,
64 StringRef Constraints, bool hasSideEffects,
68 bool hasSideEffects() const { return HasSideEffects; } in hasSideEffects() function
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrExtension.td14 let hasSideEffects = 0 in {
42 let hasSideEffects = 0 in {
50 } // hasSideEffects = 0
68 let hasSideEffects = 0 in {
76 } // hasSideEffects = 0
97 let hasSideEffects = 0, isCodeGenOnly = 1 in {
HDX86InstrArithmetic.td18 let hasSideEffects = 0 in
68 let Defs = [AX,DX,EFLAGS], Uses = [AX], hasSideEffects = 0 in
73 let Defs = [EAX,EDX,EFLAGS], Uses = [EAX], hasSideEffects = 0 in
79 let Defs = [RAX,RDX,EFLAGS], Uses = [RAX], hasSideEffects = 0 in
94 let mayLoad = 1, hasSideEffects = 0 in {
110 let hasSideEffects = 0 in {
148 } // hasSideEffects
295 let hasSideEffects = 1 in { // so that we don't speculatively execute
367 } // hasSideEffects = 0
474 let CodeSize = 1, hasSideEffects = 0 in {
[all …]
HDX86InstrFMA.td72 let hasSideEffects = 0 in {
84 } // hasSideEffects = 0
158 let hasSideEffects = 0 in {
247 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in
324 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
HDX86InstrControl.td62 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
75 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
102 let isBranch = 1, isTerminator = 1, hasSideEffects = 0, SchedRW = [WriteJump] in {
186 let hasSideEffects = 0 in
HDX86InstrMMX.td257 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayLoad = 1 in
271 let hasSideEffects = 0 in
275 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
282 let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0, mayStore = 1 in
318 let isCodeGenOnly = 1, hasSideEffects = 1 in {
HDX86InstrInfo.td971 let hasSideEffects = 0, SchedRW = [WriteZero] in {
985 let Defs = [EBP, ESP], Uses = [EBP, ESP], mayLoad = 1, hasSideEffects=0 in
990 let Defs = [RBP,RSP], Uses = [RBP,RSP], mayLoad = 1, hasSideEffects = 0 in
1000 let Defs = [ESP], Uses = [ESP], hasSideEffects=0 in {
1044 let Defs = [ESP, EFLAGS], Uses = [ESP], mayLoad = 1, hasSideEffects=0,
1052 let Defs = [ESP], Uses = [ESP, EFLAGS], mayStore = 1, hasSideEffects=0,
1060 let Defs = [RSP], Uses = [RSP], hasSideEffects=0 in {
1079 let Defs = [RSP], Uses = [RSP], hasSideEffects = 0, mayStore = 1,
1088 let Defs = [RSP, EFLAGS], Uses = [RSP], mayLoad = 1, hasSideEffects=0 in
1091 let Defs = [RSP], Uses = [RSP, EFLAGS], mayStore = 1, hasSideEffects=0 in
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/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreInstrInfo.td374 let hasSideEffects = 1 in
385 let hasSideEffects = 0 in {
436 let hasSideEffects = 0 in
447 let hasSideEffects = 0 in
466 let hasSideEffects = 1 in {
542 let hasSideEffects = 0, isReMaterializable = 1 in
568 let mayLoad = 1, isReMaterializable = 1, hasSideEffects = 0 in {
597 let hasSideEffects = 0 in {
632 let hasSideEffects = 0 in
643 let hasSideEffects = 0 in
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/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrFormats.td797 let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
823 let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
985 let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
1186 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1201 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1477 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1505 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1617 let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
1652 let hasSideEffects = 0, isReMaterializable = 1, isAsCheapAsAMove = 1 in {
1685 let AddedComplexity = 1, hasSideEffects = 0 in {
[all …]
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstr64Bit.td239 let mayLoad = 1, hasSideEffects = 0 in {
249 let Defs = [CR0], mayStore = 1, hasSideEffects = 0 in
301 let hasSideEffects = 0 in {
318 } // hasSideEffects = 0
320 let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in {
352 let hasSideEffects = 1, Defs = [CTR8] in {
391 let hasSideEffects = 0 in {
542 let isCompare = 1, hasSideEffects = 0 in {
554 let hasSideEffects = 0 in {
658 let hasSideEffects = 0 in {
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/NextBSD/contrib/llvm/include/llvm/Target/
HDTarget.td403 // hasSideEffects - The instruction has side effects that are not
406 bit hasSideEffects = ?;
697 // The instruction properties mayLoad, mayStore, and hasSideEffects are unset
743 let hasSideEffects = 0; // Note side effect is encoded in an operand.
770 let hasSideEffects = 0;
776 let hasSideEffects = 0;
782 let hasSideEffects = 0;
789 let hasSideEffects = 0;
797 let hasSideEffects = 0;
803 let hasSideEffects = 0;
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/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrInfo.td19 let hasSideEffects = 0 in {
276 let hasSideEffects = 0 in {
299 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
415 let hasSideEffects = 0 in {
421 let hasSideEffects = 0 in {
465 let hasSideEffects = 0 in {
477 let hasSideEffects = 0 in {
559 let hasSideEffects = 0 in {
579 let hasSideEffects = 0, isAsCheapAsAMove = 1, isReMaterializable = 1,
593 let hasSideEffects = 0, isAsCheapAsAMove = 1, isMoveImm = 1,
[all …]
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenDAGPatterns.cpp2697 bool hasSideEffects; member in InstAnalyzer
2704 : CDP(cdp), hasSideEffects(false), mayStore(false), mayLoad(false), in InstAnalyzer()
2718 if (hasSideEffects || mayLoad || mayStore || isVariadic) in IsNodeBitcast()
2750 if (CP.hasProperty(SDNPSideEffect)) hasSideEffects = true; in AnalyzeNode()
2769 if (N->NodeHasProperty(SDNPSideEffect, CDP)) hasSideEffects = true; in AnalyzeNode()
2782 hasSideEffects = true; in AnalyzeNode()
2798 if (InstInfo.hasSideEffects != PatInfo.hasSideEffects && in InferFromPattern()
2803 if (!InstInfo.hasSideEffects) { in InferFromPattern()
2806 Twine(InstInfo.hasSideEffects)); in InferFromPattern()
2827 InstInfo.hasSideEffects |= PatInfo.hasSideEffects; in InferFromPattern()
[all …]
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMInstrThumb.td252 // FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
255 let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
719 let hasSideEffects = 0 in {
759 } // hasSideEffects
893 let hasSideEffects = 0 in
1053 let hasSideEffects = 0 in {
1075 } // hasSideEffects
1253 let hasSideEffects = 0, isReMaterializable = 1 in
1257 let hasSideEffects = 1 in
1289 hasSideEffects = 1, isBarrier = 1, isCodeGenOnly = 1,
[all …]

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