| /NextBSD/contrib/llvm/lib/Target/ARM/MCTargetDesc/ |
| HD | ARMMCCodeEmitter.cpp | 534 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); in getMachineOpValue() 564 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in EncodeAddrModeOpValues() 873 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue() 874 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue() 891 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrModeImm12OpValue() 975 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getT2AddrModeImm8s4OpValue() 1012 unsigned Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getT2AddrModeImm0_1020s4OpValue() 1080 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getLdStSORegOpValue() 1081 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getLdStSORegOpValue() 1116 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrMode2OpValue() [all …]
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsFrameLowering.cpp | 98 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasFP() 107 const TargetRegisterInfo *TRI = STI.getRegisterInfo(); in hasBP() 114 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); in estimateStackSize()
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| HD | MipsSEInstrInfo.cpp | 32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { in getRegisterInfo() function in MipsSEInstrInfo 446 const MipsRegisterInfo *RI = &getRegisterInfo(); in compareOpndSize() 481 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandPseudoMTLoHi() 482 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi() 503 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt() 506 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); in expandCvtFPInt() 522 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); in expandExtractElementF64() 558 const TargetRegisterInfo &TRI = getRegisterInfo(); in expandBuildPairF64()
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| HD | MipsSubtarget.h | 285 const MipsRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 286 return &InstrInfo->getRegisterInfo(); in getRegisterInfo()
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| HD | Mips16FrameLowering.cpp | 49 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); in emitPrologue() 161 const MipsRegisterInfo &RI = TII.getRegisterInfo(); in determineCalleeSaves()
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| /NextBSD/contrib/llvm/lib/Target/XCore/ |
| HD | XCoreSubtarget.h | 60 const TargetRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 61 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /NextBSD/contrib/llvm/lib/Target/BPF/ |
| HD | BPFSubtarget.h | 58 const TargetRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 59 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /NextBSD/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430Subtarget.h | 57 const TargetRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 58 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcSubtarget.h | 53 const SparcRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 54 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | TargetFrameLoweringImpl.cpp | 47 const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo(); in getFrameIndexReference() 65 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo(); in determineCalleeSaves()
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| HD | MIRPrinter.cpp | 114 convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo()); in print() 237 const auto *TRI = MBB.getParent()->getSubtarget().getRegisterInfo(); in convert() 257 const auto *TRI = MF.getSubtarget().getRegisterInfo(); in initRegisterMaskIds() 265 const auto *TRI = SubTarget.getRegisterInfo(); in print()
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| HD | RegisterClassInfo.cpp | 40 if (MF->getSubtarget().getRegisterInfo() != TRI) { in runOnMachineFunction() 41 TRI = MF->getSubtarget().getRegisterInfo(); in runOnMachineFunction()
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| HD | StackMaps.cpp | 91 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo(); in parseOperand() 159 AP.MF ? AP.MF->getSubtarget().getRegisterInfo() : nullptr; in print() 240 const TargetRegisterInfo *TRI = AP.MF->getSubtarget().getRegisterInfo(); in parseRegisterLiveOutMask() 335 const TargetRegisterInfo *RegInfo = AP.MF->getSubtarget().getRegisterInfo(); in recordStackMapOpers()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonSubtarget.h | 64 const HexagonRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 65 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /NextBSD/contrib/llvm/lib/Target/SystemZ/ |
| HD | SystemZSubtarget.h | 66 const SystemZRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 67 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| /NextBSD/contrib/llvm/lib/Target/NVPTX/ |
| HD | NVPTXSubtarget.h | 62 const NVPTXRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 63 return &InstrInfo.getRegisterInfo(); in getRegisterInfo()
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| HD | NVPTXPrologEpilogPass.cpp | 53 const TargetRegisterInfo &TRI = *STI.getRegisterInfo(); in runOnMachineFunction() 113 const TargetRegisterInfo *RegInfo = Fn.getSubtarget().getRegisterInfo(); in calculateFrameObjectOffsets()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64Subtarget.h | 89 const AArch64RegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 90 return &getInstrInfo()->getRegisterInfo(); in getRegisterInfo()
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| HD | AArch64FrameLowering.cpp | 142 const TargetRegisterInfo *RegInfo = MF.getSubtarget().getRegisterInfo(); in hasFP() 210 const MCRegisterInfo *MRI = MMI.getContext().getRegisterInfo(); in emitCalleeSavedFrameMoves() 284 MF.getSubtarget().getRegisterInfo()); in emitPrologue() 542 MF.getSubtarget().getRegisterInfo()); in emitEpilogue() 663 MF.getSubtarget().getRegisterInfo()); in resolveFrameIndexReference() 890 MF.getSubtarget().getRegisterInfo()); in determineCalleeSaves()
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| /NextBSD/contrib/llvm/lib/Target/AMDGPU/ |
| HD | AMDGPUSubtarget.h | 112 const AMDGPURegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 113 return &InstrInfo->getRegisterInfo(); in getRegisterInfo()
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| HD | R600ExpandSpecialInstrs.cpp | 71 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() 179 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction() 200 const R600RegisterInfo &TRI = TII->getRegisterInfo(); in runOnMachineFunction()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCSubtarget.h | 170 const PPCRegisterInfo *getRegisterInfo() const override { in getRegisterInfo() function 171 return &getInstrInfo()->getRegisterInfo(); in getRegisterInfo()
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| /NextBSD/contrib/llvm/lib/Target/WebAssembly/ |
| HD | WebAssemblyInstrInfo.h | 32 const WebAssemblyRegisterInfo &getRegisterInfo() const { return RI; } in getRegisterInfo() function
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| /NextBSD/contrib/llvm/lib/Target/AArch64/Disassembler/ |
| HD | AArch64ExternalSymbolizer.cpp | 95 const MCRegisterInfo &MCRI = *Ctx.getRegisterInfo(); in tryAddingSymbolicOperand() 121 const MCRegisterInfo &MCRI = *Ctx.getRegisterInfo(); in tryAddingSymbolicOperand()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86MachineFunctionInfo.cpp | 21 MF->getSubtarget().getRegisterInfo()); in setRestoreBasePointer()
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