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Searched refs:getOperand (Results 1 – 25 of 541) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/X86/InstPrinter/
HDX86InstComments.cpp130 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
134 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) in EmitAnyX86InstComments()
136 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments()
138 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
139 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
142 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
145 if (MI->getOperand(MI->getNumOperands() - 1).isImm()) in EmitAnyX86InstComments()
147 MI->getOperand(MI->getNumOperands() - 1).getImm(), in EmitAnyX86InstComments()
149 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
150 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
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/NextBSD/contrib/llvm/lib/Target/Hexagon/MCTargetDesc/
HDHexagonMCDuplexInfo.cpp193 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
194 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
199 MCI.getOperand(2).isImm() && in getDuplexCandidateGroup()
200 isShiftedUInt<5, 2>(MCI.getOperand(2).getImm())) { in getDuplexCandidateGroup()
205 (MCI.getOperand(2).isImm() && in getDuplexCandidateGroup()
206 isShiftedUInt<4, 2>(MCI.getOperand(2).getImm()))) { in getDuplexCandidateGroup()
213 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
214 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
217 MCI.getOperand(2).isImm() && isUInt<4>(MCI.getOperand(2).getImm())) { in getDuplexCandidateGroup()
234 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
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HDHexagonMCCompound.cpp100 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
101 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
102 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
114 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
115 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
118 MI.getOperand(2).isImm() && ((isUInt<5>(MI.getOperand(2).getImm())) || in getCompoundCandidateGroup()
119 (MI.getOperand(2).getImm() == -1))) in getCompoundCandidateGroup()
126 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
127 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
136 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
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/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
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HDSystemZInstrInfo.cpp61 MachineOperand &HighRegOp = EarlierMI->getOperand(0); in splitMove()
62 MachineOperand &LowRegOp = MI->getOperand(0); in splitMove()
68 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2); in splitMove()
69 MachineOperand &LowOffsetOp = MI->getOperand(2); in splitMove()
86 MachineOperand &OffsetMO = MI->getOperand(2); in splitAdjDynAlloc()
106 unsigned Reg = MI->getOperand(0).getReg(); in expandRIPseudo()
110 MI->getOperand(1).setImm(uint32_t(MI->getOperand(1).getImm())); in expandRIPseudo()
120 unsigned DestReg = MI->getOperand(0).getReg(); in expandRIEPseudo()
121 unsigned SrcReg = MI->getOperand(1).getReg(); in expandRIEPseudo()
129 MI->getOperand(1).isKill()); in expandRIEPseudo()
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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCVSXFMAMutate.cpp105 LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
123 unsigned AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
125 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
131 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
157 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
174 if (LIS->getInterval(MI->getOperand(2).getReg()) in processBlock()
178 } else if (LIS->getInterval(MI->getOperand(3).getReg()) in processBlock()
200 unsigned AddReg = AddendMI->getOperand(1).getReg(); in processBlock()
201 unsigned KilledProdReg = MI->getOperand(KilledProdOp).getReg(); in processBlock()
202 unsigned OtherProdReg = MI->getOperand(OtherProdOp).getReg(); in processBlock()
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HDPPCISelDAGToDAG.cpp402 && isInt32Immediate(N->getOperand(1).getNode(), Imm); in isOpcWithIntImmediate()
429 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) in isRotateAndMask()
462 SDValue Op0 = N->getOperand(0); in SelectBitfieldInsert()
463 SDValue Op1 = N->getOperand(1); in SelectBitfieldInsert()
483 if (Op0.getOperand(0).getOpcode() == ISD::SHL || in SelectBitfieldInsert()
484 Op0.getOperand(0).getOpcode() == ISD::SRL) { in SelectBitfieldInsert()
485 if (Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
486 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
493 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
494 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600ClauseMergePass.cpp76 return MI->getOperand( in getCFAluSize()
82 return MI->getOperand( in isCFAluEnabled()
99 CFAlu->getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
124 if (LatrCFAlu->getOperand(Mode0Idx).getImm() && in mergeIfPossible()
125 RootCFAlu->getOperand(Mode0Idx).getImm() && in mergeIfPossible()
126 (LatrCFAlu->getOperand(KBank0Idx).getImm() != in mergeIfPossible()
127 RootCFAlu->getOperand(KBank0Idx).getImm() || in mergeIfPossible()
128 LatrCFAlu->getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
129 RootCFAlu->getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
140 if (LatrCFAlu->getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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HDR600ISelLowering.cpp211 if (!MRI.use_empty(MI->getOperand(DstIdx).getReg()) || in EmitInstrWithCustomInserter()
218 NewMI.addOperand(MI->getOperand(i)); in EmitInstrWithCustomInserter()
227 MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
228 MI->getOperand(1).getReg()); in EmitInstrWithCustomInserter()
236 MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
237 MI->getOperand(1).getReg()); in EmitInstrWithCustomInserter()
245 MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
246 MI->getOperand(1).getReg()); in EmitInstrWithCustomInserter()
252 unsigned maskedRegister = MI->getOperand(0).getReg(); in EmitInstrWithCustomInserter()
260 TII->buildMovImm(*BB, I, MI->getOperand(0).getReg(), in EmitInstrWithCustomInserter()
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/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelDAGToDAG.cpp513 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in SelectIntrinsicChain()
548 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in SelectIntrinsicNoChain()
559 SDValue Wrapper = N->getOperand(1); in SelectTexSurfHandle()
560 SDValue GlobalVal = Wrapper.getOperand(0); in SelectTexSurfHandle()
566 SDValue Src = N->getOperand(0); in SelectAddrSpaceCast()
680 SDValue Chain = N->getOperand(0); in SelectLoad()
681 SDValue N1 = N->getOperand(1); in SelectLoad()
860 SDValue Chain = N->getOperand(0); in SelectLoadVector()
861 SDValue Op1 = N->getOperand(1); in SelectLoadVector()
898 N->getOperand(N->getNumOperands() - 1))->getZExtValue(); in SelectLoadVector()
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/NextBSD/contrib/llvm/lib/Target/ARM/InstPrinter/
HDARMInstPrinter.cpp79 switch (MI->getOperand(0).getImm()) { in printInst()
115 const MCOperand &Dst = MI->getOperand(0); in printInst()
116 const MCOperand &MO1 = MI->getOperand(1); in printInst()
117 const MCOperand &MO2 = MI->getOperand(2); in printInst()
118 const MCOperand &MO3 = MI->getOperand(3); in printInst()
138 const MCOperand &Dst = MI->getOperand(0); in printInst()
139 const MCOperand &MO1 = MI->getOperand(1); in printInst()
140 const MCOperand &MO2 = MI->getOperand(2); in printInst()
165 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
179 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
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/NextBSD/contrib/llvm/lib/Target/Mips/MCTargetDesc/
HDMipsMCCodeEmitter.cpp55 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
57 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
63 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
95 assert(InstIn.getOperand(2).isImm()); in LowerDextDins()
96 int64_t pos = InstIn.getOperand(2).getImm(); in LowerDextDins()
97 assert(InstIn.getOperand(3).isImm()); in LowerDextDins()
98 int64_t size = InstIn.getOperand(3).getImm(); in LowerDextDins()
104 InstIn.getOperand(2).setImm(pos - 32); in LowerDextDins()
110 InstIn.getOperand(3).setImm(size - 32); in LowerDextDins()
221 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
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/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelDAGToDAG.cpp98 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
99 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
129 OutOps.push_back(Op.getOperand(0)); in SelectInlineAsmMemoryOperand()
162 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
163 N->getOperand(2) }; in Select()
168 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
169 N->getOperand(2) }; in Select()
174 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
175 N->getOperand(2), N->getOperand(3) }; in Select()
180 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelLowering.cpp395 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); in selectMADD()
400 SDValue MultHi = ADDENode->getOperand(0); in selectMADD()
401 SDValue MultLo = ADDCNode->getOperand(0); in selectMADD()
432 ADDCNode->getOperand(1), in selectMADD()
433 ADDENode->getOperand(1)); in selectMADD()
439 MultNode->getOperand(0),// Factor 0 in selectMADD()
440 MultNode->getOperand(1),// Factor 1 in selectMADD()
467 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); in selectMSUB()
472 SDValue MultHi = SUBENode->getOperand(1); in selectMSUB()
473 SDValue MultLo = SUBCNode->getOperand(1); in selectMSUB()
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/NextBSD/contrib/llvm/lib/Transforms/InstCombine/
HDInstCombineVectorOps.cpp47 isa<ConstantInt>(I->getOperand(2))) in CheapToScalarize()
53 (CheapToScalarize(BO->getOperand(0), isConstant) || in CheapToScalarize()
54 CheapToScalarize(BO->getOperand(1), isConstant))) in CheapToScalarize()
58 (CheapToScalarize(CI->getOperand(0), isConstant) || in CheapToScalarize()
59 CheapToScalarize(CI->getOperand(1), isConstant))) in CheapToScalarize()
103 unsigned opId = (B0->getOperand(0) == PN) ? 1 : 0; in scalarizePHI()
105 ExtractElementInst::Create(B0->getOperand(opId), Elt, in scalarizePHI()
106 B0->getOperand(opId)->getName() + ".Elt"), in scalarizePHI()
139 if (Constant *C = dyn_cast<Constant>(EI.getOperand(0))) in visitExtractElementInst()
145 if (ConstantInt *IdxC = dyn_cast<ConstantInt>(EI.getOperand(1))) { in visitExtractElementInst()
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HDInstCombineShifts.cpp25 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType()); in commonShiftTransforms()
26 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms()
94 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
97 return CanEvaluateTruncated(I->getOperand(0), Ty); in CanEvaluateShifted()
114 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC, I) && in CanEvaluateShifted()
115 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC, I); in CanEvaluateShifted()
119 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
134 if (IC.MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
144 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
159 if (IC.MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
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HDInstCombineSimplifyDemanded.cpp35 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo)); in ShrinkDemandedConstant()
161 computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth + 1, in SimplifyDemandedUseBits()
163 computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth + 1, in SimplifyDemandedUseBits()
171 return I->getOperand(0); in SimplifyDemandedUseBits()
174 return I->getOperand(1); in SimplifyDemandedUseBits()
185 computeKnownBits(I->getOperand(1), RHSKnownZero, RHSKnownOne, Depth + 1, in SimplifyDemandedUseBits()
187 computeKnownBits(I->getOperand(0), LHSKnownZero, LHSKnownOne, Depth + 1, in SimplifyDemandedUseBits()
195 return I->getOperand(0); in SimplifyDemandedUseBits()
198 return I->getOperand(1); in SimplifyDemandedUseBits()
204 return I->getOperand(0); in SimplifyDemandedUseBits()
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/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp565 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
569 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
583 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, in isNegatibleForFree()
587 return isNegatibleForFree(Op.getOperand(1), LegalOperations, TLI, Options, in isNegatibleForFree()
593 return isNegatibleForFree(Op.getOperand(0), LegalOperations, TLI, Options, in isNegatibleForFree()
603 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
621 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, in GetNegatedExpression()
624 GetNegatedExpression(Op.getOperand(0), DAG, in GetNegatedExpression()
626 Op.getOperand(1)); in GetNegatedExpression()
629 GetNegatedExpression(Op.getOperand(1), DAG, in GetNegatedExpression()
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HDTargetLowering.cpp296 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)); in ShrinkDemandedConstant()
306 SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0), in ShrinkDemandedConstant()
357 Op.getNode()->getOperand(0)), in ShrinkDemandedOp()
359 Op.getNode()->getOperand(1))); in ShrinkDemandedOp()
424 if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(Op.getOperand(1))) { in SimplifyDemandedBits()
427 TLO.DAG.computeKnownBits(Op.getOperand(0), LHSZero, LHSOne, Depth); in SimplifyDemandedBits()
430 return TLO.CombineTo(Op, Op.getOperand(0)); in SimplifyDemandedBits()
437 if (SimplifyDemandedBits(Op.getOperand(1), NewMask, KnownZero, in SimplifyDemandedBits()
441 if (SimplifyDemandedBits(Op.getOperand(0), ~KnownZero & NewMask, in SimplifyDemandedBits()
449 return TLO.CombineTo(Op, Op.getOperand(0)); in SimplifyDemandedBits()
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/NextBSD/contrib/llvm/lib/Target/ARM/AsmParser/
HDARMAsmParser.cpp4710 Inst.addOperand(Inst.getOperand(0)); in cvtThumbMultiply()
6042 unsigned OpReg = Inst.getOperand(i).getReg(); in checkLowRegisterList()
6056 unsigned OpReg = Inst.getOperand(i).getReg(); in listContainsReg()
6135 unsigned Cond = Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm(); in validateInstruction()
6151 Inst.getOperand(MCID.findFirstPredOperandIdx()).getImm() != in validateInstruction()
6161 const unsigned RtReg = Inst.getOperand(0).getReg(); in validateInstruction()
6175 const unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
6181 const unsigned Rn = MRI->getEncodingValue(Inst.getOperand(3).getReg()); in validateInstruction()
6196 unsigned Rt = MRI->getEncodingValue(Inst.getOperand(0).getReg()); in validateInstruction()
6197 unsigned Rt2 = MRI->getEncodingValue(Inst.getOperand(1).getReg()); in validateInstruction()
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/NextBSD/contrib/llvm/tools/lldb/source/Plugins/Instruction/MIPS/
HDEmulateInstructionMIPS.cpp627 const uint32_t imm16 = insn.getOperand(2).getImm(); in Emulate_ADDiu()
632 dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); in Emulate_ADDiu()
633 src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); in Emulate_ADDiu()
663 uint32_t imm16 = insn.getOperand(2).getImm(); in Emulate_SW()
667 src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); in Emulate_SW()
668 base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); in Emulate_SW()
717 src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); in Emulate_LW()
718 base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); in Emulate_LW()
753 rs = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); in Emulate_BEQ()
754 rt = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); in Emulate_BEQ()
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/NextBSD/contrib/llvm/lib/Target/PowerPC/InstPrinter/
HDPPCInstPrinter.cpp60 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
61 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
62 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
83 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
93 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
94 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
116 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
159 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
255 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
262 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU2ImmOperand()
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/NextBSD/contrib/llvm/lib/Target/ARM/MCTargetDesc/
HDARMMCTargetDesc.cpp37 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
38 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
41 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
42 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
43 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
50 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
57 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
58 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
68 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() && in getITDeprecationInfo()
69 MI.getOperand(1).getImm() != 8) { in getITDeprecationInfo()
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/NextBSD/contrib/llvm/tools/lldb/source/Plugins/Instruction/MIPS64/
HDEmulateInstructionMIPS64.cpp630 const uint32_t imm16 = insn.getOperand(2).getImm(); in Emulate_DADDiu()
635 dst = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); in Emulate_DADDiu()
636 src = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); in Emulate_DADDiu()
670 base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); in Emulate_SW()
671 imm = insn.getOperand(2).getImm(); in Emulate_SW()
700 base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); in Emulate_LW()
701 imm = insn.getOperand(2).getImm(); in Emulate_LW()
729 uint32_t imm16 = insn.getOperand(2).getImm(); in Emulate_SD()
734 src = m_reg_info->getEncodingValue (insn.getOperand(0).getReg()); in Emulate_SD()
735 base = m_reg_info->getEncodingValue (insn.getOperand(1).getReg()); in Emulate_SD()
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/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelDAGToDAG.cpp89 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { in SelectADDRri()
92 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { in SelectADDRri()
97 Base = Addr.getOperand(0); in SelectADDRri()
104 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
105 Base = Addr.getOperand(1); in SelectADDRri()
106 Offset = Addr.getOperand(0).getOperand(0); in SelectADDRri()
109 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
110 Base = Addr.getOperand(0); in SelectADDRri()
111 Offset = Addr.getOperand(1).getOperand(0); in SelectADDRri()
128 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRrr()
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