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Searched refs:getOpcode (Results 1 – 25 of 489) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelDAGToDAG.cpp83 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRri()
84 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRri()
85 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRri()
88 if (Addr.getOpcode() == ISD::ADD) { in SelectADDRri()
104 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
109 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
121 if (Addr.getOpcode() == ISD::FrameIndex) return false; in SelectADDRrr()
122 if (Addr.getOpcode() == ISD::TargetExternalSymbol || in SelectADDRrr()
123 Addr.getOpcode() == ISD::TargetGlobalAddress || in SelectADDRrr()
124 Addr.getOpcode() == ISD::TargetGlobalTLSAddress) in SelectADDRrr()
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HDDelaySlotFiller.cpp119 (MI->getOpcode() == SP::RESTORErr in runOnMachineBasicBlock()
120 || MI->getOpcode() == SP::RESTOREri)) { in runOnMachineBasicBlock()
126 (MI->getOpcode() == SP::FCMPS || MI->getOpcode() == SP::FCMPD in runOnMachineBasicBlock()
127 || MI->getOpcode() == SP::FCMPQ)) { in runOnMachineBasicBlock()
178 if (slot->getOpcode() == SP::RET || slot->getOpcode() == SP::TLS_CALL) in findDelayInstr()
181 if (slot->getOpcode() == SP::RETL) { in findDelayInstr()
185 if (J->getOpcode() == SP::RESTORErr in findDelayInstr()
186 || J->getOpcode() == SP::RESTOREri) { in findDelayInstr()
280 switch(MI->getOpcode()) { in insertCallDefsUses()
319 if (MO.isImplicit() && MI->getOpcode() == SP::RETL) in insertDefsUses()
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/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDSelectionDAGNodes.h163 inline unsigned getOpcode() const;
385 unsigned getOpcode() const { return (unsigned short)NodeType; }
885 inline unsigned SDValue::getOpcode() const {
886 return Node->getOpcode();
1057 return isBinOpWithFlags(N->getOpcode());
1102 return N->getOpcode() == ISD::ADDRSPACECAST;
1189 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
1196 return N->getOpcode() == ISD::LOAD ||
1197 N->getOpcode() == ISD::STORE ||
1198 N->getOpcode() == ISD::PREFETCH ||
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HDMachineInstr.h267 unsigned getOpcode() const { return MCID->Opcode; }
736 bool isEHLabel() const { return getOpcode() == TargetOpcode::EH_LABEL; }
737 bool isGCLabel() const { return getOpcode() == TargetOpcode::GC_LABEL; }
742 return getOpcode() == TargetOpcode::CFI_INSTRUCTION;
748 bool isDebugValue() const { return getOpcode() == TargetOpcode::DBG_VALUE; }
757 bool isPHI() const { return getOpcode() == TargetOpcode::PHI; }
758 bool isKill() const { return getOpcode() == TargetOpcode::KILL; }
759 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
760 bool isInlineAsm() const { return getOpcode() == TargetOpcode::INLINEASM; }
762 return getOpcode() == TargetOpcode::INLINEASM && getInlineAsmDialect();
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/NextBSD/contrib/llvm/include/llvm/IR/
HDOperator.h48 unsigned getOpcode() const { in getOpcode() function
50 return I->getOpcode(); in getOpcode()
51 return cast<ConstantExpr>(this)->getOpcode(); in getOpcode()
56 static unsigned getOpcode(const Value *V) { in getOpcode() function
58 return I->getOpcode(); in getOpcode()
60 return CE->getOpcode(); in getOpcode()
107 return I->getOpcode() == Instruction::Add || in classof()
108 I->getOpcode() == Instruction::Sub || in classof()
109 I->getOpcode() == Instruction::Mul || in classof()
110 I->getOpcode() == Instruction::Shl; in classof()
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HDInstruction.h112 unsigned getOpcode() const { return getValueID() - InstructionVal; }
114 const char *getOpcodeName() const { return getOpcodeName(getOpcode()); }
115 bool isTerminator() const { return isTerminator(getOpcode()); }
116 bool isBinaryOp() const { return isBinaryOp(getOpcode()); }
117 bool isShift() { return isShift(getOpcode()); }
118 bool isCast() const { return isCast(getOpcode()); }
138 return getOpcode() == Shl || getOpcode() == LShr;
143 return getOpcode() == AShr;
327 bool isCommutative() const { return isCommutative(getOpcode()); }
336 bool isIdempotent() const { return isIdempotent(getOpcode()); }
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/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonNewValueJump.cpp131 if (II->getOpcode() == TargetOpcode::KILL) in INITIALIZE_PASS_DEPENDENCY()
181 if (MII->getOpcode() == Hexagon::J2_call) in commonChecksToProhibitNewValueJump()
195 if (MII->getOpcode() == TargetOpcode::KILL || in commonChecksToProhibitNewValueJump()
196 MII->getOpcode() == TargetOpcode::PHI || in commonChecksToProhibitNewValueJump()
197 MII->getOpcode() == TargetOpcode::COPY) in commonChecksToProhibitNewValueJump()
204 if (MII->getOpcode() == Hexagon::LDriw_pred || in commonChecksToProhibitNewValueJump()
205 MII->getOpcode() == Hexagon::STriw_pred) in commonChecksToProhibitNewValueJump()
229 ((MI->getOpcode() == Hexagon::C2_cmpeqi || in canCompareBeNewValueJump()
230 MI->getOpcode() == Hexagon::C2_cmpgti) && in canCompareBeNewValueJump()
247 if (def->getOpcode() == TargetOpcode::COPY) in canCompareBeNewValueJump()
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/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCBranchSelector.cpp143 if (I->getOpcode() == PPC::BCC && !I->getOperand(2).isImm()) in runOnMachineFunction()
145 else if ((I->getOpcode() == PPC::BC || I->getOpcode() == PPC::BCn) && in runOnMachineFunction()
148 else if ((I->getOpcode() == PPC::BDNZ8 || I->getOpcode() == PPC::BDNZ || in runOnMachineFunction()
149 I->getOpcode() == PPC::BDZ8 || I->getOpcode() == PPC::BDZ) && in runOnMachineFunction()
188 if (I->getOpcode() == PPC::BCC) { in runOnMachineFunction()
199 } else if (I->getOpcode() == PPC::BC) { in runOnMachineFunction()
202 } else if (I->getOpcode() == PPC::BCn) { in runOnMachineFunction()
205 } else if (I->getOpcode() == PPC::BDNZ) { in runOnMachineFunction()
207 } else if (I->getOpcode() == PPC::BDNZ8) { in runOnMachineFunction()
209 } else if (I->getOpcode() == PPC::BDZ) { in runOnMachineFunction()
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HDPPCEarlyReturn.cpp66 (I->getOpcode() != PPC::BLR && I->getOpcode() != PPC::BLR8) || in processBlock()
76 if (J->getOpcode() == PPC::B) { in processBlock()
81 BuildMI(**PI, J, J->getDebugLoc(), TII->get(I->getOpcode())); in processBlock()
89 } else if (J->getOpcode() == PPC::BCC) { in processBlock()
103 } else if (J->getOpcode() == PPC::BC || J->getOpcode() == PPC::BCn) { in processBlock()
108 TII->get(J->getOpcode() == PPC::BC ? in processBlock()
HDPPCInstrInfo.cpp193 switch (MI.getOpcode()) { in isCoalescableExtInstr()
207 switch (MI->getOpcode()) { in isLoadFromStackSlot()
236 switch (MI->getOpcode()) { in isStoreToStackSlot()
269 if (MI->getOpcode() != PPC::RLWIMI && in commuteInstruction()
270 MI->getOpcode() != PPC::RLWIMIo) in commuteInstruction()
352 int AltOpc = PPC::getAltVSXFMAOpcode(MI->getOpcode()); in findCommutedOpIndices()
405 if (LastInst->getOpcode() == PPC::B) { in AnalyzeBranch()
410 } else if (LastInst->getOpcode() == PPC::BCC) { in AnalyzeBranch()
418 } else if (LastInst->getOpcode() == PPC::BC) { in AnalyzeBranch()
426 } else if (LastInst->getOpcode() == PPC::BCn) { in AnalyzeBranch()
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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600EmitClauseMarkers.cpp42 switch (MI->getOpcode()) { in OccupiedDwords()
56 if (TII->isLDSRetInstr(MI->getOpcode())) in OccupiedDwords()
60 TII->isCubeOp(MI->getOpcode()) || in OccupiedDwords()
61 TII->isReductionOp(MI->getOpcode())) in OccupiedDwords()
75 if (TII->isALUInstr(MI->getOpcode())) in isALU()
77 if (TII->isVector(*MI) || TII->isCubeOp(MI->getOpcode())) in isALU()
79 switch (MI->getOpcode()) { in isALU()
93 switch (MI->getOpcode()) { in IsTrivialInst()
122 if (!TII->isALUInstr(MI->getOpcode()) && MI->getOpcode() != AMDGPU::DOT_4) in SubstituteKCacheBank()
127 assert((TII->isALUInstr(MI->getOpcode()) || in SubstituteKCacheBank()
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HDR600Packetizer.cpp76 if (!TII->isALUInstr(I->getOpcode()) && !I->isBundle()) in getPreviousVector()
90 int OperandIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::write); in getPreviousVector()
93 int DstIdx = TII->getOperandIdx(BI->getOpcode(), AMDGPU::OpName::dst); in getPreviousVector()
102 if (BI->getOpcode() == AMDGPU::DOT4_r600 || in getPreviousVector()
103 BI->getOpcode() == AMDGPU::DOT4_eg) { in getPreviousVector()
140 int OperandIdx = TII->getOperandIdx(MI->getOpcode(), Ops[i]); in substitutePV()
175 if (!TII->isALUInstr(MI->getOpcode())) in isSoloInstruction()
177 if (MI->getOpcode() == AMDGPU::GROUP_BARRIER) in isSoloInstruction()
181 if (TII->isLDSInstr(MI->getOpcode())) in isSoloInstruction()
193 int OpI = TII->getOperandIdx(MII->getOpcode(), AMDGPU::OpName::pred_sel), in isLegalToPacketizeTogether()
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HDR600InstrInfo.cpp39 return get(MI.getOpcode()).TSFlags & R600_InstFlag::TRIG; in isTrig()
43 return get(MI.getOpcode()).TSFlags & R600_InstFlag::VECTOR; in isVector()
162 if (isALUInstr(MI->getOpcode())) in canBeConsideredALU()
164 if (isVector(*MI) || isCubeOp(MI->getOpcode())) in canBeConsideredALU()
166 switch (MI->getOpcode()) { in canBeConsideredALU()
186 return isTransOnly(MI->getOpcode()); in isTransOnly()
194 return isVectorOnly(MI->getOpcode()); in isVectorOnly()
209 usesVertexCache(MI->getOpcode()); in usesVertexCache()
220 usesVertexCache(MI->getOpcode())) || in usesTextureCache()
221 usesTextureCache(MI->getOpcode()); in usesTextureCache()
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HDSIInsertWaits.cpp142 uint64_t TSFlags = TII->get(MI.getOpcode()).TSFlags; in getHwCounts()
149 (MI.getOpcode() == AMDGPU::EXP || MI.getDesc().mayStore())); in getHwCounts()
154 if (TII->isSMRD(MI.getOpcode())) { in getHwCounts()
187 if (MI.getOpcode() == AMDGPU::EXP) in isOpRelevant()
199 if (TII->isDS(MI.getOpcode())) { in isOpRelevant()
273 if ((LastOpcodeType == SMEM && TII->isSMRD(I->getOpcode())) || in pushInstruction()
281 if (TII->isSMRD(I->getOpcode())) in pushInstruction()
289 ExpInstrTypesSeen |= I->getOpcode() == AMDGPU::EXP ? 1 : 2; in pushInstruction()
317 if (I != MBB.end() && I->getOpcode() == AMDGPU::S_ENDPGM) in insertWait()
390 if (MI.getOpcode() == AMDGPU::S_SENDMSG) in handleOperands()
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HDSIShrinkInstructions.cpp98 switch (MI.getOpcode()) { in canShrink()
144 assert(TII->isVOP1(MI.getOpcode()) || TII->isVOP2(MI.getOpcode()) || in foldImmediates()
145 TII->isVOPC(MI.getOpcode())); in foldImmediates()
148 int Src0Idx = AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::src0); in foldImmediates()
207 if (MI.getOpcode() == AMDGPU::S_MOV_B32) { in runOnMachineFunction()
218 if (!TII->hasVALU32BitEncoding(MI.getOpcode())) in runOnMachineFunction()
231 if (!TII->hasVALU32BitEncoding(MI.getOpcode())) in runOnMachineFunction()
234 int Op32 = AMDGPU::getVOPe32(MI.getOpcode()); in runOnMachineFunction()
/NextBSD/contrib/llvm/lib/Transforms/InstCombine/
HDInstCombineShifts.cpp108 switch (I->getOpcode()) { in CanEvaluateShifted()
206 switch (I->getOpcode()) { in GetShiftedValue()
323 bool isLeftShift = I.getOpcode() == Instruction::Shl; in FoldShiftByConstant()
338 if (I.getOpcode() != Instruction::AShr && in FoldShiftByConstant()
356 if (BO->getOpcode() == Instruction::Mul && isLeftShift) in FoldShiftByConstant()
382 Value *NSh = Builder->CreateBinOp(I.getOpcode(), TrOp, ShAmt,I.getName()); in FoldShiftByConstant()
396 if (I.getOpcode() == Instruction::Shl) in FoldShiftByConstant()
399 assert(I.getOpcode() == Instruction::LShr && "Unknown logical shift"); in FoldShiftByConstant()
418 switch (Op0BO->getOpcode()) { in FoldShiftByConstant()
432 Value *X = Builder->CreateBinOp(Op0BO->getOpcode(), YS, V1, in FoldShiftByConstant()
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/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDDAGCombiner.cpp136 if (N->getOpcode() == ISD::HANDLENODE) in AddToWorklist()
541 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
549 switch (Op.getOpcode()) { in isNegatibleForFree()
603 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
609 switch (Op.getOpcode()) { in GetNegatedExpression()
652 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
658 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
665 return DAG.getNode(Op.getOpcode(), SDLoc(Op), Op.getValueType(), in GetNegatedExpression()
683 if (N.getOpcode() == ISD::SETCC) { in isSetCCEquivalent()
690 if (N.getOpcode() != ISD::SELECT_CC || in isSetCCEquivalent()
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/NextBSD/contrib/llvm/include/llvm/MC/
HDMCInstrAnalysis.h35 return Info->get(Inst.getOpcode()).isBranch(); in isBranch()
39 return Info->get(Inst.getOpcode()).isConditionalBranch(); in isConditionalBranch()
43 return Info->get(Inst.getOpcode()).isUnconditionalBranch(); in isUnconditionalBranch()
47 return Info->get(Inst.getOpcode()).isIndirectBranch(); in isIndirectBranch()
51 return Info->get(Inst.getOpcode()).isCall(); in isCall()
55 return Info->get(Inst.getOpcode()).isReturn(); in isReturn()
59 return Info->get(Inst.getOpcode()).isTerminator(); in isTerminator()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64BranchRelaxation.cpp293 switch (MI->getOpcode()) { in getDestBlock()
346 assert(MI->getOpcode() == AArch64::Bcc && "Unexpected opcode!"); in invertBccCondition()
376 BMI->getOpcode() == AArch64::B) { in fixupConditionalBranch()
386 getBranchDisplacementBits(MI->getOpcode()))) { in fixupConditionalBranch()
390 unsigned OpNum = (MI->getOpcode() == AArch64::TBZW || in fixupConditionalBranch()
391 MI->getOpcode() == AArch64::TBNZW || in fixupConditionalBranch()
392 MI->getOpcode() == AArch64::TBZX || in fixupConditionalBranch()
393 MI->getOpcode() == AArch64::TBNZX) in fixupConditionalBranch()
397 MI->setDesc(TII->get(getOppositeConditionOpcode(MI->getOpcode()))); in fixupConditionalBranch()
398 if (MI->getOpcode() == AArch64::Bcc) in fixupConditionalBranch()
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/NextBSD/contrib/llvm/lib/Target/AArch64/Disassembler/
HDAArch64ExternalSymbolizer.cpp91 } else if (MI.getOpcode() == AArch64::ADRP) { in tryAddingSymbolicOperand()
104 } else if (MI.getOpcode() == AArch64::ADDXri || in tryAddingSymbolicOperand()
105 MI.getOpcode() == AArch64::LDRXui || in tryAddingSymbolicOperand()
106 MI.getOpcode() == AArch64::LDRXl || in tryAddingSymbolicOperand()
107 MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
108 if (MI.getOpcode() == AArch64::ADDXri) in tryAddingSymbolicOperand()
110 else if (MI.getOpcode() == AArch64::LDRXui) in tryAddingSymbolicOperand()
112 if (MI.getOpcode() == AArch64::LDRXl) { in tryAddingSymbolicOperand()
116 } else if (MI.getOpcode() == AArch64::ADR) { in tryAddingSymbolicOperand()
125 MI.getOpcode() == AArch64::ADDXri ? 0x91000000: 0xF9400000; in tryAddingSymbolicOperand()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXInstrInfo.cpp90 switch (MI.getOpcode()) { in isReadSpecialReg()
134 if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS) in CanTailMerge()
181 if (LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
184 } else if (LastInst->getOpcode() == NVPTX::CBranch) { in AnalyzeBranch()
202 if (SecondLastInst->getOpcode() == NVPTX::CBranch && in AnalyzeBranch()
203 LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
212 if (SecondLastInst->getOpcode() == NVPTX::GOTO && in AnalyzeBranch()
213 LastInst->getOpcode() == NVPTX::GOTO) { in AnalyzeBranch()
230 if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch) in RemoveBranch()
241 if (I->getOpcode() != NVPTX::CBranch) in RemoveBranch()
/NextBSD/contrib/llvm/lib/Analysis/
HDCostModel.cpp174 unsigned Opcode = BinOp->getOpcode(); in matchPairwiseReductionAtLevel()
221 else if (NextLevelBinOp->getOpcode() != Opcode) in matchPairwiseReductionAtLevel()
285 Opcode = RdxStart->getOpcode(); in matchPairwiseReduction()
321 unsigned RdxOpcode = RdxStart->getOpcode(); in matchVectorSplittingReduction()
348 if (BinOp->getOpcode() != RdxOpcode) in matchVectorSplittingReduction()
385 switch (I->getOpcode()) { in getInstructionCost()
394 return TTI->getCFInstrCost(I->getOpcode()); in getInstructionCost()
418 return TTI->getArithmeticInstrCost(I->getOpcode(), I->getType(), Op1VK, in getInstructionCost()
424 return TTI->getCmpSelInstrCost(I->getOpcode(), I->getType(), CondTy); in getInstructionCost()
429 return TTI->getCmpSelInstrCost(I->getOpcode(), ValTy); in getInstructionCost()
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/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreInstrInfo.cpp65 int Opcode = MI->getOpcode(); in isLoadFromStackSlot()
87 int Opcode = MI->getOpcode(); in isStoreToStackSlot()
211 if (IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
216 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
237 unsigned SecondLastOpc = SecondLastInst->getOpcode(); in AnalyzeBranch()
243 && IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
255 if (IsBRU(SecondLastInst->getOpcode()) && in AnalyzeBranch()
256 IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
265 if (IsBR_JT(SecondLastInst->getOpcode()) && IsBRU(LastInst->getOpcode())) { in AnalyzeBranch()
314 if (!IsBRU(I->getOpcode()) && !IsCondBranch(I->getOpcode())) in RemoveBranch()
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/NextBSD/contrib/llvm/lib/Transforms/Utils/
HDIntegerDivision.cpp377 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainder()
378 Rem->getOpcode() == Instruction::URem) && in expandRemainder()
393 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainder()
421 assert(UDiv->getOpcode() == Instruction::UDiv && "Non-udiv in expansion?"); in expandRemainder()
437 assert((Div->getOpcode() == Instruction::SDiv || in expandDivision()
438 Div->getOpcode() == Instruction::UDiv) && in expandDivision()
453 if (Div->getOpcode() == Instruction::SDiv) { in expandDivision()
490 assert((Rem->getOpcode() == Instruction::SRem || in expandRemainderUpTo32Bits()
491 Rem->getOpcode() == Instruction::URem) && in expandRemainderUpTo32Bits()
516 if (Rem->getOpcode() == Instruction::SRem) { in expandRemainderUpTo32Bits()
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/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430InstrInfo.cpp115 if (I->getOpcode() != MSP430::JMP && in RemoveBranch()
116 I->getOpcode() != MSP430::JCC && in RemoveBranch()
117 I->getOpcode() != MSP430::Br && in RemoveBranch()
118 I->getOpcode() != MSP430::Bm) in RemoveBranch()
196 if (I->getOpcode() == MSP430::Br || in AnalyzeBranch()
197 I->getOpcode() == MSP430::Bm) in AnalyzeBranch()
201 if (I->getOpcode() == MSP430::JMP) { in AnalyzeBranch()
227 assert(I->getOpcode() == MSP430::JCC && "Invalid conditional branch"); in AnalyzeBranch()
300 switch (Desc.getOpcode()) { in GetInstSizeInBytes()
316 switch (MI->getOpcode()) { in GetInstSizeInBytes()

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