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Searched refs:getCondCode (Results 1 – 9 of 9) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600ISelLowering.cpp1074 DAG.getCondCode(ISD::SETNE) in LowerFPTOUINT()
1143 CC = DAG.getCondCode(InverseCC); in LowerSELECT_CC()
1149 CC = DAG.getCondCode(SwapInvCC); in LowerSELECT_CC()
1177 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1185 CC = DAG.getCondCode(CCSwapped); in LowerSELECT_CC()
1217 DAG.getCondCode(CCOpcode)); in LowerSELECT_CC()
1243 DAG.getCondCode(ISD::SETNE)); in LowerSELECT_CC()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeFloatTypes.cpp771 DAG.getCondCode(CCCode), NewLHS, NewRHS, in SoftenFloatOp_BR_CC()
811 DAG.getCondCode(CCCode)), in SoftenFloatOp_SELECT_CC()
833 DAG.getCondCode(CCCode)), in SoftenFloatOp_SETCC()
1454 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandFloatOp_BR_CC()
1549 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SELECT_CC()
1566 DAG.getCondCode(CCCode)), 0); in ExpandFloatOp_SETCC()
HDLegalizeDAG.cpp1706 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
1757 CC = DAG.getCondCode(InvCC); in LegalizeSetCCCondCode()
3901 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
4015 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
4046 Tmp4 = DAG.getCondCode(ISD::SETNE); in ExpandNode()
HDLegalizeIntegerTypes.cpp2716 LHSHi, RHSHi, DAG.getCondCode(CCCode)); in IntegerExpandSetCCOperands()
2760 DAG.getCondCode(CCCode), NewLHS, NewRHS, in ExpandIntOp_BR_CC()
2779 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SELECT_CC()
2796 DAG.getCondCode(CCCode)), 0); in ExpandIntOp_SETCC()
HDTargetLowering.cpp213 NewLHS, NewRHS, DAG.getCondCode(CCCode)); in softenSetCCOperands()
219 NewLHS, NewRHS, DAG.getCondCode(getCmpLibcallCC(LC2))); in softenSetCCOperands()
HDSelectionDAG.cpp1495 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode() function in SelectionDAG
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDSelectionDAG.h564 SDValue getCondCode(ISD::CondCode Cond);
734 return getNode(ISD::SETCC, DL, VT, LHS, RHS, getCondCode(Cond));
755 LHS, RHS, True, False, getCondCode(Cond));
/NextBSD/contrib/llvm/lib/Target/AArch64/AsmParser/
HDAArch64AsmParser.cpp341 AArch64CC::CondCode getCondCode() const { in getCondCode() function in __anon61806b610211::AArch64Operand
1255 Inst.addOperand(MCOperand::createImm(getCondCode())); in addCondCodeOperands()
1746 OS << "<condcode " << getCondCode() << ">"; in print()
/NextBSD/contrib/llvm/lib/Target/ARM/AsmParser/
HDARMAsmParser.cpp663 ARMCC::CondCodes getCondCode() const { in getCondCode() function in __anonde494dcf0311::ARMOperand
1765 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addCondCodeOperands()
1766 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands()
1792 Inst.addOperand(MCOperand::createImm(unsigned(getCondCode()))); in addITCondCodeOperands()
2847 OS << "<ARMCC::" << ARMCondCodeToString(getCondCode()) << ">"; in print()
4738 unsigned Cond = static_cast<ARMOperand &>(*Operands[CondOp]).getCondCode(); in cvtThumbBranches()