1 /*-
2 * Copyright (c) 2013-2015 The FreeBSD Foundation
3 * All rights reserved.
4 *
5 * This software was developed by Konstantin Belousov <kib@FreeBSD.org>
6 * under sponsorship from the FreeBSD Foundation.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
32
33 #include "opt_acpi.h"
34 #if defined(__amd64__)
35 #define DEV_APIC
36 #else
37 #include "opt_apic.h"
38 #endif
39 #include "opt_ddb.h"
40
41 #include <sys/param.h>
42 #include <sys/bus.h>
43 #include <sys/kernel.h>
44 #include <sys/lock.h>
45 #include <sys/malloc.h>
46 #include <sys/memdesc.h>
47 #include <sys/module.h>
48 #include <sys/rman.h>
49 #include <sys/rwlock.h>
50 #include <sys/smp.h>
51 #include <sys/taskqueue.h>
52 #include <sys/tree.h>
53 #include <sys/vmem.h>
54 #include <machine/bus.h>
55 #include <contrib/dev/acpica/include/acpi.h>
56 #include <contrib/dev/acpica/include/accommon.h>
57 #include <dev/acpica/acpivar.h>
58 #include <vm/vm.h>
59 #include <vm/vm_extern.h>
60 #include <vm/vm_kern.h>
61 #include <vm/vm_object.h>
62 #include <vm/vm_page.h>
63 #include <vm/vm_pager.h>
64 #include <vm/vm_map.h>
65 #include <x86/include/busdma_impl.h>
66 #include <x86/iommu/intel_reg.h>
67 #include <x86/iommu/busdma_dmar.h>
68 #include <x86/iommu/intel_dmar.h>
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
71
72 #ifdef DEV_APIC
73 #include "pcib_if.h"
74 #endif
75
76 #define DMAR_FAULT_IRQ_RID 0
77 #define DMAR_QI_IRQ_RID 1
78 #define DMAR_REG_RID 2
79
80 static devclass_t dmar_devclass;
81 static device_t *dmar_devs;
82 static int dmar_devcnt;
83
84 typedef int (*dmar_iter_t)(ACPI_DMAR_HEADER *, void *);
85
86 static void
dmar_iterate_tbl(dmar_iter_t iter,void * arg)87 dmar_iterate_tbl(dmar_iter_t iter, void *arg)
88 {
89 ACPI_TABLE_DMAR *dmartbl;
90 ACPI_DMAR_HEADER *dmarh;
91 char *ptr, *ptrend;
92 ACPI_STATUS status;
93
94 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
95 if (ACPI_FAILURE(status))
96 return;
97 ptr = (char *)dmartbl + sizeof(*dmartbl);
98 ptrend = (char *)dmartbl + dmartbl->Header.Length;
99 for (;;) {
100 if (ptr >= ptrend)
101 break;
102 dmarh = (ACPI_DMAR_HEADER *)ptr;
103 if (dmarh->Length <= 0) {
104 printf("dmar_identify: corrupted DMAR table, l %d\n",
105 dmarh->Length);
106 break;
107 }
108 ptr += dmarh->Length;
109 if (!iter(dmarh, arg))
110 break;
111 }
112 }
113
114 struct find_iter_args {
115 int i;
116 ACPI_DMAR_HARDWARE_UNIT *res;
117 };
118
119 static int
dmar_find_iter(ACPI_DMAR_HEADER * dmarh,void * arg)120 dmar_find_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
121 {
122 struct find_iter_args *fia;
123
124 if (dmarh->Type != ACPI_DMAR_TYPE_HARDWARE_UNIT)
125 return (1);
126
127 fia = arg;
128 if (fia->i == 0) {
129 fia->res = (ACPI_DMAR_HARDWARE_UNIT *)dmarh;
130 return (0);
131 }
132 fia->i--;
133 return (1);
134 }
135
136 static ACPI_DMAR_HARDWARE_UNIT *
dmar_find_by_index(int idx)137 dmar_find_by_index(int idx)
138 {
139 struct find_iter_args fia;
140
141 fia.i = idx;
142 fia.res = NULL;
143 dmar_iterate_tbl(dmar_find_iter, &fia);
144 return (fia.res);
145 }
146
147 static int
dmar_count_iter(ACPI_DMAR_HEADER * dmarh,void * arg)148 dmar_count_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
149 {
150
151 if (dmarh->Type == ACPI_DMAR_TYPE_HARDWARE_UNIT)
152 dmar_devcnt++;
153 return (1);
154 }
155
156 static int dmar_enable = 0;
157 static void
dmar_identify(driver_t * driver,device_t parent)158 dmar_identify(driver_t *driver, device_t parent)
159 {
160 ACPI_TABLE_DMAR *dmartbl;
161 ACPI_DMAR_HARDWARE_UNIT *dmarh;
162 ACPI_STATUS status;
163 int i, error;
164
165 if (acpi_disabled("dmar"))
166 return;
167 TUNABLE_INT_FETCH("hw.dmar.enable", &dmar_enable);
168 if (!dmar_enable)
169 return;
170 #ifdef INVARIANTS
171 TUNABLE_INT_FETCH("hw.dmar.check_free", &dmar_check_free);
172 #endif
173 TUNABLE_INT_FETCH("hw.dmar.match_verbose", &dmar_match_verbose);
174 status = AcpiGetTable(ACPI_SIG_DMAR, 1, (ACPI_TABLE_HEADER **)&dmartbl);
175 if (ACPI_FAILURE(status))
176 return;
177 haw = dmartbl->Width + 1;
178 if ((1ULL << (haw + 1)) > BUS_SPACE_MAXADDR)
179 dmar_high = BUS_SPACE_MAXADDR;
180 else
181 dmar_high = 1ULL << (haw + 1);
182 if (bootverbose) {
183 printf("DMAR HAW=%d flags=<%b>\n", dmartbl->Width,
184 (unsigned)dmartbl->Flags,
185 "\020\001INTR_REMAP\002X2APIC_OPT_OUT");
186 }
187
188 dmar_iterate_tbl(dmar_count_iter, NULL);
189 if (dmar_devcnt == 0)
190 return;
191 dmar_devs = malloc(sizeof(device_t) * dmar_devcnt, M_DEVBUF,
192 M_WAITOK | M_ZERO);
193 for (i = 0; i < dmar_devcnt; i++) {
194 dmarh = dmar_find_by_index(i);
195 if (dmarh == NULL) {
196 printf("dmar_identify: cannot find HWUNIT %d\n", i);
197 continue;
198 }
199 dmar_devs[i] = BUS_ADD_CHILD(parent, 1, "dmar", i);
200 if (dmar_devs[i] == NULL) {
201 printf("dmar_identify: cannot create instance %d\n", i);
202 continue;
203 }
204 error = bus_set_resource(dmar_devs[i], SYS_RES_MEMORY,
205 DMAR_REG_RID, dmarh->Address, PAGE_SIZE);
206 if (error != 0) {
207 printf(
208 "dmar%d: unable to alloc register window at 0x%08jx: error %d\n",
209 i, (uintmax_t)dmarh->Address, error);
210 device_delete_child(parent, dmar_devs[i]);
211 dmar_devs[i] = NULL;
212 }
213 }
214 }
215
216 static int
dmar_probe(device_t dev)217 dmar_probe(device_t dev)
218 {
219
220 if (acpi_get_handle(dev) != NULL)
221 return (ENXIO);
222 device_set_desc(dev, "DMA remap");
223 return (BUS_PROBE_NOWILDCARD);
224 }
225
226 static void
dmar_release_intr(device_t dev,struct dmar_unit * unit,int idx)227 dmar_release_intr(device_t dev, struct dmar_unit *unit, int idx)
228 {
229 struct dmar_msi_data *dmd;
230
231 dmd = &unit->intrs[idx];
232 if (dmd->irq == -1)
233 return;
234 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
235 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
236 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
237 PCIB_RELEASE_MSIX(device_get_parent(device_get_parent(dev)),
238 dev, dmd->irq);
239 dmd->irq = -1;
240 }
241
242 static void
dmar_release_resources(device_t dev,struct dmar_unit * unit)243 dmar_release_resources(device_t dev, struct dmar_unit *unit)
244 {
245 int i;
246
247 dmar_fini_busdma(unit);
248 dmar_fini_irt(unit);
249 dmar_fini_qi(unit);
250 dmar_fini_fault_log(unit);
251 for (i = 0; i < DMAR_INTR_TOTAL; i++)
252 dmar_release_intr(dev, unit, i);
253 if (unit->regs != NULL) {
254 bus_deactivate_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
255 unit->regs);
256 bus_release_resource(dev, SYS_RES_MEMORY, unit->reg_rid,
257 unit->regs);
258 unit->regs = NULL;
259 }
260 if (unit->domids != NULL) {
261 delete_unrhdr(unit->domids);
262 unit->domids = NULL;
263 }
264 if (unit->ctx_obj != NULL) {
265 vm_object_deallocate(unit->ctx_obj);
266 unit->ctx_obj = NULL;
267 }
268 }
269
270 static int
dmar_alloc_irq(device_t dev,struct dmar_unit * unit,int idx)271 dmar_alloc_irq(device_t dev, struct dmar_unit *unit, int idx)
272 {
273 device_t pcib;
274 struct dmar_msi_data *dmd;
275 uint64_t msi_addr;
276 uint32_t msi_data;
277 int error;
278
279 dmd = &unit->intrs[idx];
280 pcib = device_get_parent(device_get_parent(dev)); /* Really not pcib */
281 error = PCIB_ALLOC_MSIX(pcib, dev, &dmd->irq);
282 if (error != 0) {
283 device_printf(dev, "cannot allocate %s interrupt, %d\n",
284 dmd->name, error);
285 goto err1;
286 }
287 error = bus_set_resource(dev, SYS_RES_IRQ, dmd->irq_rid,
288 dmd->irq, 1);
289 if (error != 0) {
290 device_printf(dev, "cannot set %s interrupt resource, %d\n",
291 dmd->name, error);
292 goto err2;
293 }
294 dmd->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ,
295 &dmd->irq_rid, RF_ACTIVE);
296 if (dmd->irq_res == NULL) {
297 device_printf(dev,
298 "cannot allocate resource for %s interrupt\n", dmd->name);
299 error = ENXIO;
300 goto err3;
301 }
302 error = bus_setup_intr(dev, dmd->irq_res, INTR_TYPE_MISC,
303 dmd->handler, NULL, unit, &dmd->intr_handle);
304 if (error != 0) {
305 device_printf(dev, "cannot setup %s interrupt, %d\n",
306 dmd->name, error);
307 goto err4;
308 }
309 bus_describe_intr(dev, dmd->irq_res, dmd->intr_handle, dmd->name);
310 error = PCIB_MAP_MSI(pcib, dev, dmd->irq, &msi_addr, &msi_data);
311 if (error != 0) {
312 device_printf(dev, "cannot map %s interrupt, %d\n",
313 dmd->name, error);
314 goto err5;
315 }
316 dmar_write4(unit, dmd->msi_data_reg, msi_data);
317 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
318 /* Only for xAPIC mode */
319 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
320 return (0);
321
322 err5:
323 bus_teardown_intr(dev, dmd->irq_res, dmd->intr_handle);
324 err4:
325 bus_release_resource(dev, SYS_RES_IRQ, dmd->irq_rid, dmd->irq_res);
326 err3:
327 bus_delete_resource(dev, SYS_RES_IRQ, dmd->irq_rid);
328 err2:
329 PCIB_RELEASE_MSIX(pcib, dev, dmd->irq);
330 dmd->irq = -1;
331 err1:
332 return (error);
333 }
334
335 #ifdef DEV_APIC
336 static int
dmar_remap_intr(device_t dev,device_t child,u_int irq)337 dmar_remap_intr(device_t dev, device_t child, u_int irq)
338 {
339 struct dmar_unit *unit;
340 struct dmar_msi_data *dmd;
341 uint64_t msi_addr;
342 uint32_t msi_data;
343 int i, error;
344
345 unit = device_get_softc(dev);
346 for (i = 0; i < DMAR_INTR_TOTAL; i++) {
347 dmd = &unit->intrs[i];
348 if (irq == dmd->irq) {
349 error = PCIB_MAP_MSI(device_get_parent(
350 device_get_parent(dev)),
351 dev, irq, &msi_addr, &msi_data);
352 if (error != 0)
353 return (error);
354 DMAR_LOCK(unit);
355 (dmd->disable_intr)(unit);
356 dmar_write4(unit, dmd->msi_data_reg, msi_data);
357 dmar_write4(unit, dmd->msi_addr_reg, msi_addr);
358 dmar_write4(unit, dmd->msi_uaddr_reg, msi_addr >> 32);
359 (dmd->enable_intr)(unit);
360 DMAR_UNLOCK(unit);
361 return (0);
362 }
363 }
364 return (ENOENT);
365 }
366 #endif
367
368 static void
dmar_print_caps(device_t dev,struct dmar_unit * unit,ACPI_DMAR_HARDWARE_UNIT * dmaru)369 dmar_print_caps(device_t dev, struct dmar_unit *unit,
370 ACPI_DMAR_HARDWARE_UNIT *dmaru)
371 {
372 uint32_t caphi, ecaphi;
373
374 device_printf(dev, "regs@0x%08jx, ver=%d.%d, seg=%d, flags=<%b>\n",
375 (uintmax_t)dmaru->Address, DMAR_MAJOR_VER(unit->hw_ver),
376 DMAR_MINOR_VER(unit->hw_ver), dmaru->Segment,
377 dmaru->Flags, "\020\001INCLUDE_ALL_PCI");
378 caphi = unit->hw_cap >> 32;
379 device_printf(dev, "cap=%b,", (u_int)unit->hw_cap,
380 "\020\004AFL\005WBF\006PLMR\007PHMR\010CM\027ZLR\030ISOCH");
381 printf("%b, ", caphi, "\020\010PSI\027DWD\030DRD\031FL1GP\034PSI");
382 printf("ndoms=%d, sagaw=%d, mgaw=%d, fro=%d, nfr=%d, superp=%d",
383 DMAR_CAP_ND(unit->hw_cap), DMAR_CAP_SAGAW(unit->hw_cap),
384 DMAR_CAP_MGAW(unit->hw_cap), DMAR_CAP_FRO(unit->hw_cap),
385 DMAR_CAP_NFR(unit->hw_cap), DMAR_CAP_SPS(unit->hw_cap));
386 if ((unit->hw_cap & DMAR_CAP_PSI) != 0)
387 printf(", mamv=%d", DMAR_CAP_MAMV(unit->hw_cap));
388 printf("\n");
389 ecaphi = unit->hw_ecap >> 32;
390 device_printf(dev, "ecap=%b,", (u_int)unit->hw_ecap,
391 "\020\001C\002QI\003DI\004IR\005EIM\007PT\010SC\031ECS\032MTS"
392 "\033NEST\034DIS\035PASID\036PRS\037ERS\040SRS");
393 printf("%b, ", ecaphi, "\020\002NWFS\003EAFS");
394 printf("mhmw=%d, iro=%d\n", DMAR_ECAP_MHMV(unit->hw_ecap),
395 DMAR_ECAP_IRO(unit->hw_ecap));
396 }
397
398 static int
dmar_attach(device_t dev)399 dmar_attach(device_t dev)
400 {
401 struct dmar_unit *unit;
402 ACPI_DMAR_HARDWARE_UNIT *dmaru;
403 int i, error;
404
405 unit = device_get_softc(dev);
406 unit->dev = dev;
407 unit->unit = device_get_unit(dev);
408 dmaru = dmar_find_by_index(unit->unit);
409 if (dmaru == NULL)
410 return (EINVAL);
411 unit->segment = dmaru->Segment;
412 unit->base = dmaru->Address;
413 unit->reg_rid = DMAR_REG_RID;
414 unit->regs = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
415 &unit->reg_rid, RF_ACTIVE);
416 if (unit->regs == NULL) {
417 device_printf(dev, "cannot allocate register window\n");
418 return (ENOMEM);
419 }
420 unit->hw_ver = dmar_read4(unit, DMAR_VER_REG);
421 unit->hw_cap = dmar_read8(unit, DMAR_CAP_REG);
422 unit->hw_ecap = dmar_read8(unit, DMAR_ECAP_REG);
423 if (bootverbose)
424 dmar_print_caps(dev, unit, dmaru);
425 dmar_quirks_post_ident(unit);
426
427 for (i = 0; i < DMAR_INTR_TOTAL; i++)
428 unit->intrs[i].irq = -1;
429
430 unit->intrs[DMAR_INTR_FAULT].name = "fault";
431 unit->intrs[DMAR_INTR_FAULT].irq_rid = DMAR_FAULT_IRQ_RID;
432 unit->intrs[DMAR_INTR_FAULT].handler = dmar_fault_intr;
433 unit->intrs[DMAR_INTR_FAULT].msi_data_reg = DMAR_FEDATA_REG;
434 unit->intrs[DMAR_INTR_FAULT].msi_addr_reg = DMAR_FEADDR_REG;
435 unit->intrs[DMAR_INTR_FAULT].msi_uaddr_reg = DMAR_FEUADDR_REG;
436 unit->intrs[DMAR_INTR_FAULT].enable_intr = dmar_enable_fault_intr;
437 unit->intrs[DMAR_INTR_FAULT].disable_intr = dmar_disable_fault_intr;
438 error = dmar_alloc_irq(dev, unit, DMAR_INTR_FAULT);
439 if (error != 0) {
440 dmar_release_resources(dev, unit);
441 return (error);
442 }
443 if (DMAR_HAS_QI(unit)) {
444 unit->intrs[DMAR_INTR_QI].name = "qi";
445 unit->intrs[DMAR_INTR_QI].irq_rid = DMAR_QI_IRQ_RID;
446 unit->intrs[DMAR_INTR_QI].handler = dmar_qi_intr;
447 unit->intrs[DMAR_INTR_QI].msi_data_reg = DMAR_IEDATA_REG;
448 unit->intrs[DMAR_INTR_QI].msi_addr_reg = DMAR_IEADDR_REG;
449 unit->intrs[DMAR_INTR_QI].msi_uaddr_reg = DMAR_IEUADDR_REG;
450 unit->intrs[DMAR_INTR_QI].enable_intr = dmar_enable_qi_intr;
451 unit->intrs[DMAR_INTR_QI].disable_intr = dmar_disable_qi_intr;
452 error = dmar_alloc_irq(dev, unit, DMAR_INTR_QI);
453 if (error != 0) {
454 dmar_release_resources(dev, unit);
455 return (error);
456 }
457 }
458
459 mtx_init(&unit->lock, "dmarhw", NULL, MTX_DEF);
460 unit->domids = new_unrhdr(0, dmar_nd2mask(DMAR_CAP_ND(unit->hw_cap)),
461 &unit->lock);
462 LIST_INIT(&unit->domains);
463
464 /*
465 * 9.2 "Context Entry":
466 * When Caching Mode (CM) field is reported as Set, the
467 * domain-id value of zero is architecturally reserved.
468 * Software must not use domain-id value of zero
469 * when CM is Set.
470 */
471 if ((unit->hw_cap & DMAR_CAP_CM) != 0)
472 alloc_unr_specific(unit->domids, 0);
473
474 unit->ctx_obj = vm_pager_allocate(OBJT_PHYS, NULL, IDX_TO_OFF(1 +
475 DMAR_CTX_CNT), 0, 0, NULL);
476
477 /*
478 * Allocate and load the root entry table pointer. Enable the
479 * address translation after the required invalidations are
480 * done.
481 */
482 dmar_pgalloc(unit->ctx_obj, 0, DMAR_PGF_WAITOK | DMAR_PGF_ZERO);
483 DMAR_LOCK(unit);
484 error = dmar_load_root_entry_ptr(unit);
485 if (error != 0) {
486 DMAR_UNLOCK(unit);
487 dmar_release_resources(dev, unit);
488 return (error);
489 }
490 error = dmar_inv_ctx_glob(unit);
491 if (error != 0) {
492 DMAR_UNLOCK(unit);
493 dmar_release_resources(dev, unit);
494 return (error);
495 }
496 if ((unit->hw_ecap & DMAR_ECAP_DI) != 0) {
497 error = dmar_inv_iotlb_glob(unit);
498 if (error != 0) {
499 DMAR_UNLOCK(unit);
500 dmar_release_resources(dev, unit);
501 return (error);
502 }
503 }
504
505 DMAR_UNLOCK(unit);
506 error = dmar_init_fault_log(unit);
507 if (error != 0) {
508 dmar_release_resources(dev, unit);
509 return (error);
510 }
511 error = dmar_init_qi(unit);
512 if (error != 0) {
513 dmar_release_resources(dev, unit);
514 return (error);
515 }
516 error = dmar_init_irt(unit);
517 if (error != 0) {
518 dmar_release_resources(dev, unit);
519 return (error);
520 }
521 error = dmar_init_busdma(unit);
522 if (error != 0) {
523 dmar_release_resources(dev, unit);
524 return (error);
525 }
526
527 #ifdef NOTYET
528 DMAR_LOCK(unit);
529 error = dmar_enable_translation(unit);
530 if (error != 0) {
531 DMAR_UNLOCK(unit);
532 dmar_release_resources(dev, unit);
533 return (error);
534 }
535 DMAR_UNLOCK(unit);
536 #endif
537
538 return (0);
539 }
540
541 static int
dmar_detach(device_t dev)542 dmar_detach(device_t dev)
543 {
544
545 return (EBUSY);
546 }
547
548 static int
dmar_suspend(device_t dev)549 dmar_suspend(device_t dev)
550 {
551
552 return (0);
553 }
554
555 static int
dmar_resume(device_t dev)556 dmar_resume(device_t dev)
557 {
558
559 /* XXXKIB */
560 return (0);
561 }
562
563 static device_method_t dmar_methods[] = {
564 DEVMETHOD(device_identify, dmar_identify),
565 DEVMETHOD(device_probe, dmar_probe),
566 DEVMETHOD(device_attach, dmar_attach),
567 DEVMETHOD(device_detach, dmar_detach),
568 DEVMETHOD(device_suspend, dmar_suspend),
569 DEVMETHOD(device_resume, dmar_resume),
570 #ifdef DEV_APIC
571 DEVMETHOD(bus_remap_intr, dmar_remap_intr),
572 #endif
573 DEVMETHOD_END
574 };
575
576 static driver_t dmar_driver = {
577 "dmar",
578 dmar_methods,
579 sizeof(struct dmar_unit),
580 };
581
582 DRIVER_MODULE(dmar, acpi, dmar_driver, dmar_devclass, 0, 0);
583 MODULE_DEPEND(dmar, acpi, 1, 1, 1);
584
585 static void
dmar_print_path(device_t dev,const char * banner,int busno,int depth,const ACPI_DMAR_PCI_PATH * path)586 dmar_print_path(device_t dev, const char *banner, int busno, int depth,
587 const ACPI_DMAR_PCI_PATH *path)
588 {
589 int i;
590
591 device_printf(dev, "%s [%d, ", banner, busno);
592 for (i = 0; i < depth; i++) {
593 if (i != 0)
594 printf(", ");
595 printf("(%d, %d)", path[i].Device, path[i].Function);
596 }
597 printf("]\n");
598 }
599
600 static int
dmar_dev_depth(device_t child)601 dmar_dev_depth(device_t child)
602 {
603 devclass_t pci_class;
604 device_t bus, pcib;
605 int depth;
606
607 pci_class = devclass_find("pci");
608 for (depth = 1; ; depth++) {
609 bus = device_get_parent(child);
610 pcib = device_get_parent(bus);
611 if (device_get_devclass(device_get_parent(pcib)) !=
612 pci_class)
613 return (depth);
614 child = pcib;
615 }
616 }
617
618 static void
dmar_dev_path(device_t child,int * busno,ACPI_DMAR_PCI_PATH * path,int depth)619 dmar_dev_path(device_t child, int *busno, ACPI_DMAR_PCI_PATH *path, int depth)
620 {
621 devclass_t pci_class;
622 device_t bus, pcib;
623
624 pci_class = devclass_find("pci");
625 for (depth--; depth != -1; depth--) {
626 path[depth].Device = pci_get_slot(child);
627 path[depth].Function = pci_get_function(child);
628 bus = device_get_parent(child);
629 pcib = device_get_parent(bus);
630 if (device_get_devclass(device_get_parent(pcib)) !=
631 pci_class) {
632 /* reached a host bridge */
633 *busno = pcib_get_bus(bus);
634 return;
635 }
636 child = pcib;
637 }
638 panic("wrong depth");
639 }
640
641 static int
dmar_match_pathes(int busno1,const ACPI_DMAR_PCI_PATH * path1,int depth1,int busno2,const ACPI_DMAR_PCI_PATH * path2,int depth2,enum AcpiDmarScopeType scope_type)642 dmar_match_pathes(int busno1, const ACPI_DMAR_PCI_PATH *path1, int depth1,
643 int busno2, const ACPI_DMAR_PCI_PATH *path2, int depth2,
644 enum AcpiDmarScopeType scope_type)
645 {
646 int i, depth;
647
648 if (busno1 != busno2)
649 return (0);
650 if (scope_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && depth1 != depth2)
651 return (0);
652 depth = depth1;
653 if (depth2 < depth)
654 depth = depth2;
655 for (i = 0; i < depth; i++) {
656 if (path1[i].Device != path2[i].Device ||
657 path1[i].Function != path2[i].Function)
658 return (0);
659 }
660 return (1);
661 }
662
663 static int
dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE * devscope,device_t dev,int dev_busno,const ACPI_DMAR_PCI_PATH * dev_path,int dev_path_len)664 dmar_match_devscope(ACPI_DMAR_DEVICE_SCOPE *devscope, device_t dev,
665 int dev_busno, const ACPI_DMAR_PCI_PATH *dev_path, int dev_path_len)
666 {
667 ACPI_DMAR_PCI_PATH *path;
668 int path_len;
669
670 if (devscope->Length < sizeof(*devscope)) {
671 printf("dmar_find: corrupted DMAR table, dl %d\n",
672 devscope->Length);
673 return (-1);
674 }
675 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT &&
676 devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_BRIDGE)
677 return (0);
678 path_len = devscope->Length - sizeof(*devscope);
679 if (path_len % 2 != 0) {
680 printf("dmar_find_bsf: corrupted DMAR table, dl %d\n",
681 devscope->Length);
682 return (-1);
683 }
684 path_len /= 2;
685 path = (ACPI_DMAR_PCI_PATH *)(devscope + 1);
686 if (path_len == 0) {
687 printf("dmar_find: corrupted DMAR table, dl %d\n",
688 devscope->Length);
689 return (-1);
690 }
691 if (dmar_match_verbose)
692 dmar_print_path(dev, "DMAR", devscope->Bus, path_len, path);
693
694 return (dmar_match_pathes(devscope->Bus, path, path_len, dev_busno,
695 dev_path, dev_path_len, devscope->EntryType));
696 }
697
698 struct dmar_unit *
dmar_find(device_t dev)699 dmar_find(device_t dev)
700 {
701 device_t dmar_dev;
702 ACPI_DMAR_HARDWARE_UNIT *dmarh;
703 ACPI_DMAR_DEVICE_SCOPE *devscope;
704 char *ptr, *ptrend;
705 int i, match, dev_domain, dev_busno, dev_path_len;
706
707 dmar_dev = NULL;
708 dev_domain = pci_get_domain(dev);
709 dev_path_len = dmar_dev_depth(dev);
710 ACPI_DMAR_PCI_PATH dev_path[dev_path_len];
711 dmar_dev_path(dev, &dev_busno, dev_path, dev_path_len);
712 if (dmar_match_verbose)
713 dmar_print_path(dev, "PCI", dev_busno, dev_path_len, dev_path);
714
715 for (i = 0; i < dmar_devcnt; i++) {
716 if (dmar_devs[i] == NULL)
717 continue;
718 dmarh = dmar_find_by_index(i);
719 if (dmarh == NULL)
720 continue;
721 if (dmarh->Segment != dev_domain)
722 continue;
723 if ((dmarh->Flags & ACPI_DMAR_INCLUDE_ALL) != 0) {
724 dmar_dev = dmar_devs[i];
725 if (dmar_match_verbose) {
726 device_printf(dev,
727 "pci%d:%d:%d:%d matched dmar%d INCLUDE_ALL\n",
728 dev_domain, pci_get_bus(dev),
729 pci_get_slot(dev),
730 pci_get_function(dev),
731 ((struct dmar_unit *)device_get_softc(
732 dmar_dev))->unit);
733 }
734 goto found;
735 }
736 ptr = (char *)dmarh + sizeof(*dmarh);
737 ptrend = (char *)dmarh + dmarh->Header.Length;
738 for (;;) {
739 if (ptr >= ptrend)
740 break;
741 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
742 ptr += devscope->Length;
743 if (dmar_match_verbose) {
744 device_printf(dev,
745 "pci%d:%d:%d:%d matching dmar%d\n",
746 dev_domain, pci_get_bus(dev),
747 pci_get_slot(dev),
748 pci_get_function(dev),
749 ((struct dmar_unit *)device_get_softc(
750 dmar_devs[i]))->unit);
751 }
752 match = dmar_match_devscope(devscope, dev, dev_busno,
753 dev_path, dev_path_len);
754 if (dmar_match_verbose) {
755 if (match == -1)
756 printf("table error\n");
757 else if (match == 0)
758 printf("not matched\n");
759 else
760 printf("matched\n");
761 }
762 if (match == -1)
763 return (NULL);
764 else if (match == 1) {
765 dmar_dev = dmar_devs[i];
766 goto found;
767 }
768 }
769 }
770 return (NULL);
771 found:
772 return (device_get_softc(dmar_dev));
773 }
774
775 static struct dmar_unit *
dmar_find_nonpci(u_int id,u_int entry_type,uint16_t * rid)776 dmar_find_nonpci(u_int id, u_int entry_type, uint16_t *rid)
777 {
778 device_t dmar_dev;
779 struct dmar_unit *unit;
780 ACPI_DMAR_HARDWARE_UNIT *dmarh;
781 ACPI_DMAR_DEVICE_SCOPE *devscope;
782 ACPI_DMAR_PCI_PATH *path;
783 char *ptr, *ptrend;
784 int i;
785
786 for (i = 0; i < dmar_devcnt; i++) {
787 dmar_dev = dmar_devs[i];
788 if (dmar_dev == NULL)
789 continue;
790 unit = (struct dmar_unit *)device_get_softc(dmar_dev);
791 dmarh = dmar_find_by_index(i);
792 if (dmarh == NULL)
793 continue;
794 ptr = (char *)dmarh + sizeof(*dmarh);
795 ptrend = (char *)dmarh + dmarh->Header.Length;
796 for (;;) {
797 if (ptr >= ptrend)
798 break;
799 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
800 ptr += devscope->Length;
801 if (devscope->EntryType != entry_type)
802 continue;
803 if (devscope->EnumerationId != id)
804 continue;
805 if (devscope->Length - sizeof(ACPI_DMAR_DEVICE_SCOPE)
806 == 2) {
807 if (rid != NULL) {
808 path = (ACPI_DMAR_PCI_PATH *)
809 (devscope + 1);
810 *rid = PCI_RID(devscope->Bus,
811 path->Device, path->Function);
812 }
813 return (unit);
814 } else {
815 /* XXXKIB */
816 printf(
817 "dmar_find_nonpci: id %d type %d path length != 2\n",
818 id, entry_type);
819 }
820 }
821 }
822 return (NULL);
823 }
824
825
826 struct dmar_unit *
dmar_find_hpet(device_t dev,uint16_t * rid)827 dmar_find_hpet(device_t dev, uint16_t *rid)
828 {
829 ACPI_HANDLE handle;
830 uint32_t hpet_id;
831
832 handle = acpi_get_handle(dev);
833 if (ACPI_FAILURE(acpi_GetInteger(handle, "_UID", &hpet_id)))
834 return (NULL);
835 return (dmar_find_nonpci(hpet_id, ACPI_DMAR_SCOPE_TYPE_HPET, rid));
836 }
837
838 struct dmar_unit *
dmar_find_ioapic(u_int apic_id,uint16_t * rid)839 dmar_find_ioapic(u_int apic_id, uint16_t *rid)
840 {
841
842 return (dmar_find_nonpci(apic_id, ACPI_DMAR_SCOPE_TYPE_IOAPIC, rid));
843 }
844
845 struct rmrr_iter_args {
846 struct dmar_domain *domain;
847 device_t dev;
848 int dev_domain;
849 int dev_busno;
850 ACPI_DMAR_PCI_PATH *dev_path;
851 int dev_path_len;
852 struct dmar_map_entries_tailq *rmrr_entries;
853 };
854
855 static int
dmar_rmrr_iter(ACPI_DMAR_HEADER * dmarh,void * arg)856 dmar_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
857 {
858 struct rmrr_iter_args *ria;
859 ACPI_DMAR_RESERVED_MEMORY *resmem;
860 ACPI_DMAR_DEVICE_SCOPE *devscope;
861 struct dmar_map_entry *entry;
862 char *ptr, *ptrend;
863 int match;
864
865 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
866 return (1);
867
868 ria = arg;
869 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
870 if (dmar_match_verbose) {
871 printf("RMRR [%jx,%jx] segment %d\n",
872 (uintmax_t)resmem->BaseAddress,
873 (uintmax_t)resmem->EndAddress,
874 resmem->Segment);
875 }
876 if (resmem->Segment != ria->dev_domain)
877 return (1);
878
879 ptr = (char *)resmem + sizeof(*resmem);
880 ptrend = (char *)resmem + resmem->Header.Length;
881 for (;;) {
882 if (ptr >= ptrend)
883 break;
884 devscope = (ACPI_DMAR_DEVICE_SCOPE *)ptr;
885 ptr += devscope->Length;
886 match = dmar_match_devscope(devscope, ria->dev, ria->dev_busno,
887 ria->dev_path, ria->dev_path_len);
888 if (match == 1) {
889 if (dmar_match_verbose)
890 printf("matched\n");
891 entry = dmar_gas_alloc_entry(ria->domain,
892 DMAR_PGF_WAITOK);
893 entry->start = resmem->BaseAddress;
894 /* The RMRR entry end address is inclusive. */
895 entry->end = resmem->EndAddress;
896 TAILQ_INSERT_TAIL(ria->rmrr_entries, entry,
897 unroll_link);
898 } else if (dmar_match_verbose) {
899 printf("not matched, err %d\n", match);
900 }
901 }
902
903 return (1);
904 }
905
906 void
dmar_dev_parse_rmrr(struct dmar_domain * domain,device_t dev,struct dmar_map_entries_tailq * rmrr_entries)907 dmar_dev_parse_rmrr(struct dmar_domain *domain, device_t dev,
908 struct dmar_map_entries_tailq *rmrr_entries)
909 {
910 struct rmrr_iter_args ria;
911
912 ria.dev_domain = pci_get_domain(dev);
913 ria.dev_path_len = dmar_dev_depth(dev);
914 ACPI_DMAR_PCI_PATH dev_path[ria.dev_path_len];
915 dmar_dev_path(dev, &ria.dev_busno, dev_path, ria.dev_path_len);
916
917 if (dmar_match_verbose) {
918 device_printf(dev, "parsing RMRR entries for ");
919 dmar_print_path(dev, "PCI", ria.dev_busno, ria.dev_path_len,
920 dev_path);
921 }
922
923 ria.domain = domain;
924 ria.dev = dev;
925 ria.dev_path = dev_path;
926 ria.rmrr_entries = rmrr_entries;
927 dmar_iterate_tbl(dmar_rmrr_iter, &ria);
928 }
929
930 struct inst_rmrr_iter_args {
931 struct dmar_unit *dmar;
932 };
933
934 static device_t
dmar_path_dev(int segment,int path_len,int busno,const ACPI_DMAR_PCI_PATH * path)935 dmar_path_dev(int segment, int path_len, int busno,
936 const ACPI_DMAR_PCI_PATH *path)
937 {
938 devclass_t pci_class;
939 device_t bus, pcib, dev;
940 int i;
941
942 pci_class = devclass_find("pci");
943 dev = NULL;
944 for (i = 0; i < path_len; i++, path++) {
945 dev = pci_find_dbsf(segment, busno, path->Device,
946 path->Function);
947 if (dev == NULL)
948 break;
949 if (i != path_len - 1) {
950 bus = device_get_parent(dev);
951 pcib = device_get_parent(bus);
952 if (device_get_devclass(device_get_parent(pcib)) !=
953 pci_class)
954 return (NULL);
955 }
956 busno = pcib_get_bus(dev);
957 }
958 return (dev);
959 }
960
961 static int
dmar_inst_rmrr_iter(ACPI_DMAR_HEADER * dmarh,void * arg)962 dmar_inst_rmrr_iter(ACPI_DMAR_HEADER *dmarh, void *arg)
963 {
964 const ACPI_DMAR_RESERVED_MEMORY *resmem;
965 const ACPI_DMAR_DEVICE_SCOPE *devscope;
966 struct inst_rmrr_iter_args *iria;
967 const char *ptr, *ptrend;
968 struct dmar_unit *dev_dmar;
969 device_t dev;
970
971 if (dmarh->Type != ACPI_DMAR_TYPE_RESERVED_MEMORY)
972 return (1);
973
974 iria = arg;
975 resmem = (ACPI_DMAR_RESERVED_MEMORY *)dmarh;
976 if (resmem->Segment != iria->dmar->segment)
977 return (1);
978 if (dmar_match_verbose) {
979 printf("dmar%d: RMRR [%jx,%jx]\n", iria->dmar->unit,
980 (uintmax_t)resmem->BaseAddress,
981 (uintmax_t)resmem->EndAddress);
982 }
983
984 ptr = (const char *)resmem + sizeof(*resmem);
985 ptrend = (const char *)resmem + resmem->Header.Length;
986 for (;;) {
987 if (ptr >= ptrend)
988 break;
989 devscope = (const ACPI_DMAR_DEVICE_SCOPE *)ptr;
990 ptr += devscope->Length;
991 /* XXXKIB bridge */
992 if (devscope->EntryType != ACPI_DMAR_SCOPE_TYPE_ENDPOINT)
993 continue;
994 if (dmar_match_verbose) {
995 dmar_print_path(iria->dmar->dev, "RMRR scope",
996 devscope->Bus, (devscope->Length -
997 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2,
998 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
999 }
1000 dev = dmar_path_dev(resmem->Segment, (devscope->Length -
1001 sizeof(ACPI_DMAR_DEVICE_SCOPE)) / 2, devscope->Bus,
1002 (const ACPI_DMAR_PCI_PATH *)(devscope + 1));
1003 if (dev == NULL) {
1004 if (dmar_match_verbose)
1005 printf("null dev\n");
1006 continue;
1007 }
1008 dev_dmar = dmar_find(dev);
1009 if (dev_dmar != iria->dmar) {
1010 if (dmar_match_verbose) {
1011 printf("dmar%d matched, skipping\n",
1012 dev_dmar->unit);
1013 }
1014 continue;
1015 }
1016 if (dmar_match_verbose)
1017 printf("matched, instantiating RMRR context\n");
1018 dmar_instantiate_ctx(iria->dmar, dev, true);
1019 }
1020
1021 return (1);
1022
1023 }
1024
1025 /*
1026 * Pre-create all contexts for the DMAR which have RMRR entries.
1027 */
1028 int
dmar_instantiate_rmrr_ctxs(struct dmar_unit * dmar)1029 dmar_instantiate_rmrr_ctxs(struct dmar_unit *dmar)
1030 {
1031 struct inst_rmrr_iter_args iria;
1032 int error;
1033
1034 if (!dmar_barrier_enter(dmar, DMAR_BARRIER_RMRR))
1035 return (0);
1036
1037 error = 0;
1038 iria.dmar = dmar;
1039 if (dmar_match_verbose)
1040 printf("dmar%d: instantiating RMRR contexts\n", dmar->unit);
1041 dmar_iterate_tbl(dmar_inst_rmrr_iter, &iria);
1042 DMAR_LOCK(dmar);
1043 if (!LIST_EMPTY(&dmar->domains)) {
1044 KASSERT((dmar->hw_gcmd & DMAR_GCMD_TE) == 0,
1045 ("dmar%d: RMRR not handled but translation is already enabled",
1046 dmar->unit));
1047 error = dmar_enable_translation(dmar);
1048 }
1049 dmar_barrier_exit(dmar, DMAR_BARRIER_RMRR);
1050 return (error);
1051 }
1052
1053 #ifdef DDB
1054 #include <ddb/ddb.h>
1055 #include <ddb/db_lex.h>
1056
1057 static void
dmar_print_domain_entry(const struct dmar_map_entry * entry)1058 dmar_print_domain_entry(const struct dmar_map_entry *entry)
1059 {
1060 struct dmar_map_entry *l, *r;
1061
1062 db_printf(
1063 " start %jx end %jx free_after %jx free_down %jx flags %x ",
1064 entry->start, entry->end, entry->free_after, entry->free_down,
1065 entry->flags);
1066 db_printf("left ");
1067 l = RB_LEFT(entry, rb_entry);
1068 if (l == NULL)
1069 db_printf("NULL ");
1070 else
1071 db_printf("%jx ", l->start);
1072 db_printf("right ");
1073 r = RB_RIGHT(entry, rb_entry);
1074 if (r == NULL)
1075 db_printf("NULL");
1076 else
1077 db_printf("%jx", r->start);
1078 db_printf("\n");
1079 }
1080
1081 static void
dmar_print_ctx(struct dmar_ctx * ctx)1082 dmar_print_ctx(struct dmar_ctx *ctx)
1083 {
1084
1085 db_printf(
1086 " @%p pci%d:%d:%d refs %d flags %x loads %lu unloads %lu\n",
1087 ctx, pci_get_bus(ctx->ctx_tag.owner),
1088 pci_get_slot(ctx->ctx_tag.owner),
1089 pci_get_function(ctx->ctx_tag.owner), ctx->refs, ctx->flags,
1090 ctx->loads, ctx->unloads);
1091 }
1092
1093 static void
dmar_print_domain(struct dmar_domain * domain,bool show_mappings)1094 dmar_print_domain(struct dmar_domain *domain, bool show_mappings)
1095 {
1096 struct dmar_map_entry *entry;
1097 struct dmar_ctx *ctx;
1098
1099 db_printf(
1100 " @%p dom %d mgaw %d agaw %d pglvl %d end %jx refs %d\n"
1101 " ctx_cnt %d flags %x pgobj %p map_ents %u\n",
1102 domain, domain->domain, domain->mgaw, domain->agaw, domain->pglvl,
1103 (uintmax_t)domain->end, domain->refs, domain->ctx_cnt,
1104 domain->flags, domain->pgtbl_obj, domain->entries_cnt);
1105 if (!LIST_EMPTY(&domain->contexts)) {
1106 db_printf(" Contexts:\n");
1107 LIST_FOREACH(ctx, &domain->contexts, link)
1108 dmar_print_ctx(ctx);
1109 }
1110 if (!show_mappings)
1111 return;
1112 db_printf(" mapped:\n");
1113 RB_FOREACH(entry, dmar_gas_entries_tree, &domain->rb_root) {
1114 dmar_print_domain_entry(entry);
1115 if (db_pager_quit)
1116 break;
1117 }
1118 if (db_pager_quit)
1119 return;
1120 db_printf(" unloading:\n");
1121 TAILQ_FOREACH(entry, &domain->unload_entries, dmamap_link) {
1122 dmar_print_domain_entry(entry);
1123 if (db_pager_quit)
1124 break;
1125 }
1126 }
1127
DB_FUNC(dmar_domain,db_dmar_print_domain,db_show_table,CS_OWN,NULL)1128 DB_FUNC(dmar_domain, db_dmar_print_domain, db_show_table, CS_OWN, NULL)
1129 {
1130 struct dmar_unit *unit;
1131 struct dmar_domain *domain;
1132 struct dmar_ctx *ctx;
1133 bool show_mappings, valid;
1134 int pci_domain, bus, device, function, i, t;
1135 db_expr_t radix;
1136
1137 valid = false;
1138 radix = db_radix;
1139 db_radix = 10;
1140 t = db_read_token();
1141 if (t == tSLASH) {
1142 t = db_read_token();
1143 if (t != tIDENT) {
1144 db_printf("Bad modifier\n");
1145 db_radix = radix;
1146 db_skip_to_eol();
1147 return;
1148 }
1149 show_mappings = strchr(db_tok_string, 'm') != NULL;
1150 t = db_read_token();
1151 } else {
1152 show_mappings = false;
1153 }
1154 if (t == tNUMBER) {
1155 pci_domain = db_tok_number;
1156 t = db_read_token();
1157 if (t == tNUMBER) {
1158 bus = db_tok_number;
1159 t = db_read_token();
1160 if (t == tNUMBER) {
1161 device = db_tok_number;
1162 t = db_read_token();
1163 if (t == tNUMBER) {
1164 function = db_tok_number;
1165 valid = true;
1166 }
1167 }
1168 }
1169 }
1170 db_radix = radix;
1171 db_skip_to_eol();
1172 if (!valid) {
1173 db_printf("usage: show dmar_domain [/m] "
1174 "<domain> <bus> <device> <func>\n");
1175 return;
1176 }
1177 for (i = 0; i < dmar_devcnt; i++) {
1178 unit = device_get_softc(dmar_devs[i]);
1179 LIST_FOREACH(domain, &unit->domains, link) {
1180 LIST_FOREACH(ctx, &domain->contexts, link) {
1181 if (pci_domain == unit->segment &&
1182 bus == pci_get_bus(ctx->ctx_tag.owner) &&
1183 device ==
1184 pci_get_slot(ctx->ctx_tag.owner) &&
1185 function ==
1186 pci_get_function(ctx->ctx_tag.owner)) {
1187 dmar_print_domain(domain,
1188 show_mappings);
1189 goto out;
1190 }
1191 }
1192 }
1193 }
1194 out:;
1195 }
1196
1197 static void
dmar_print_one(int idx,bool show_domains,bool show_mappings)1198 dmar_print_one(int idx, bool show_domains, bool show_mappings)
1199 {
1200 struct dmar_unit *unit;
1201 struct dmar_domain *domain;
1202 int i, frir;
1203
1204 unit = device_get_softc(dmar_devs[idx]);
1205 db_printf("dmar%d at %p, root at 0x%jx, ver 0x%x\n", unit->unit, unit,
1206 dmar_read8(unit, DMAR_RTADDR_REG), dmar_read4(unit, DMAR_VER_REG));
1207 db_printf("cap 0x%jx ecap 0x%jx gsts 0x%x fsts 0x%x fectl 0x%x\n",
1208 (uintmax_t)dmar_read8(unit, DMAR_CAP_REG),
1209 (uintmax_t)dmar_read8(unit, DMAR_ECAP_REG),
1210 dmar_read4(unit, DMAR_GSTS_REG),
1211 dmar_read4(unit, DMAR_FSTS_REG),
1212 dmar_read4(unit, DMAR_FECTL_REG));
1213 if (unit->ir_enabled) {
1214 db_printf("ir is enabled; IRT @%p phys 0x%jx maxcnt %d\n",
1215 unit->irt, (uintmax_t)unit->irt_phys, unit->irte_cnt);
1216 }
1217 db_printf("fed 0x%x fea 0x%x feua 0x%x\n",
1218 dmar_read4(unit, DMAR_FEDATA_REG),
1219 dmar_read4(unit, DMAR_FEADDR_REG),
1220 dmar_read4(unit, DMAR_FEUADDR_REG));
1221 db_printf("primary fault log:\n");
1222 for (i = 0; i < DMAR_CAP_NFR(unit->hw_cap); i++) {
1223 frir = (DMAR_CAP_FRO(unit->hw_cap) + i) * 16;
1224 db_printf(" %d at 0x%x: %jx %jx\n", i, frir,
1225 (uintmax_t)dmar_read8(unit, frir),
1226 (uintmax_t)dmar_read8(unit, frir + 8));
1227 }
1228 if (DMAR_HAS_QI(unit)) {
1229 db_printf("ied 0x%x iea 0x%x ieua 0x%x\n",
1230 dmar_read4(unit, DMAR_IEDATA_REG),
1231 dmar_read4(unit, DMAR_IEADDR_REG),
1232 dmar_read4(unit, DMAR_IEUADDR_REG));
1233 if (unit->qi_enabled) {
1234 db_printf("qi is enabled: queue @0x%jx (IQA 0x%jx) "
1235 "size 0x%jx\n"
1236 " head 0x%x tail 0x%x avail 0x%x status 0x%x ctrl 0x%x\n"
1237 " hw compl 0x%x@%p/phys@%jx next seq 0x%x gen 0x%x\n",
1238 (uintmax_t)unit->inv_queue,
1239 (uintmax_t)dmar_read8(unit, DMAR_IQA_REG),
1240 (uintmax_t)unit->inv_queue_size,
1241 dmar_read4(unit, DMAR_IQH_REG),
1242 dmar_read4(unit, DMAR_IQT_REG),
1243 unit->inv_queue_avail,
1244 dmar_read4(unit, DMAR_ICS_REG),
1245 dmar_read4(unit, DMAR_IECTL_REG),
1246 unit->inv_waitd_seq_hw,
1247 &unit->inv_waitd_seq_hw,
1248 (uintmax_t)unit->inv_waitd_seq_hw_phys,
1249 unit->inv_waitd_seq,
1250 unit->inv_waitd_gen);
1251 } else {
1252 db_printf("qi is disabled\n");
1253 }
1254 }
1255 if (show_domains) {
1256 db_printf("domains:\n");
1257 LIST_FOREACH(domain, &unit->domains, link) {
1258 dmar_print_domain(domain, show_mappings);
1259 if (db_pager_quit)
1260 break;
1261 }
1262 }
1263 }
1264
DB_SHOW_COMMAND(dmar,db_dmar_print)1265 DB_SHOW_COMMAND(dmar, db_dmar_print)
1266 {
1267 bool show_domains, show_mappings;
1268
1269 show_domains = strchr(modif, 'd') != NULL;
1270 show_mappings = strchr(modif, 'm') != NULL;
1271 if (!have_addr) {
1272 db_printf("usage: show dmar [/d] [/m] index\n");
1273 return;
1274 }
1275 dmar_print_one((int)addr, show_domains, show_mappings);
1276 }
1277
DB_SHOW_ALL_COMMAND(dmars,db_show_all_dmars)1278 DB_SHOW_ALL_COMMAND(dmars, db_show_all_dmars)
1279 {
1280 int i;
1281 bool show_domains, show_mappings;
1282
1283 show_domains = strchr(modif, 'd') != NULL;
1284 show_mappings = strchr(modif, 'm') != NULL;
1285
1286 for (i = 0; i < dmar_devcnt; i++) {
1287 dmar_print_one(i, show_domains, show_mappings);
1288 if (db_pager_quit)
1289 break;
1290 }
1291 }
1292 #endif
1293