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39
40
41 /**
42 * cvmx-pow-defs.h
43 *
44 * Configuration and status register (CSR) type definitions for
45 * Octeon pow.
46 *
47 * This file is auto generated. Do not edit.
48 *
49 * <hr>$Revision$<hr>
50 *
51 */
52 #ifndef __CVMX_POW_DEFS_H__
53 #define __CVMX_POW_DEFS_H__
54
55 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
56 #define CVMX_POW_BIST_STAT CVMX_POW_BIST_STAT_FUNC()
CVMX_POW_BIST_STAT_FUNC(void)57 static inline uint64_t CVMX_POW_BIST_STAT_FUNC(void)
58 {
59 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
60 cvmx_warn("CVMX_POW_BIST_STAT not supported on this chip\n");
61 return CVMX_ADD_IO_SEG(0x00016700000003F8ull);
62 }
63 #else
64 #define CVMX_POW_BIST_STAT (CVMX_ADD_IO_SEG(0x00016700000003F8ull))
65 #endif
66 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
67 #define CVMX_POW_DS_PC CVMX_POW_DS_PC_FUNC()
CVMX_POW_DS_PC_FUNC(void)68 static inline uint64_t CVMX_POW_DS_PC_FUNC(void)
69 {
70 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
71 cvmx_warn("CVMX_POW_DS_PC not supported on this chip\n");
72 return CVMX_ADD_IO_SEG(0x0001670000000398ull);
73 }
74 #else
75 #define CVMX_POW_DS_PC (CVMX_ADD_IO_SEG(0x0001670000000398ull))
76 #endif
77 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
78 #define CVMX_POW_ECC_ERR CVMX_POW_ECC_ERR_FUNC()
CVMX_POW_ECC_ERR_FUNC(void)79 static inline uint64_t CVMX_POW_ECC_ERR_FUNC(void)
80 {
81 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
82 cvmx_warn("CVMX_POW_ECC_ERR not supported on this chip\n");
83 return CVMX_ADD_IO_SEG(0x0001670000000218ull);
84 }
85 #else
86 #define CVMX_POW_ECC_ERR (CVMX_ADD_IO_SEG(0x0001670000000218ull))
87 #endif
88 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
89 #define CVMX_POW_INT_CTL CVMX_POW_INT_CTL_FUNC()
CVMX_POW_INT_CTL_FUNC(void)90 static inline uint64_t CVMX_POW_INT_CTL_FUNC(void)
91 {
92 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
93 cvmx_warn("CVMX_POW_INT_CTL not supported on this chip\n");
94 return CVMX_ADD_IO_SEG(0x0001670000000220ull);
95 }
96 #else
97 #define CVMX_POW_INT_CTL (CVMX_ADD_IO_SEG(0x0001670000000220ull))
98 #endif
99 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_POW_IQ_CNTX(unsigned long offset)100 static inline uint64_t CVMX_POW_IQ_CNTX(unsigned long offset)
101 {
102 if (!(
103 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
104 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
105 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
106 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
107 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
108 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
109 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
110 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
111 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
112 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
113 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
114 cvmx_warn("CVMX_POW_IQ_CNTX(%lu) is invalid on this chip\n", offset);
115 return CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8;
116 }
117 #else
118 #define CVMX_POW_IQ_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000340ull) + ((offset) & 7) * 8)
119 #endif
120 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
121 #define CVMX_POW_IQ_COM_CNT CVMX_POW_IQ_COM_CNT_FUNC()
CVMX_POW_IQ_COM_CNT_FUNC(void)122 static inline uint64_t CVMX_POW_IQ_COM_CNT_FUNC(void)
123 {
124 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
125 cvmx_warn("CVMX_POW_IQ_COM_CNT not supported on this chip\n");
126 return CVMX_ADD_IO_SEG(0x0001670000000388ull);
127 }
128 #else
129 #define CVMX_POW_IQ_COM_CNT (CVMX_ADD_IO_SEG(0x0001670000000388ull))
130 #endif
131 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
132 #define CVMX_POW_IQ_INT CVMX_POW_IQ_INT_FUNC()
CVMX_POW_IQ_INT_FUNC(void)133 static inline uint64_t CVMX_POW_IQ_INT_FUNC(void)
134 {
135 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
136 cvmx_warn("CVMX_POW_IQ_INT not supported on this chip\n");
137 return CVMX_ADD_IO_SEG(0x0001670000000238ull);
138 }
139 #else
140 #define CVMX_POW_IQ_INT (CVMX_ADD_IO_SEG(0x0001670000000238ull))
141 #endif
142 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
143 #define CVMX_POW_IQ_INT_EN CVMX_POW_IQ_INT_EN_FUNC()
CVMX_POW_IQ_INT_EN_FUNC(void)144 static inline uint64_t CVMX_POW_IQ_INT_EN_FUNC(void)
145 {
146 if (!(OCTEON_IS_MODEL(OCTEON_CN52XX) || OCTEON_IS_MODEL(OCTEON_CN56XX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
147 cvmx_warn("CVMX_POW_IQ_INT_EN not supported on this chip\n");
148 return CVMX_ADD_IO_SEG(0x0001670000000240ull);
149 }
150 #else
151 #define CVMX_POW_IQ_INT_EN (CVMX_ADD_IO_SEG(0x0001670000000240ull))
152 #endif
153 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_POW_IQ_THRX(unsigned long offset)154 static inline uint64_t CVMX_POW_IQ_THRX(unsigned long offset)
155 {
156 if (!(
157 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
158 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
159 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
160 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
161 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
162 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
163 cvmx_warn("CVMX_POW_IQ_THRX(%lu) is invalid on this chip\n", offset);
164 return CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8;
165 }
166 #else
167 #define CVMX_POW_IQ_THRX(offset) (CVMX_ADD_IO_SEG(0x00016700000003A0ull) + ((offset) & 7) * 8)
168 #endif
169 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
170 #define CVMX_POW_NOS_CNT CVMX_POW_NOS_CNT_FUNC()
CVMX_POW_NOS_CNT_FUNC(void)171 static inline uint64_t CVMX_POW_NOS_CNT_FUNC(void)
172 {
173 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
174 cvmx_warn("CVMX_POW_NOS_CNT not supported on this chip\n");
175 return CVMX_ADD_IO_SEG(0x0001670000000228ull);
176 }
177 #else
178 #define CVMX_POW_NOS_CNT (CVMX_ADD_IO_SEG(0x0001670000000228ull))
179 #endif
180 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
181 #define CVMX_POW_NW_TIM CVMX_POW_NW_TIM_FUNC()
CVMX_POW_NW_TIM_FUNC(void)182 static inline uint64_t CVMX_POW_NW_TIM_FUNC(void)
183 {
184 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
185 cvmx_warn("CVMX_POW_NW_TIM not supported on this chip\n");
186 return CVMX_ADD_IO_SEG(0x0001670000000210ull);
187 }
188 #else
189 #define CVMX_POW_NW_TIM (CVMX_ADD_IO_SEG(0x0001670000000210ull))
190 #endif
191 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
192 #define CVMX_POW_PF_RST_MSK CVMX_POW_PF_RST_MSK_FUNC()
CVMX_POW_PF_RST_MSK_FUNC(void)193 static inline uint64_t CVMX_POW_PF_RST_MSK_FUNC(void)
194 {
195 if (!(OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
196 cvmx_warn("CVMX_POW_PF_RST_MSK not supported on this chip\n");
197 return CVMX_ADD_IO_SEG(0x0001670000000230ull);
198 }
199 #else
200 #define CVMX_POW_PF_RST_MSK (CVMX_ADD_IO_SEG(0x0001670000000230ull))
201 #endif
202 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_POW_PP_GRP_MSKX(unsigned long offset)203 static inline uint64_t CVMX_POW_PP_GRP_MSKX(unsigned long offset)
204 {
205 if (!(
206 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset == 0))) ||
207 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 1))) ||
208 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
209 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 1))) ||
210 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 3))) ||
211 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 11))) ||
212 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
213 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 3))) ||
214 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 5))) ||
215 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 9))) ||
216 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 3)))))
217 cvmx_warn("CVMX_POW_PP_GRP_MSKX(%lu) is invalid on this chip\n", offset);
218 return CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8;
219 }
220 #else
221 #define CVMX_POW_PP_GRP_MSKX(offset) (CVMX_ADD_IO_SEG(0x0001670000000000ull) + ((offset) & 15) * 8)
222 #endif
223 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_POW_QOS_RNDX(unsigned long offset)224 static inline uint64_t CVMX_POW_QOS_RNDX(unsigned long offset)
225 {
226 if (!(
227 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
228 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
229 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
230 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
231 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
232 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
233 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
234 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
235 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
236 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
237 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
238 cvmx_warn("CVMX_POW_QOS_RNDX(%lu) is invalid on this chip\n", offset);
239 return CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8;
240 }
241 #else
242 #define CVMX_POW_QOS_RNDX(offset) (CVMX_ADD_IO_SEG(0x00016700000001C0ull) + ((offset) & 7) * 8)
243 #endif
244 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_POW_QOS_THRX(unsigned long offset)245 static inline uint64_t CVMX_POW_QOS_THRX(unsigned long offset)
246 {
247 if (!(
248 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
249 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
250 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
251 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
252 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
253 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
254 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
255 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
256 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
257 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
258 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
259 cvmx_warn("CVMX_POW_QOS_THRX(%lu) is invalid on this chip\n", offset);
260 return CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8;
261 }
262 #else
263 #define CVMX_POW_QOS_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000180ull) + ((offset) & 7) * 8)
264 #endif
265 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
266 #define CVMX_POW_TS_PC CVMX_POW_TS_PC_FUNC()
CVMX_POW_TS_PC_FUNC(void)267 static inline uint64_t CVMX_POW_TS_PC_FUNC(void)
268 {
269 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
270 cvmx_warn("CVMX_POW_TS_PC not supported on this chip\n");
271 return CVMX_ADD_IO_SEG(0x0001670000000390ull);
272 }
273 #else
274 #define CVMX_POW_TS_PC (CVMX_ADD_IO_SEG(0x0001670000000390ull))
275 #endif
276 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
277 #define CVMX_POW_WA_COM_PC CVMX_POW_WA_COM_PC_FUNC()
CVMX_POW_WA_COM_PC_FUNC(void)278 static inline uint64_t CVMX_POW_WA_COM_PC_FUNC(void)
279 {
280 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
281 cvmx_warn("CVMX_POW_WA_COM_PC not supported on this chip\n");
282 return CVMX_ADD_IO_SEG(0x0001670000000380ull);
283 }
284 #else
285 #define CVMX_POW_WA_COM_PC (CVMX_ADD_IO_SEG(0x0001670000000380ull))
286 #endif
287 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_POW_WA_PCX(unsigned long offset)288 static inline uint64_t CVMX_POW_WA_PCX(unsigned long offset)
289 {
290 if (!(
291 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 7))) ||
292 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 7))) ||
293 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 7))) ||
294 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 7))) ||
295 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 7))) ||
296 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 7))) ||
297 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 7))) ||
298 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 7))) ||
299 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 7))) ||
300 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 7))) ||
301 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 7)))))
302 cvmx_warn("CVMX_POW_WA_PCX(%lu) is invalid on this chip\n", offset);
303 return CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8;
304 }
305 #else
306 #define CVMX_POW_WA_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000300ull) + ((offset) & 7) * 8)
307 #endif
308 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
309 #define CVMX_POW_WQ_INT CVMX_POW_WQ_INT_FUNC()
CVMX_POW_WQ_INT_FUNC(void)310 static inline uint64_t CVMX_POW_WQ_INT_FUNC(void)
311 {
312 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
313 cvmx_warn("CVMX_POW_WQ_INT not supported on this chip\n");
314 return CVMX_ADD_IO_SEG(0x0001670000000200ull);
315 }
316 #else
317 #define CVMX_POW_WQ_INT (CVMX_ADD_IO_SEG(0x0001670000000200ull))
318 #endif
319 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_POW_WQ_INT_CNTX(unsigned long offset)320 static inline uint64_t CVMX_POW_WQ_INT_CNTX(unsigned long offset)
321 {
322 if (!(
323 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
324 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
325 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
326 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
327 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
328 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
329 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
330 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
331 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
332 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
333 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
334 cvmx_warn("CVMX_POW_WQ_INT_CNTX(%lu) is invalid on this chip\n", offset);
335 return CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8;
336 }
337 #else
338 #define CVMX_POW_WQ_INT_CNTX(offset) (CVMX_ADD_IO_SEG(0x0001670000000100ull) + ((offset) & 15) * 8)
339 #endif
340 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
341 #define CVMX_POW_WQ_INT_PC CVMX_POW_WQ_INT_PC_FUNC()
CVMX_POW_WQ_INT_PC_FUNC(void)342 static inline uint64_t CVMX_POW_WQ_INT_PC_FUNC(void)
343 {
344 if (!(OCTEON_IS_MODEL(OCTEON_CN3XXX) || OCTEON_IS_MODEL(OCTEON_CN5XXX) || OCTEON_IS_MODEL(OCTEON_CN61XX) || OCTEON_IS_MODEL(OCTEON_CN63XX) || OCTEON_IS_MODEL(OCTEON_CN66XX) || OCTEON_IS_MODEL(OCTEON_CNF71XX)))
345 cvmx_warn("CVMX_POW_WQ_INT_PC not supported on this chip\n");
346 return CVMX_ADD_IO_SEG(0x0001670000000208ull);
347 }
348 #else
349 #define CVMX_POW_WQ_INT_PC (CVMX_ADD_IO_SEG(0x0001670000000208ull))
350 #endif
351 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_POW_WQ_INT_THRX(unsigned long offset)352 static inline uint64_t CVMX_POW_WQ_INT_THRX(unsigned long offset)
353 {
354 if (!(
355 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
356 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
357 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
358 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
359 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
360 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
361 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
362 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
363 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
364 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
365 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
366 cvmx_warn("CVMX_POW_WQ_INT_THRX(%lu) is invalid on this chip\n", offset);
367 return CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8;
368 }
369 #else
370 #define CVMX_POW_WQ_INT_THRX(offset) (CVMX_ADD_IO_SEG(0x0001670000000080ull) + ((offset) & 15) * 8)
371 #endif
372 #if CVMX_ENABLE_CSR_ADDRESS_CHECKING
CVMX_POW_WS_PCX(unsigned long offset)373 static inline uint64_t CVMX_POW_WS_PCX(unsigned long offset)
374 {
375 if (!(
376 (OCTEON_IS_MODEL(OCTEON_CN30XX) && ((offset <= 15))) ||
377 (OCTEON_IS_MODEL(OCTEON_CN31XX) && ((offset <= 15))) ||
378 (OCTEON_IS_MODEL(OCTEON_CN38XX) && ((offset <= 15))) ||
379 (OCTEON_IS_MODEL(OCTEON_CN50XX) && ((offset <= 15))) ||
380 (OCTEON_IS_MODEL(OCTEON_CN52XX) && ((offset <= 15))) ||
381 (OCTEON_IS_MODEL(OCTEON_CN56XX) && ((offset <= 15))) ||
382 (OCTEON_IS_MODEL(OCTEON_CN58XX) && ((offset <= 15))) ||
383 (OCTEON_IS_MODEL(OCTEON_CN61XX) && ((offset <= 15))) ||
384 (OCTEON_IS_MODEL(OCTEON_CN63XX) && ((offset <= 15))) ||
385 (OCTEON_IS_MODEL(OCTEON_CN66XX) && ((offset <= 15))) ||
386 (OCTEON_IS_MODEL(OCTEON_CNF71XX) && ((offset <= 15)))))
387 cvmx_warn("CVMX_POW_WS_PCX(%lu) is invalid on this chip\n", offset);
388 return CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8;
389 }
390 #else
391 #define CVMX_POW_WS_PCX(offset) (CVMX_ADD_IO_SEG(0x0001670000000280ull) + ((offset) & 15) * 8)
392 #endif
393
394 /**
395 * cvmx_pow_bist_stat
396 *
397 * POW_BIST_STAT = POW BIST Status Register
398 *
399 * Contains the BIST status for the POW memories ('0' = pass, '1' = fail).
400 *
401 * Also contains the BIST status for the PP's. Each bit in the PP field is the OR of all BIST
402 * results for the corresponding physical PP ('0' = pass, '1' = fail).
403 */
404 union cvmx_pow_bist_stat {
405 uint64_t u64;
406 struct cvmx_pow_bist_stat_s {
407 #ifdef __BIG_ENDIAN_BITFIELD
408 uint64_t reserved_32_63 : 32;
409 uint64_t pp : 16; /**< Physical PP BIST status */
410 uint64_t reserved_0_15 : 16;
411 #else
412 uint64_t reserved_0_15 : 16;
413 uint64_t pp : 16;
414 uint64_t reserved_32_63 : 32;
415 #endif
416 } s;
417 struct cvmx_pow_bist_stat_cn30xx {
418 #ifdef __BIG_ENDIAN_BITFIELD
419 uint64_t reserved_17_63 : 47;
420 uint64_t pp : 1; /**< Physical PP BIST status */
421 uint64_t reserved_9_15 : 7;
422 uint64_t cam : 1; /**< POW CAM BIST status */
423 uint64_t nbt1 : 1; /**< NCB transmitter memory 1 BIST status */
424 uint64_t nbt0 : 1; /**< NCB transmitter memory 0 BIST status */
425 uint64_t index : 1; /**< Index memory BIST status */
426 uint64_t fidx : 1; /**< Forward index memory BIST status */
427 uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */
428 uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */
429 uint64_t pend : 1; /**< Pending switch memory BIST status */
430 uint64_t adr : 1; /**< Address memory BIST status */
431 #else
432 uint64_t adr : 1;
433 uint64_t pend : 1;
434 uint64_t nbr0 : 1;
435 uint64_t nbr1 : 1;
436 uint64_t fidx : 1;
437 uint64_t index : 1;
438 uint64_t nbt0 : 1;
439 uint64_t nbt1 : 1;
440 uint64_t cam : 1;
441 uint64_t reserved_9_15 : 7;
442 uint64_t pp : 1;
443 uint64_t reserved_17_63 : 47;
444 #endif
445 } cn30xx;
446 struct cvmx_pow_bist_stat_cn31xx {
447 #ifdef __BIG_ENDIAN_BITFIELD
448 uint64_t reserved_18_63 : 46;
449 uint64_t pp : 2; /**< Physical PP BIST status */
450 uint64_t reserved_9_15 : 7;
451 uint64_t cam : 1; /**< POW CAM BIST status */
452 uint64_t nbt1 : 1; /**< NCB transmitter memory 1 BIST status */
453 uint64_t nbt0 : 1; /**< NCB transmitter memory 0 BIST status */
454 uint64_t index : 1; /**< Index memory BIST status */
455 uint64_t fidx : 1; /**< Forward index memory BIST status */
456 uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */
457 uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */
458 uint64_t pend : 1; /**< Pending switch memory BIST status */
459 uint64_t adr : 1; /**< Address memory BIST status */
460 #else
461 uint64_t adr : 1;
462 uint64_t pend : 1;
463 uint64_t nbr0 : 1;
464 uint64_t nbr1 : 1;
465 uint64_t fidx : 1;
466 uint64_t index : 1;
467 uint64_t nbt0 : 1;
468 uint64_t nbt1 : 1;
469 uint64_t cam : 1;
470 uint64_t reserved_9_15 : 7;
471 uint64_t pp : 2;
472 uint64_t reserved_18_63 : 46;
473 #endif
474 } cn31xx;
475 struct cvmx_pow_bist_stat_cn38xx {
476 #ifdef __BIG_ENDIAN_BITFIELD
477 uint64_t reserved_32_63 : 32;
478 uint64_t pp : 16; /**< Physical PP BIST status */
479 uint64_t reserved_10_15 : 6;
480 uint64_t cam : 1; /**< POW CAM BIST status */
481 uint64_t nbt : 1; /**< NCB transmitter memory BIST status */
482 uint64_t index : 1; /**< Index memory BIST status */
483 uint64_t fidx : 1; /**< Forward index memory BIST status */
484 uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */
485 uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */
486 uint64_t pend1 : 1; /**< Pending switch memory 1 BIST status */
487 uint64_t pend0 : 1; /**< Pending switch memory 0 BIST status */
488 uint64_t adr1 : 1; /**< Address memory 1 BIST status */
489 uint64_t adr0 : 1; /**< Address memory 0 BIST status */
490 #else
491 uint64_t adr0 : 1;
492 uint64_t adr1 : 1;
493 uint64_t pend0 : 1;
494 uint64_t pend1 : 1;
495 uint64_t nbr0 : 1;
496 uint64_t nbr1 : 1;
497 uint64_t fidx : 1;
498 uint64_t index : 1;
499 uint64_t nbt : 1;
500 uint64_t cam : 1;
501 uint64_t reserved_10_15 : 6;
502 uint64_t pp : 16;
503 uint64_t reserved_32_63 : 32;
504 #endif
505 } cn38xx;
506 struct cvmx_pow_bist_stat_cn38xx cn38xxp2;
507 struct cvmx_pow_bist_stat_cn31xx cn50xx;
508 struct cvmx_pow_bist_stat_cn52xx {
509 #ifdef __BIG_ENDIAN_BITFIELD
510 uint64_t reserved_20_63 : 44;
511 uint64_t pp : 4; /**< Physical PP BIST status */
512 uint64_t reserved_9_15 : 7;
513 uint64_t cam : 1; /**< POW CAM BIST status */
514 uint64_t nbt1 : 1; /**< NCB transmitter memory 1 BIST status */
515 uint64_t nbt0 : 1; /**< NCB transmitter memory 0 BIST status */
516 uint64_t index : 1; /**< Index memory BIST status */
517 uint64_t fidx : 1; /**< Forward index memory BIST status */
518 uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */
519 uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */
520 uint64_t pend : 1; /**< Pending switch memory BIST status */
521 uint64_t adr : 1; /**< Address memory BIST status */
522 #else
523 uint64_t adr : 1;
524 uint64_t pend : 1;
525 uint64_t nbr0 : 1;
526 uint64_t nbr1 : 1;
527 uint64_t fidx : 1;
528 uint64_t index : 1;
529 uint64_t nbt0 : 1;
530 uint64_t nbt1 : 1;
531 uint64_t cam : 1;
532 uint64_t reserved_9_15 : 7;
533 uint64_t pp : 4;
534 uint64_t reserved_20_63 : 44;
535 #endif
536 } cn52xx;
537 struct cvmx_pow_bist_stat_cn52xx cn52xxp1;
538 struct cvmx_pow_bist_stat_cn56xx {
539 #ifdef __BIG_ENDIAN_BITFIELD
540 uint64_t reserved_28_63 : 36;
541 uint64_t pp : 12; /**< Physical PP BIST status */
542 uint64_t reserved_10_15 : 6;
543 uint64_t cam : 1; /**< POW CAM BIST status */
544 uint64_t nbt : 1; /**< NCB transmitter memory BIST status */
545 uint64_t index : 1; /**< Index memory BIST status */
546 uint64_t fidx : 1; /**< Forward index memory BIST status */
547 uint64_t nbr1 : 1; /**< NCB receiver memory 1 BIST status */
548 uint64_t nbr0 : 1; /**< NCB receiver memory 0 BIST status */
549 uint64_t pend1 : 1; /**< Pending switch memory 1 BIST status */
550 uint64_t pend0 : 1; /**< Pending switch memory 0 BIST status */
551 uint64_t adr1 : 1; /**< Address memory 1 BIST status */
552 uint64_t adr0 : 1; /**< Address memory 0 BIST status */
553 #else
554 uint64_t adr0 : 1;
555 uint64_t adr1 : 1;
556 uint64_t pend0 : 1;
557 uint64_t pend1 : 1;
558 uint64_t nbr0 : 1;
559 uint64_t nbr1 : 1;
560 uint64_t fidx : 1;
561 uint64_t index : 1;
562 uint64_t nbt : 1;
563 uint64_t cam : 1;
564 uint64_t reserved_10_15 : 6;
565 uint64_t pp : 12;
566 uint64_t reserved_28_63 : 36;
567 #endif
568 } cn56xx;
569 struct cvmx_pow_bist_stat_cn56xx cn56xxp1;
570 struct cvmx_pow_bist_stat_cn38xx cn58xx;
571 struct cvmx_pow_bist_stat_cn38xx cn58xxp1;
572 struct cvmx_pow_bist_stat_cn61xx {
573 #ifdef __BIG_ENDIAN_BITFIELD
574 uint64_t reserved_20_63 : 44;
575 uint64_t pp : 4; /**< Physical PP BIST status */
576 uint64_t reserved_12_15 : 4;
577 uint64_t cam : 1; /**< POW CAM BIST status */
578 uint64_t nbr : 3; /**< NCB receiver memory BIST status */
579 uint64_t nbt : 4; /**< NCB transmitter memory BIST status */
580 uint64_t index : 1; /**< Index memory BIST status */
581 uint64_t fidx : 1; /**< Forward index memory BIST status */
582 uint64_t pend : 1; /**< Pending switch memory BIST status */
583 uint64_t adr : 1; /**< Address memory BIST status */
584 #else
585 uint64_t adr : 1;
586 uint64_t pend : 1;
587 uint64_t fidx : 1;
588 uint64_t index : 1;
589 uint64_t nbt : 4;
590 uint64_t nbr : 3;
591 uint64_t cam : 1;
592 uint64_t reserved_12_15 : 4;
593 uint64_t pp : 4;
594 uint64_t reserved_20_63 : 44;
595 #endif
596 } cn61xx;
597 struct cvmx_pow_bist_stat_cn63xx {
598 #ifdef __BIG_ENDIAN_BITFIELD
599 uint64_t reserved_22_63 : 42;
600 uint64_t pp : 6; /**< Physical PP BIST status */
601 uint64_t reserved_12_15 : 4;
602 uint64_t cam : 1; /**< POW CAM BIST status */
603 uint64_t nbr : 3; /**< NCB receiver memory BIST status */
604 uint64_t nbt : 4; /**< NCB transmitter memory BIST status */
605 uint64_t index : 1; /**< Index memory BIST status */
606 uint64_t fidx : 1; /**< Forward index memory BIST status */
607 uint64_t pend : 1; /**< Pending switch memory BIST status */
608 uint64_t adr : 1; /**< Address memory BIST status */
609 #else
610 uint64_t adr : 1;
611 uint64_t pend : 1;
612 uint64_t fidx : 1;
613 uint64_t index : 1;
614 uint64_t nbt : 4;
615 uint64_t nbr : 3;
616 uint64_t cam : 1;
617 uint64_t reserved_12_15 : 4;
618 uint64_t pp : 6;
619 uint64_t reserved_22_63 : 42;
620 #endif
621 } cn63xx;
622 struct cvmx_pow_bist_stat_cn63xx cn63xxp1;
623 struct cvmx_pow_bist_stat_cn66xx {
624 #ifdef __BIG_ENDIAN_BITFIELD
625 uint64_t reserved_26_63 : 38;
626 uint64_t pp : 10; /**< Physical PP BIST status */
627 uint64_t reserved_12_15 : 4;
628 uint64_t cam : 1; /**< POW CAM BIST status */
629 uint64_t nbr : 3; /**< NCB receiver memory BIST status */
630 uint64_t nbt : 4; /**< NCB transmitter memory BIST status */
631 uint64_t index : 1; /**< Index memory BIST status */
632 uint64_t fidx : 1; /**< Forward index memory BIST status */
633 uint64_t pend : 1; /**< Pending switch memory BIST status */
634 uint64_t adr : 1; /**< Address memory BIST status */
635 #else
636 uint64_t adr : 1;
637 uint64_t pend : 1;
638 uint64_t fidx : 1;
639 uint64_t index : 1;
640 uint64_t nbt : 4;
641 uint64_t nbr : 3;
642 uint64_t cam : 1;
643 uint64_t reserved_12_15 : 4;
644 uint64_t pp : 10;
645 uint64_t reserved_26_63 : 38;
646 #endif
647 } cn66xx;
648 struct cvmx_pow_bist_stat_cn61xx cnf71xx;
649 };
650 typedef union cvmx_pow_bist_stat cvmx_pow_bist_stat_t;
651
652 /**
653 * cvmx_pow_ds_pc
654 *
655 * POW_DS_PC = POW De-Schedule Performance Counter
656 *
657 * Counts the number of de-schedule requests. Write to clear.
658 */
659 union cvmx_pow_ds_pc {
660 uint64_t u64;
661 struct cvmx_pow_ds_pc_s {
662 #ifdef __BIG_ENDIAN_BITFIELD
663 uint64_t reserved_32_63 : 32;
664 uint64_t ds_pc : 32; /**< De-schedule performance counter */
665 #else
666 uint64_t ds_pc : 32;
667 uint64_t reserved_32_63 : 32;
668 #endif
669 } s;
670 struct cvmx_pow_ds_pc_s cn30xx;
671 struct cvmx_pow_ds_pc_s cn31xx;
672 struct cvmx_pow_ds_pc_s cn38xx;
673 struct cvmx_pow_ds_pc_s cn38xxp2;
674 struct cvmx_pow_ds_pc_s cn50xx;
675 struct cvmx_pow_ds_pc_s cn52xx;
676 struct cvmx_pow_ds_pc_s cn52xxp1;
677 struct cvmx_pow_ds_pc_s cn56xx;
678 struct cvmx_pow_ds_pc_s cn56xxp1;
679 struct cvmx_pow_ds_pc_s cn58xx;
680 struct cvmx_pow_ds_pc_s cn58xxp1;
681 struct cvmx_pow_ds_pc_s cn61xx;
682 struct cvmx_pow_ds_pc_s cn63xx;
683 struct cvmx_pow_ds_pc_s cn63xxp1;
684 struct cvmx_pow_ds_pc_s cn66xx;
685 struct cvmx_pow_ds_pc_s cnf71xx;
686 };
687 typedef union cvmx_pow_ds_pc cvmx_pow_ds_pc_t;
688
689 /**
690 * cvmx_pow_ecc_err
691 *
692 * POW_ECC_ERR = POW ECC Error Register
693 *
694 * Contains the single and double error bits and the corresponding interrupt enables for the ECC-
695 * protected POW index memory. Also contains the syndrome value in the event of an ECC error.
696 *
697 * Also contains the remote pointer error bit and interrupt enable. RPE is set when the POW detected
698 * corruption on one or more of the input queue lists in L2/DRAM (POW's local copy of the tail pointer
699 * for the L2/DRAM input queue did not match the last entry on the the list). This is caused by
700 * L2/DRAM corruption, and is generally a fatal error because it likely caused POW to load bad work
701 * queue entries.
702 *
703 * This register also contains the illegal operation error bits and the corresponding interrupt
704 * enables as follows:
705 *
706 * <0> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL_NULL state
707 * <1> Received SWTAG/SWTAG_DESCH/DESCH/UPD_WQP from PP in NULL state
708 * <2> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/GET_WORK from PP with pending tag switch to ORDERED or ATOMIC
709 * <3> Received SWTAG/SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL_NULL
710 * <4> Received SWTAG_FULL/SWTAG_DESCH from PP with tag specified as NULL
711 * <5> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with GET_WORK pending
712 * <6> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with NULL_RD pending
713 * <7> Received CLR_NSCHED from PP with SWTAG_DESCH/DESCH/CLR_NSCHED pending
714 * <8> Received SWTAG/SWTAG_FULL/SWTAG_DESCH/DESCH/UPD_WQP/GET_WORK/NULL_RD from PP with CLR_NSCHED pending
715 * <9> Received illegal opcode
716 * <10> Received ADD_WORK with tag specified as NULL_NULL
717 * <11> Received DBG load from PP with DBG load pending
718 * <12> Received CSR load from PP with CSR load pending
719 */
720 union cvmx_pow_ecc_err {
721 uint64_t u64;
722 struct cvmx_pow_ecc_err_s {
723 #ifdef __BIG_ENDIAN_BITFIELD
724 uint64_t reserved_45_63 : 19;
725 uint64_t iop_ie : 13; /**< Illegal operation interrupt enables */
726 uint64_t reserved_29_31 : 3;
727 uint64_t iop : 13; /**< Illegal operation errors */
728 uint64_t reserved_14_15 : 2;
729 uint64_t rpe_ie : 1; /**< Remote pointer error interrupt enable */
730 uint64_t rpe : 1; /**< Remote pointer error */
731 uint64_t reserved_9_11 : 3;
732 uint64_t syn : 5; /**< Syndrome value (only valid when DBE or SBE is set) */
733 uint64_t dbe_ie : 1; /**< Double bit error interrupt enable */
734 uint64_t sbe_ie : 1; /**< Single bit error interrupt enable */
735 uint64_t dbe : 1; /**< Double bit error */
736 uint64_t sbe : 1; /**< Single bit error */
737 #else
738 uint64_t sbe : 1;
739 uint64_t dbe : 1;
740 uint64_t sbe_ie : 1;
741 uint64_t dbe_ie : 1;
742 uint64_t syn : 5;
743 uint64_t reserved_9_11 : 3;
744 uint64_t rpe : 1;
745 uint64_t rpe_ie : 1;
746 uint64_t reserved_14_15 : 2;
747 uint64_t iop : 13;
748 uint64_t reserved_29_31 : 3;
749 uint64_t iop_ie : 13;
750 uint64_t reserved_45_63 : 19;
751 #endif
752 } s;
753 struct cvmx_pow_ecc_err_s cn30xx;
754 struct cvmx_pow_ecc_err_cn31xx {
755 #ifdef __BIG_ENDIAN_BITFIELD
756 uint64_t reserved_14_63 : 50;
757 uint64_t rpe_ie : 1; /**< Remote pointer error interrupt enable */
758 uint64_t rpe : 1; /**< Remote pointer error */
759 uint64_t reserved_9_11 : 3;
760 uint64_t syn : 5; /**< Syndrome value (only valid when DBE or SBE is set) */
761 uint64_t dbe_ie : 1; /**< Double bit error interrupt enable */
762 uint64_t sbe_ie : 1; /**< Single bit error interrupt enable */
763 uint64_t dbe : 1; /**< Double bit error */
764 uint64_t sbe : 1; /**< Single bit error */
765 #else
766 uint64_t sbe : 1;
767 uint64_t dbe : 1;
768 uint64_t sbe_ie : 1;
769 uint64_t dbe_ie : 1;
770 uint64_t syn : 5;
771 uint64_t reserved_9_11 : 3;
772 uint64_t rpe : 1;
773 uint64_t rpe_ie : 1;
774 uint64_t reserved_14_63 : 50;
775 #endif
776 } cn31xx;
777 struct cvmx_pow_ecc_err_s cn38xx;
778 struct cvmx_pow_ecc_err_cn31xx cn38xxp2;
779 struct cvmx_pow_ecc_err_s cn50xx;
780 struct cvmx_pow_ecc_err_s cn52xx;
781 struct cvmx_pow_ecc_err_s cn52xxp1;
782 struct cvmx_pow_ecc_err_s cn56xx;
783 struct cvmx_pow_ecc_err_s cn56xxp1;
784 struct cvmx_pow_ecc_err_s cn58xx;
785 struct cvmx_pow_ecc_err_s cn58xxp1;
786 struct cvmx_pow_ecc_err_s cn61xx;
787 struct cvmx_pow_ecc_err_s cn63xx;
788 struct cvmx_pow_ecc_err_s cn63xxp1;
789 struct cvmx_pow_ecc_err_s cn66xx;
790 struct cvmx_pow_ecc_err_s cnf71xx;
791 };
792 typedef union cvmx_pow_ecc_err cvmx_pow_ecc_err_t;
793
794 /**
795 * cvmx_pow_int_ctl
796 *
797 * POW_INT_CTL = POW Internal Control Register
798 *
799 * Contains POW internal control values (for internal use, not typically for customer use):
800 *
801 * PFR_DIS = Disable high-performance pre-fetch reset mode.
802 *
803 * NBR_THR = Assert ncb__busy when the number of remaining coherent bus NBR credits equals is less
804 * than or equal to this value.
805 */
806 union cvmx_pow_int_ctl {
807 uint64_t u64;
808 struct cvmx_pow_int_ctl_s {
809 #ifdef __BIG_ENDIAN_BITFIELD
810 uint64_t reserved_6_63 : 58;
811 uint64_t pfr_dis : 1; /**< High-perf pre-fetch reset mode disable */
812 uint64_t nbr_thr : 5; /**< NBR busy threshold */
813 #else
814 uint64_t nbr_thr : 5;
815 uint64_t pfr_dis : 1;
816 uint64_t reserved_6_63 : 58;
817 #endif
818 } s;
819 struct cvmx_pow_int_ctl_s cn30xx;
820 struct cvmx_pow_int_ctl_s cn31xx;
821 struct cvmx_pow_int_ctl_s cn38xx;
822 struct cvmx_pow_int_ctl_s cn38xxp2;
823 struct cvmx_pow_int_ctl_s cn50xx;
824 struct cvmx_pow_int_ctl_s cn52xx;
825 struct cvmx_pow_int_ctl_s cn52xxp1;
826 struct cvmx_pow_int_ctl_s cn56xx;
827 struct cvmx_pow_int_ctl_s cn56xxp1;
828 struct cvmx_pow_int_ctl_s cn58xx;
829 struct cvmx_pow_int_ctl_s cn58xxp1;
830 struct cvmx_pow_int_ctl_s cn61xx;
831 struct cvmx_pow_int_ctl_s cn63xx;
832 struct cvmx_pow_int_ctl_s cn63xxp1;
833 struct cvmx_pow_int_ctl_s cn66xx;
834 struct cvmx_pow_int_ctl_s cnf71xx;
835 };
836 typedef union cvmx_pow_int_ctl cvmx_pow_int_ctl_t;
837
838 /**
839 * cvmx_pow_iq_cnt#
840 *
841 * POW_IQ_CNTX = POW Input Queue Count Register (1 per QOS level)
842 *
843 * Contains a read-only count of the number of work queue entries for each QOS level.
844 */
845 union cvmx_pow_iq_cntx {
846 uint64_t u64;
847 struct cvmx_pow_iq_cntx_s {
848 #ifdef __BIG_ENDIAN_BITFIELD
849 uint64_t reserved_32_63 : 32;
850 uint64_t iq_cnt : 32; /**< Input queue count for QOS level X */
851 #else
852 uint64_t iq_cnt : 32;
853 uint64_t reserved_32_63 : 32;
854 #endif
855 } s;
856 struct cvmx_pow_iq_cntx_s cn30xx;
857 struct cvmx_pow_iq_cntx_s cn31xx;
858 struct cvmx_pow_iq_cntx_s cn38xx;
859 struct cvmx_pow_iq_cntx_s cn38xxp2;
860 struct cvmx_pow_iq_cntx_s cn50xx;
861 struct cvmx_pow_iq_cntx_s cn52xx;
862 struct cvmx_pow_iq_cntx_s cn52xxp1;
863 struct cvmx_pow_iq_cntx_s cn56xx;
864 struct cvmx_pow_iq_cntx_s cn56xxp1;
865 struct cvmx_pow_iq_cntx_s cn58xx;
866 struct cvmx_pow_iq_cntx_s cn58xxp1;
867 struct cvmx_pow_iq_cntx_s cn61xx;
868 struct cvmx_pow_iq_cntx_s cn63xx;
869 struct cvmx_pow_iq_cntx_s cn63xxp1;
870 struct cvmx_pow_iq_cntx_s cn66xx;
871 struct cvmx_pow_iq_cntx_s cnf71xx;
872 };
873 typedef union cvmx_pow_iq_cntx cvmx_pow_iq_cntx_t;
874
875 /**
876 * cvmx_pow_iq_com_cnt
877 *
878 * POW_IQ_COM_CNT = POW Input Queue Combined Count Register
879 *
880 * Contains a read-only count of the total number of work queue entries in all QOS levels.
881 */
882 union cvmx_pow_iq_com_cnt {
883 uint64_t u64;
884 struct cvmx_pow_iq_com_cnt_s {
885 #ifdef __BIG_ENDIAN_BITFIELD
886 uint64_t reserved_32_63 : 32;
887 uint64_t iq_cnt : 32; /**< Input queue combined count */
888 #else
889 uint64_t iq_cnt : 32;
890 uint64_t reserved_32_63 : 32;
891 #endif
892 } s;
893 struct cvmx_pow_iq_com_cnt_s cn30xx;
894 struct cvmx_pow_iq_com_cnt_s cn31xx;
895 struct cvmx_pow_iq_com_cnt_s cn38xx;
896 struct cvmx_pow_iq_com_cnt_s cn38xxp2;
897 struct cvmx_pow_iq_com_cnt_s cn50xx;
898 struct cvmx_pow_iq_com_cnt_s cn52xx;
899 struct cvmx_pow_iq_com_cnt_s cn52xxp1;
900 struct cvmx_pow_iq_com_cnt_s cn56xx;
901 struct cvmx_pow_iq_com_cnt_s cn56xxp1;
902 struct cvmx_pow_iq_com_cnt_s cn58xx;
903 struct cvmx_pow_iq_com_cnt_s cn58xxp1;
904 struct cvmx_pow_iq_com_cnt_s cn61xx;
905 struct cvmx_pow_iq_com_cnt_s cn63xx;
906 struct cvmx_pow_iq_com_cnt_s cn63xxp1;
907 struct cvmx_pow_iq_com_cnt_s cn66xx;
908 struct cvmx_pow_iq_com_cnt_s cnf71xx;
909 };
910 typedef union cvmx_pow_iq_com_cnt cvmx_pow_iq_com_cnt_t;
911
912 /**
913 * cvmx_pow_iq_int
914 *
915 * POW_IQ_INT = POW Input Queue Interrupt Register
916 *
917 * Contains the bits (1 per QOS level) that can trigger the input queue interrupt. An IQ_INT bit
918 * will be set if POW_IQ_CNT#QOS# changes and the resulting value is equal to POW_IQ_THR#QOS#.
919 */
920 union cvmx_pow_iq_int {
921 uint64_t u64;
922 struct cvmx_pow_iq_int_s {
923 #ifdef __BIG_ENDIAN_BITFIELD
924 uint64_t reserved_8_63 : 56;
925 uint64_t iq_int : 8; /**< Input queue interrupt bits */
926 #else
927 uint64_t iq_int : 8;
928 uint64_t reserved_8_63 : 56;
929 #endif
930 } s;
931 struct cvmx_pow_iq_int_s cn52xx;
932 struct cvmx_pow_iq_int_s cn52xxp1;
933 struct cvmx_pow_iq_int_s cn56xx;
934 struct cvmx_pow_iq_int_s cn56xxp1;
935 struct cvmx_pow_iq_int_s cn61xx;
936 struct cvmx_pow_iq_int_s cn63xx;
937 struct cvmx_pow_iq_int_s cn63xxp1;
938 struct cvmx_pow_iq_int_s cn66xx;
939 struct cvmx_pow_iq_int_s cnf71xx;
940 };
941 typedef union cvmx_pow_iq_int cvmx_pow_iq_int_t;
942
943 /**
944 * cvmx_pow_iq_int_en
945 *
946 * POW_IQ_INT_EN = POW Input Queue Interrupt Enable Register
947 *
948 * Contains the bits (1 per QOS level) that enable the input queue interrupt.
949 */
950 union cvmx_pow_iq_int_en {
951 uint64_t u64;
952 struct cvmx_pow_iq_int_en_s {
953 #ifdef __BIG_ENDIAN_BITFIELD
954 uint64_t reserved_8_63 : 56;
955 uint64_t int_en : 8; /**< Input queue interrupt enable bits */
956 #else
957 uint64_t int_en : 8;
958 uint64_t reserved_8_63 : 56;
959 #endif
960 } s;
961 struct cvmx_pow_iq_int_en_s cn52xx;
962 struct cvmx_pow_iq_int_en_s cn52xxp1;
963 struct cvmx_pow_iq_int_en_s cn56xx;
964 struct cvmx_pow_iq_int_en_s cn56xxp1;
965 struct cvmx_pow_iq_int_en_s cn61xx;
966 struct cvmx_pow_iq_int_en_s cn63xx;
967 struct cvmx_pow_iq_int_en_s cn63xxp1;
968 struct cvmx_pow_iq_int_en_s cn66xx;
969 struct cvmx_pow_iq_int_en_s cnf71xx;
970 };
971 typedef union cvmx_pow_iq_int_en cvmx_pow_iq_int_en_t;
972
973 /**
974 * cvmx_pow_iq_thr#
975 *
976 * POW_IQ_THRX = POW Input Queue Threshold Register (1 per QOS level)
977 *
978 * Threshold value for triggering input queue interrupts.
979 */
980 union cvmx_pow_iq_thrx {
981 uint64_t u64;
982 struct cvmx_pow_iq_thrx_s {
983 #ifdef __BIG_ENDIAN_BITFIELD
984 uint64_t reserved_32_63 : 32;
985 uint64_t iq_thr : 32; /**< Input queue threshold for QOS level X */
986 #else
987 uint64_t iq_thr : 32;
988 uint64_t reserved_32_63 : 32;
989 #endif
990 } s;
991 struct cvmx_pow_iq_thrx_s cn52xx;
992 struct cvmx_pow_iq_thrx_s cn52xxp1;
993 struct cvmx_pow_iq_thrx_s cn56xx;
994 struct cvmx_pow_iq_thrx_s cn56xxp1;
995 struct cvmx_pow_iq_thrx_s cn61xx;
996 struct cvmx_pow_iq_thrx_s cn63xx;
997 struct cvmx_pow_iq_thrx_s cn63xxp1;
998 struct cvmx_pow_iq_thrx_s cn66xx;
999 struct cvmx_pow_iq_thrx_s cnf71xx;
1000 };
1001 typedef union cvmx_pow_iq_thrx cvmx_pow_iq_thrx_t;
1002
1003 /**
1004 * cvmx_pow_nos_cnt
1005 *
1006 * POW_NOS_CNT = POW No-schedule Count Register
1007 *
1008 * Contains the number of work queue entries on the no-schedule list.
1009 */
1010 union cvmx_pow_nos_cnt {
1011 uint64_t u64;
1012 struct cvmx_pow_nos_cnt_s {
1013 #ifdef __BIG_ENDIAN_BITFIELD
1014 uint64_t reserved_12_63 : 52;
1015 uint64_t nos_cnt : 12; /**< # of work queue entries on the no-schedule list */
1016 #else
1017 uint64_t nos_cnt : 12;
1018 uint64_t reserved_12_63 : 52;
1019 #endif
1020 } s;
1021 struct cvmx_pow_nos_cnt_cn30xx {
1022 #ifdef __BIG_ENDIAN_BITFIELD
1023 uint64_t reserved_7_63 : 57;
1024 uint64_t nos_cnt : 7; /**< # of work queue entries on the no-schedule list */
1025 #else
1026 uint64_t nos_cnt : 7;
1027 uint64_t reserved_7_63 : 57;
1028 #endif
1029 } cn30xx;
1030 struct cvmx_pow_nos_cnt_cn31xx {
1031 #ifdef __BIG_ENDIAN_BITFIELD
1032 uint64_t reserved_9_63 : 55;
1033 uint64_t nos_cnt : 9; /**< # of work queue entries on the no-schedule list */
1034 #else
1035 uint64_t nos_cnt : 9;
1036 uint64_t reserved_9_63 : 55;
1037 #endif
1038 } cn31xx;
1039 struct cvmx_pow_nos_cnt_s cn38xx;
1040 struct cvmx_pow_nos_cnt_s cn38xxp2;
1041 struct cvmx_pow_nos_cnt_cn31xx cn50xx;
1042 struct cvmx_pow_nos_cnt_cn52xx {
1043 #ifdef __BIG_ENDIAN_BITFIELD
1044 uint64_t reserved_10_63 : 54;
1045 uint64_t nos_cnt : 10; /**< # of work queue entries on the no-schedule list */
1046 #else
1047 uint64_t nos_cnt : 10;
1048 uint64_t reserved_10_63 : 54;
1049 #endif
1050 } cn52xx;
1051 struct cvmx_pow_nos_cnt_cn52xx cn52xxp1;
1052 struct cvmx_pow_nos_cnt_s cn56xx;
1053 struct cvmx_pow_nos_cnt_s cn56xxp1;
1054 struct cvmx_pow_nos_cnt_s cn58xx;
1055 struct cvmx_pow_nos_cnt_s cn58xxp1;
1056 struct cvmx_pow_nos_cnt_cn52xx cn61xx;
1057 struct cvmx_pow_nos_cnt_cn63xx {
1058 #ifdef __BIG_ENDIAN_BITFIELD
1059 uint64_t reserved_11_63 : 53;
1060 uint64_t nos_cnt : 11; /**< # of work queue entries on the no-schedule list */
1061 #else
1062 uint64_t nos_cnt : 11;
1063 uint64_t reserved_11_63 : 53;
1064 #endif
1065 } cn63xx;
1066 struct cvmx_pow_nos_cnt_cn63xx cn63xxp1;
1067 struct cvmx_pow_nos_cnt_cn63xx cn66xx;
1068 struct cvmx_pow_nos_cnt_cn52xx cnf71xx;
1069 };
1070 typedef union cvmx_pow_nos_cnt cvmx_pow_nos_cnt_t;
1071
1072 /**
1073 * cvmx_pow_nw_tim
1074 *
1075 * POW_NW_TIM = POW New Work Timer Period Register
1076 *
1077 * Sets the minimum period for a new work request timeout. Period is specified in n-1 notation
1078 * where the increment value is 1024 clock cycles. Thus, a value of 0x0 in this register translates
1079 * to 1024 cycles, 0x1 translates to 2048 cycles, 0x2 translates to 3072 cycles, etc... Note: the
1080 * maximum period for a new work request timeout is 2 times the minimum period. Note: the new work
1081 * request timeout counter is reset when this register is written.
1082 *
1083 * There are two new work request timeout cases:
1084 *
1085 * - WAIT bit clear. The new work request can timeout if the timer expires before the pre-fetch
1086 * engine has reached the end of all work queues. This can occur if the executable work queue
1087 * entry is deep in the queue and the pre-fetch engine is subject to many resets (i.e. high switch,
1088 * de-schedule, or new work load from other PP's). Thus, it is possible for a PP to receive a work
1089 * response with the NO_WORK bit set even though there was at least one executable entry in the
1090 * work queues. The other (and typical) scenario for receiving a NO_WORK response with the WAIT
1091 * bit clear is that the pre-fetch engine has reached the end of all work queues without finding
1092 * executable work.
1093 *
1094 * - WAIT bit set. The new work request can timeout if the timer expires before the pre-fetch
1095 * engine has found executable work. In this case, the only scenario where the PP will receive a
1096 * work response with the NO_WORK bit set is if the timer expires. Note: it is still possible for
1097 * a PP to receive a NO_WORK response even though there was at least one executable entry in the
1098 * work queues.
1099 *
1100 * In either case, it's important to note that switches and de-schedules are higher priority
1101 * operations that can cause the pre-fetch engine to reset. Thus in a system with many switches or
1102 * de-schedules occuring, it's possible for the new work timer to expire (resulting in NO_WORK
1103 * responses) before the pre-fetch engine is able to get very deep into the work queues.
1104 */
1105 union cvmx_pow_nw_tim {
1106 uint64_t u64;
1107 struct cvmx_pow_nw_tim_s {
1108 #ifdef __BIG_ENDIAN_BITFIELD
1109 uint64_t reserved_10_63 : 54;
1110 uint64_t nw_tim : 10; /**< New work timer period */
1111 #else
1112 uint64_t nw_tim : 10;
1113 uint64_t reserved_10_63 : 54;
1114 #endif
1115 } s;
1116 struct cvmx_pow_nw_tim_s cn30xx;
1117 struct cvmx_pow_nw_tim_s cn31xx;
1118 struct cvmx_pow_nw_tim_s cn38xx;
1119 struct cvmx_pow_nw_tim_s cn38xxp2;
1120 struct cvmx_pow_nw_tim_s cn50xx;
1121 struct cvmx_pow_nw_tim_s cn52xx;
1122 struct cvmx_pow_nw_tim_s cn52xxp1;
1123 struct cvmx_pow_nw_tim_s cn56xx;
1124 struct cvmx_pow_nw_tim_s cn56xxp1;
1125 struct cvmx_pow_nw_tim_s cn58xx;
1126 struct cvmx_pow_nw_tim_s cn58xxp1;
1127 struct cvmx_pow_nw_tim_s cn61xx;
1128 struct cvmx_pow_nw_tim_s cn63xx;
1129 struct cvmx_pow_nw_tim_s cn63xxp1;
1130 struct cvmx_pow_nw_tim_s cn66xx;
1131 struct cvmx_pow_nw_tim_s cnf71xx;
1132 };
1133 typedef union cvmx_pow_nw_tim cvmx_pow_nw_tim_t;
1134
1135 /**
1136 * cvmx_pow_pf_rst_msk
1137 *
1138 * POW_PF_RST_MSK = POW Prefetch Reset Mask
1139 *
1140 * Resets the work prefetch engine when work is stored in an internal buffer (either when the add
1141 * work arrives or when the work is reloaded from an external buffer) for an enabled QOS level
1142 * (1 bit per QOS level).
1143 */
1144 union cvmx_pow_pf_rst_msk {
1145 uint64_t u64;
1146 struct cvmx_pow_pf_rst_msk_s {
1147 #ifdef __BIG_ENDIAN_BITFIELD
1148 uint64_t reserved_8_63 : 56;
1149 uint64_t rst_msk : 8; /**< Prefetch engine reset mask */
1150 #else
1151 uint64_t rst_msk : 8;
1152 uint64_t reserved_8_63 : 56;
1153 #endif
1154 } s;
1155 struct cvmx_pow_pf_rst_msk_s cn50xx;
1156 struct cvmx_pow_pf_rst_msk_s cn52xx;
1157 struct cvmx_pow_pf_rst_msk_s cn52xxp1;
1158 struct cvmx_pow_pf_rst_msk_s cn56xx;
1159 struct cvmx_pow_pf_rst_msk_s cn56xxp1;
1160 struct cvmx_pow_pf_rst_msk_s cn58xx;
1161 struct cvmx_pow_pf_rst_msk_s cn58xxp1;
1162 struct cvmx_pow_pf_rst_msk_s cn61xx;
1163 struct cvmx_pow_pf_rst_msk_s cn63xx;
1164 struct cvmx_pow_pf_rst_msk_s cn63xxp1;
1165 struct cvmx_pow_pf_rst_msk_s cn66xx;
1166 struct cvmx_pow_pf_rst_msk_s cnf71xx;
1167 };
1168 typedef union cvmx_pow_pf_rst_msk cvmx_pow_pf_rst_msk_t;
1169
1170 /**
1171 * cvmx_pow_pp_grp_msk#
1172 *
1173 * POW_PP_GRP_MSKX = POW PP Group Mask Register (1 per PP)
1174 *
1175 * Selects which group(s) a PP belongs to. A '1' in any bit position sets the PP's membership in
1176 * the corresponding group. A value of 0x0 will prevent the PP from receiving new work. Note:
1177 * disabled or non-existent PP's should have this field set to 0xffff (the reset value) in order to
1178 * maximize POW performance.
1179 *
1180 * Also contains the QOS level priorities for each PP. 0x0 is highest priority, and 0x7 the lowest.
1181 * Setting the priority to 0xf will prevent that PP from receiving work from that QOS level.
1182 * Priority values 0x8 through 0xe are reserved and should not be used. For a given PP, priorities
1183 * should begin at 0x0 and remain contiguous throughout the range.
1184 */
1185 union cvmx_pow_pp_grp_mskx {
1186 uint64_t u64;
1187 struct cvmx_pow_pp_grp_mskx_s {
1188 #ifdef __BIG_ENDIAN_BITFIELD
1189 uint64_t reserved_48_63 : 16;
1190 uint64_t qos7_pri : 4; /**< PPX priority for QOS level 7 */
1191 uint64_t qos6_pri : 4; /**< PPX priority for QOS level 6 */
1192 uint64_t qos5_pri : 4; /**< PPX priority for QOS level 5 */
1193 uint64_t qos4_pri : 4; /**< PPX priority for QOS level 4 */
1194 uint64_t qos3_pri : 4; /**< PPX priority for QOS level 3 */
1195 uint64_t qos2_pri : 4; /**< PPX priority for QOS level 2 */
1196 uint64_t qos1_pri : 4; /**< PPX priority for QOS level 1 */
1197 uint64_t qos0_pri : 4; /**< PPX priority for QOS level 0 */
1198 uint64_t grp_msk : 16; /**< PPX group mask */
1199 #else
1200 uint64_t grp_msk : 16;
1201 uint64_t qos0_pri : 4;
1202 uint64_t qos1_pri : 4;
1203 uint64_t qos2_pri : 4;
1204 uint64_t qos3_pri : 4;
1205 uint64_t qos4_pri : 4;
1206 uint64_t qos5_pri : 4;
1207 uint64_t qos6_pri : 4;
1208 uint64_t qos7_pri : 4;
1209 uint64_t reserved_48_63 : 16;
1210 #endif
1211 } s;
1212 struct cvmx_pow_pp_grp_mskx_cn30xx {
1213 #ifdef __BIG_ENDIAN_BITFIELD
1214 uint64_t reserved_16_63 : 48;
1215 uint64_t grp_msk : 16; /**< PPX group mask */
1216 #else
1217 uint64_t grp_msk : 16;
1218 uint64_t reserved_16_63 : 48;
1219 #endif
1220 } cn30xx;
1221 struct cvmx_pow_pp_grp_mskx_cn30xx cn31xx;
1222 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xx;
1223 struct cvmx_pow_pp_grp_mskx_cn30xx cn38xxp2;
1224 struct cvmx_pow_pp_grp_mskx_s cn50xx;
1225 struct cvmx_pow_pp_grp_mskx_s cn52xx;
1226 struct cvmx_pow_pp_grp_mskx_s cn52xxp1;
1227 struct cvmx_pow_pp_grp_mskx_s cn56xx;
1228 struct cvmx_pow_pp_grp_mskx_s cn56xxp1;
1229 struct cvmx_pow_pp_grp_mskx_s cn58xx;
1230 struct cvmx_pow_pp_grp_mskx_s cn58xxp1;
1231 struct cvmx_pow_pp_grp_mskx_s cn61xx;
1232 struct cvmx_pow_pp_grp_mskx_s cn63xx;
1233 struct cvmx_pow_pp_grp_mskx_s cn63xxp1;
1234 struct cvmx_pow_pp_grp_mskx_s cn66xx;
1235 struct cvmx_pow_pp_grp_mskx_s cnf71xx;
1236 };
1237 typedef union cvmx_pow_pp_grp_mskx cvmx_pow_pp_grp_mskx_t;
1238
1239 /**
1240 * cvmx_pow_qos_rnd#
1241 *
1242 * POW_QOS_RNDX = POW QOS Issue Round Register (4 rounds per register x 8 registers = 32 rounds)
1243 *
1244 * Contains the round definitions for issuing new work. Each round consists of 8 bits with each bit
1245 * corresponding to a QOS level. There are 4 rounds contained in each register for a total of 32
1246 * rounds. The issue logic traverses through the rounds sequentially (lowest round to highest round)
1247 * in an attempt to find new work for each PP. Within each round, the issue logic traverses through
1248 * the QOS levels sequentially (highest QOS to lowest QOS) skipping over each QOS level with a clear
1249 * bit in the round mask. Note: setting a QOS level to all zeroes in all issue round registers will
1250 * prevent work from being issued from that QOS level.
1251 */
1252 union cvmx_pow_qos_rndx {
1253 uint64_t u64;
1254 struct cvmx_pow_qos_rndx_s {
1255 #ifdef __BIG_ENDIAN_BITFIELD
1256 uint64_t reserved_32_63 : 32;
1257 uint64_t rnd_p3 : 8; /**< Round mask for round Xx4+3 */
1258 uint64_t rnd_p2 : 8; /**< Round mask for round Xx4+2 */
1259 uint64_t rnd_p1 : 8; /**< Round mask for round Xx4+1 */
1260 uint64_t rnd : 8; /**< Round mask for round Xx4 */
1261 #else
1262 uint64_t rnd : 8;
1263 uint64_t rnd_p1 : 8;
1264 uint64_t rnd_p2 : 8;
1265 uint64_t rnd_p3 : 8;
1266 uint64_t reserved_32_63 : 32;
1267 #endif
1268 } s;
1269 struct cvmx_pow_qos_rndx_s cn30xx;
1270 struct cvmx_pow_qos_rndx_s cn31xx;
1271 struct cvmx_pow_qos_rndx_s cn38xx;
1272 struct cvmx_pow_qos_rndx_s cn38xxp2;
1273 struct cvmx_pow_qos_rndx_s cn50xx;
1274 struct cvmx_pow_qos_rndx_s cn52xx;
1275 struct cvmx_pow_qos_rndx_s cn52xxp1;
1276 struct cvmx_pow_qos_rndx_s cn56xx;
1277 struct cvmx_pow_qos_rndx_s cn56xxp1;
1278 struct cvmx_pow_qos_rndx_s cn58xx;
1279 struct cvmx_pow_qos_rndx_s cn58xxp1;
1280 struct cvmx_pow_qos_rndx_s cn61xx;
1281 struct cvmx_pow_qos_rndx_s cn63xx;
1282 struct cvmx_pow_qos_rndx_s cn63xxp1;
1283 struct cvmx_pow_qos_rndx_s cn66xx;
1284 struct cvmx_pow_qos_rndx_s cnf71xx;
1285 };
1286 typedef union cvmx_pow_qos_rndx cvmx_pow_qos_rndx_t;
1287
1288 /**
1289 * cvmx_pow_qos_thr#
1290 *
1291 * POW_QOS_THRX = POW QOS Threshold Register (1 per QOS level)
1292 *
1293 * Contains the thresholds for allocating POW internal storage buffers. If the number of remaining
1294 * free buffers drops below the minimum threshold (MIN_THR) or the number of allocated buffers for
1295 * this QOS level rises above the maximum threshold (MAX_THR), future incoming work queue entries
1296 * will be buffered externally rather than internally. This register also contains a read-only count
1297 * of the current number of free buffers (FREE_CNT), the number of internal buffers currently
1298 * allocated to this QOS level (BUF_CNT), and the total number of buffers on the de-schedule list
1299 * (DES_CNT) (which is not the same as the total number of de-scheduled buffers).
1300 */
1301 union cvmx_pow_qos_thrx {
1302 uint64_t u64;
1303 struct cvmx_pow_qos_thrx_s {
1304 #ifdef __BIG_ENDIAN_BITFIELD
1305 uint64_t reserved_60_63 : 4;
1306 uint64_t des_cnt : 12; /**< # of buffers on de-schedule list */
1307 uint64_t buf_cnt : 12; /**< # of internal buffers allocated to QOS level X */
1308 uint64_t free_cnt : 12; /**< # of total free buffers */
1309 uint64_t reserved_23_23 : 1;
1310 uint64_t max_thr : 11; /**< Max threshold for QOS level X */
1311 uint64_t reserved_11_11 : 1;
1312 uint64_t min_thr : 11; /**< Min threshold for QOS level X */
1313 #else
1314 uint64_t min_thr : 11;
1315 uint64_t reserved_11_11 : 1;
1316 uint64_t max_thr : 11;
1317 uint64_t reserved_23_23 : 1;
1318 uint64_t free_cnt : 12;
1319 uint64_t buf_cnt : 12;
1320 uint64_t des_cnt : 12;
1321 uint64_t reserved_60_63 : 4;
1322 #endif
1323 } s;
1324 struct cvmx_pow_qos_thrx_cn30xx {
1325 #ifdef __BIG_ENDIAN_BITFIELD
1326 uint64_t reserved_55_63 : 9;
1327 uint64_t des_cnt : 7; /**< # of buffers on de-schedule list */
1328 uint64_t reserved_43_47 : 5;
1329 uint64_t buf_cnt : 7; /**< # of internal buffers allocated to QOS level X */
1330 uint64_t reserved_31_35 : 5;
1331 uint64_t free_cnt : 7; /**< # of total free buffers */
1332 uint64_t reserved_18_23 : 6;
1333 uint64_t max_thr : 6; /**< Max threshold for QOS level X */
1334 uint64_t reserved_6_11 : 6;
1335 uint64_t min_thr : 6; /**< Min threshold for QOS level X */
1336 #else
1337 uint64_t min_thr : 6;
1338 uint64_t reserved_6_11 : 6;
1339 uint64_t max_thr : 6;
1340 uint64_t reserved_18_23 : 6;
1341 uint64_t free_cnt : 7;
1342 uint64_t reserved_31_35 : 5;
1343 uint64_t buf_cnt : 7;
1344 uint64_t reserved_43_47 : 5;
1345 uint64_t des_cnt : 7;
1346 uint64_t reserved_55_63 : 9;
1347 #endif
1348 } cn30xx;
1349 struct cvmx_pow_qos_thrx_cn31xx {
1350 #ifdef __BIG_ENDIAN_BITFIELD
1351 uint64_t reserved_57_63 : 7;
1352 uint64_t des_cnt : 9; /**< # of buffers on de-schedule list */
1353 uint64_t reserved_45_47 : 3;
1354 uint64_t buf_cnt : 9; /**< # of internal buffers allocated to QOS level X */
1355 uint64_t reserved_33_35 : 3;
1356 uint64_t free_cnt : 9; /**< # of total free buffers */
1357 uint64_t reserved_20_23 : 4;
1358 uint64_t max_thr : 8; /**< Max threshold for QOS level X */
1359 uint64_t reserved_8_11 : 4;
1360 uint64_t min_thr : 8; /**< Min threshold for QOS level X */
1361 #else
1362 uint64_t min_thr : 8;
1363 uint64_t reserved_8_11 : 4;
1364 uint64_t max_thr : 8;
1365 uint64_t reserved_20_23 : 4;
1366 uint64_t free_cnt : 9;
1367 uint64_t reserved_33_35 : 3;
1368 uint64_t buf_cnt : 9;
1369 uint64_t reserved_45_47 : 3;
1370 uint64_t des_cnt : 9;
1371 uint64_t reserved_57_63 : 7;
1372 #endif
1373 } cn31xx;
1374 struct cvmx_pow_qos_thrx_s cn38xx;
1375 struct cvmx_pow_qos_thrx_s cn38xxp2;
1376 struct cvmx_pow_qos_thrx_cn31xx cn50xx;
1377 struct cvmx_pow_qos_thrx_cn52xx {
1378 #ifdef __BIG_ENDIAN_BITFIELD
1379 uint64_t reserved_58_63 : 6;
1380 uint64_t des_cnt : 10; /**< # of buffers on de-schedule list */
1381 uint64_t reserved_46_47 : 2;
1382 uint64_t buf_cnt : 10; /**< # of internal buffers allocated to QOS level X */
1383 uint64_t reserved_34_35 : 2;
1384 uint64_t free_cnt : 10; /**< # of total free buffers */
1385 uint64_t reserved_21_23 : 3;
1386 uint64_t max_thr : 9; /**< Max threshold for QOS level X */
1387 uint64_t reserved_9_11 : 3;
1388 uint64_t min_thr : 9; /**< Min threshold for QOS level X */
1389 #else
1390 uint64_t min_thr : 9;
1391 uint64_t reserved_9_11 : 3;
1392 uint64_t max_thr : 9;
1393 uint64_t reserved_21_23 : 3;
1394 uint64_t free_cnt : 10;
1395 uint64_t reserved_34_35 : 2;
1396 uint64_t buf_cnt : 10;
1397 uint64_t reserved_46_47 : 2;
1398 uint64_t des_cnt : 10;
1399 uint64_t reserved_58_63 : 6;
1400 #endif
1401 } cn52xx;
1402 struct cvmx_pow_qos_thrx_cn52xx cn52xxp1;
1403 struct cvmx_pow_qos_thrx_s cn56xx;
1404 struct cvmx_pow_qos_thrx_s cn56xxp1;
1405 struct cvmx_pow_qos_thrx_s cn58xx;
1406 struct cvmx_pow_qos_thrx_s cn58xxp1;
1407 struct cvmx_pow_qos_thrx_cn52xx cn61xx;
1408 struct cvmx_pow_qos_thrx_cn63xx {
1409 #ifdef __BIG_ENDIAN_BITFIELD
1410 uint64_t reserved_59_63 : 5;
1411 uint64_t des_cnt : 11; /**< # of buffers on de-schedule list */
1412 uint64_t reserved_47_47 : 1;
1413 uint64_t buf_cnt : 11; /**< # of internal buffers allocated to QOS level X */
1414 uint64_t reserved_35_35 : 1;
1415 uint64_t free_cnt : 11; /**< # of total free buffers */
1416 uint64_t reserved_22_23 : 2;
1417 uint64_t max_thr : 10; /**< Max threshold for QOS level X */
1418 uint64_t reserved_10_11 : 2;
1419 uint64_t min_thr : 10; /**< Min threshold for QOS level X */
1420 #else
1421 uint64_t min_thr : 10;
1422 uint64_t reserved_10_11 : 2;
1423 uint64_t max_thr : 10;
1424 uint64_t reserved_22_23 : 2;
1425 uint64_t free_cnt : 11;
1426 uint64_t reserved_35_35 : 1;
1427 uint64_t buf_cnt : 11;
1428 uint64_t reserved_47_47 : 1;
1429 uint64_t des_cnt : 11;
1430 uint64_t reserved_59_63 : 5;
1431 #endif
1432 } cn63xx;
1433 struct cvmx_pow_qos_thrx_cn63xx cn63xxp1;
1434 struct cvmx_pow_qos_thrx_cn63xx cn66xx;
1435 struct cvmx_pow_qos_thrx_cn52xx cnf71xx;
1436 };
1437 typedef union cvmx_pow_qos_thrx cvmx_pow_qos_thrx_t;
1438
1439 /**
1440 * cvmx_pow_ts_pc
1441 *
1442 * POW_TS_PC = POW Tag Switch Performance Counter
1443 *
1444 * Counts the number of tag switch requests. Write to clear.
1445 */
1446 union cvmx_pow_ts_pc {
1447 uint64_t u64;
1448 struct cvmx_pow_ts_pc_s {
1449 #ifdef __BIG_ENDIAN_BITFIELD
1450 uint64_t reserved_32_63 : 32;
1451 uint64_t ts_pc : 32; /**< Tag switch performance counter */
1452 #else
1453 uint64_t ts_pc : 32;
1454 uint64_t reserved_32_63 : 32;
1455 #endif
1456 } s;
1457 struct cvmx_pow_ts_pc_s cn30xx;
1458 struct cvmx_pow_ts_pc_s cn31xx;
1459 struct cvmx_pow_ts_pc_s cn38xx;
1460 struct cvmx_pow_ts_pc_s cn38xxp2;
1461 struct cvmx_pow_ts_pc_s cn50xx;
1462 struct cvmx_pow_ts_pc_s cn52xx;
1463 struct cvmx_pow_ts_pc_s cn52xxp1;
1464 struct cvmx_pow_ts_pc_s cn56xx;
1465 struct cvmx_pow_ts_pc_s cn56xxp1;
1466 struct cvmx_pow_ts_pc_s cn58xx;
1467 struct cvmx_pow_ts_pc_s cn58xxp1;
1468 struct cvmx_pow_ts_pc_s cn61xx;
1469 struct cvmx_pow_ts_pc_s cn63xx;
1470 struct cvmx_pow_ts_pc_s cn63xxp1;
1471 struct cvmx_pow_ts_pc_s cn66xx;
1472 struct cvmx_pow_ts_pc_s cnf71xx;
1473 };
1474 typedef union cvmx_pow_ts_pc cvmx_pow_ts_pc_t;
1475
1476 /**
1477 * cvmx_pow_wa_com_pc
1478 *
1479 * POW_WA_COM_PC = POW Work Add Combined Performance Counter
1480 *
1481 * Counts the number of add new work requests for all QOS levels. Write to clear.
1482 */
1483 union cvmx_pow_wa_com_pc {
1484 uint64_t u64;
1485 struct cvmx_pow_wa_com_pc_s {
1486 #ifdef __BIG_ENDIAN_BITFIELD
1487 uint64_t reserved_32_63 : 32;
1488 uint64_t wa_pc : 32; /**< Work add combined performance counter */
1489 #else
1490 uint64_t wa_pc : 32;
1491 uint64_t reserved_32_63 : 32;
1492 #endif
1493 } s;
1494 struct cvmx_pow_wa_com_pc_s cn30xx;
1495 struct cvmx_pow_wa_com_pc_s cn31xx;
1496 struct cvmx_pow_wa_com_pc_s cn38xx;
1497 struct cvmx_pow_wa_com_pc_s cn38xxp2;
1498 struct cvmx_pow_wa_com_pc_s cn50xx;
1499 struct cvmx_pow_wa_com_pc_s cn52xx;
1500 struct cvmx_pow_wa_com_pc_s cn52xxp1;
1501 struct cvmx_pow_wa_com_pc_s cn56xx;
1502 struct cvmx_pow_wa_com_pc_s cn56xxp1;
1503 struct cvmx_pow_wa_com_pc_s cn58xx;
1504 struct cvmx_pow_wa_com_pc_s cn58xxp1;
1505 struct cvmx_pow_wa_com_pc_s cn61xx;
1506 struct cvmx_pow_wa_com_pc_s cn63xx;
1507 struct cvmx_pow_wa_com_pc_s cn63xxp1;
1508 struct cvmx_pow_wa_com_pc_s cn66xx;
1509 struct cvmx_pow_wa_com_pc_s cnf71xx;
1510 };
1511 typedef union cvmx_pow_wa_com_pc cvmx_pow_wa_com_pc_t;
1512
1513 /**
1514 * cvmx_pow_wa_pc#
1515 *
1516 * POW_WA_PCX = POW Work Add Performance Counter (1 per QOS level)
1517 *
1518 * Counts the number of add new work requests for each QOS level. Write to clear.
1519 */
1520 union cvmx_pow_wa_pcx {
1521 uint64_t u64;
1522 struct cvmx_pow_wa_pcx_s {
1523 #ifdef __BIG_ENDIAN_BITFIELD
1524 uint64_t reserved_32_63 : 32;
1525 uint64_t wa_pc : 32; /**< Work add performance counter for QOS level X */
1526 #else
1527 uint64_t wa_pc : 32;
1528 uint64_t reserved_32_63 : 32;
1529 #endif
1530 } s;
1531 struct cvmx_pow_wa_pcx_s cn30xx;
1532 struct cvmx_pow_wa_pcx_s cn31xx;
1533 struct cvmx_pow_wa_pcx_s cn38xx;
1534 struct cvmx_pow_wa_pcx_s cn38xxp2;
1535 struct cvmx_pow_wa_pcx_s cn50xx;
1536 struct cvmx_pow_wa_pcx_s cn52xx;
1537 struct cvmx_pow_wa_pcx_s cn52xxp1;
1538 struct cvmx_pow_wa_pcx_s cn56xx;
1539 struct cvmx_pow_wa_pcx_s cn56xxp1;
1540 struct cvmx_pow_wa_pcx_s cn58xx;
1541 struct cvmx_pow_wa_pcx_s cn58xxp1;
1542 struct cvmx_pow_wa_pcx_s cn61xx;
1543 struct cvmx_pow_wa_pcx_s cn63xx;
1544 struct cvmx_pow_wa_pcx_s cn63xxp1;
1545 struct cvmx_pow_wa_pcx_s cn66xx;
1546 struct cvmx_pow_wa_pcx_s cnf71xx;
1547 };
1548 typedef union cvmx_pow_wa_pcx cvmx_pow_wa_pcx_t;
1549
1550 /**
1551 * cvmx_pow_wq_int
1552 *
1553 * POW_WQ_INT = POW Work Queue Interrupt Register
1554 *
1555 * Contains the bits (1 per group) that set work queue interrupts and are used to clear these
1556 * interrupts. Also contains the input queue interrupt temporary disable bits (1 per group). For
1557 * more information regarding this register, see the interrupt section.
1558 */
1559 union cvmx_pow_wq_int {
1560 uint64_t u64;
1561 struct cvmx_pow_wq_int_s {
1562 #ifdef __BIG_ENDIAN_BITFIELD
1563 uint64_t reserved_32_63 : 32;
1564 uint64_t iq_dis : 16; /**< Input queue interrupt temporary disable mask
1565 Corresponding WQ_INT<*> bit cannot be set due to
1566 IQ_CNT/IQ_THR check when this bit is set.
1567 Corresponding IQ_DIS bit is cleared by HW whenever:
1568 - POW_WQ_INT_CNT*[IQ_CNT] is zero, or
1569 - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic
1570 counter POW_WQ_INT_PC[PC]==0 */
1571 uint64_t wq_int : 16; /**< Work queue interrupt bits
1572 Corresponding WQ_INT bit is set by HW whenever:
1573 - POW_WQ_INT_CNT*[IQ_CNT] >=
1574 POW_WQ_INT_THR*[IQ_THR] and the threshold
1575 interrupt is not disabled.
1576 IQ_DIS<*>==1 disables the interrupt.
1577 POW_WQ_INT_THR*[IQ_THR]==0 disables the int.
1578 - POW_WQ_INT_CNT*[DS_CNT] >=
1579 POW_WQ_INT_THR*[DS_THR] and the threshold
1580 interrupt is not disabled
1581 POW_WQ_INT_THR*[DS_THR]==0 disables the int.
1582 - POW_WQ_INT_CNT*[TC_CNT]==1 when periodic
1583 counter POW_WQ_INT_PC[PC]==0 and
1584 POW_WQ_INT_THR*[TC_EN]==1 and at least one of:
1585 - POW_WQ_INT_CNT*[IQ_CNT] > 0
1586 - POW_WQ_INT_CNT*[DS_CNT] > 0 */
1587 #else
1588 uint64_t wq_int : 16;
1589 uint64_t iq_dis : 16;
1590 uint64_t reserved_32_63 : 32;
1591 #endif
1592 } s;
1593 struct cvmx_pow_wq_int_s cn30xx;
1594 struct cvmx_pow_wq_int_s cn31xx;
1595 struct cvmx_pow_wq_int_s cn38xx;
1596 struct cvmx_pow_wq_int_s cn38xxp2;
1597 struct cvmx_pow_wq_int_s cn50xx;
1598 struct cvmx_pow_wq_int_s cn52xx;
1599 struct cvmx_pow_wq_int_s cn52xxp1;
1600 struct cvmx_pow_wq_int_s cn56xx;
1601 struct cvmx_pow_wq_int_s cn56xxp1;
1602 struct cvmx_pow_wq_int_s cn58xx;
1603 struct cvmx_pow_wq_int_s cn58xxp1;
1604 struct cvmx_pow_wq_int_s cn61xx;
1605 struct cvmx_pow_wq_int_s cn63xx;
1606 struct cvmx_pow_wq_int_s cn63xxp1;
1607 struct cvmx_pow_wq_int_s cn66xx;
1608 struct cvmx_pow_wq_int_s cnf71xx;
1609 };
1610 typedef union cvmx_pow_wq_int cvmx_pow_wq_int_t;
1611
1612 /**
1613 * cvmx_pow_wq_int_cnt#
1614 *
1615 * POW_WQ_INT_CNTX = POW Work Queue Interrupt Count Register (1 per group)
1616 *
1617 * Contains a read-only copy of the counts used to trigger work queue interrupts. For more
1618 * information regarding this register, see the interrupt section.
1619 */
1620 union cvmx_pow_wq_int_cntx {
1621 uint64_t u64;
1622 struct cvmx_pow_wq_int_cntx_s {
1623 #ifdef __BIG_ENDIAN_BITFIELD
1624 uint64_t reserved_28_63 : 36;
1625 uint64_t tc_cnt : 4; /**< Time counter current value for group X
1626 HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
1627 - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
1628 corresponding POW_WQ_INT_CNT*[DS_CNT]==0
1629 - corresponding POW_WQ_INT[WQ_INT<*>] is written
1630 with a 1 by SW
1631 - corresponding POW_WQ_INT[IQ_DIS<*>] is written
1632 with a 1 by SW
1633 - corresponding POW_WQ_INT_THR* is written by SW
1634 - TC_CNT==1 and periodic counter
1635 POW_WQ_INT_PC[PC]==0
1636 Otherwise, HW decrements TC_CNT whenever the
1637 periodic counter POW_WQ_INT_PC[PC]==0.
1638 TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
1639 uint64_t ds_cnt : 12; /**< De-schedule executable count for group X */
1640 uint64_t iq_cnt : 12; /**< Input queue executable count for group X */
1641 #else
1642 uint64_t iq_cnt : 12;
1643 uint64_t ds_cnt : 12;
1644 uint64_t tc_cnt : 4;
1645 uint64_t reserved_28_63 : 36;
1646 #endif
1647 } s;
1648 struct cvmx_pow_wq_int_cntx_cn30xx {
1649 #ifdef __BIG_ENDIAN_BITFIELD
1650 uint64_t reserved_28_63 : 36;
1651 uint64_t tc_cnt : 4; /**< Time counter current value for group X
1652 HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
1653 - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
1654 corresponding POW_WQ_INT_CNT*[DS_CNT]==0
1655 - corresponding POW_WQ_INT[WQ_INT<*>] is written
1656 with a 1 by SW
1657 - corresponding POW_WQ_INT[IQ_DIS<*>] is written
1658 with a 1 by SW
1659 - corresponding POW_WQ_INT_THR* is written by SW
1660 - TC_CNT==1 and periodic counter
1661 POW_WQ_INT_PC[PC]==0
1662 Otherwise, HW decrements TC_CNT whenever the
1663 periodic counter POW_WQ_INT_PC[PC]==0.
1664 TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
1665 uint64_t reserved_19_23 : 5;
1666 uint64_t ds_cnt : 7; /**< De-schedule executable count for group X */
1667 uint64_t reserved_7_11 : 5;
1668 uint64_t iq_cnt : 7; /**< Input queue executable count for group X */
1669 #else
1670 uint64_t iq_cnt : 7;
1671 uint64_t reserved_7_11 : 5;
1672 uint64_t ds_cnt : 7;
1673 uint64_t reserved_19_23 : 5;
1674 uint64_t tc_cnt : 4;
1675 uint64_t reserved_28_63 : 36;
1676 #endif
1677 } cn30xx;
1678 struct cvmx_pow_wq_int_cntx_cn31xx {
1679 #ifdef __BIG_ENDIAN_BITFIELD
1680 uint64_t reserved_28_63 : 36;
1681 uint64_t tc_cnt : 4; /**< Time counter current value for group X
1682 HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
1683 - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
1684 corresponding POW_WQ_INT_CNT*[DS_CNT]==0
1685 - corresponding POW_WQ_INT[WQ_INT<*>] is written
1686 with a 1 by SW
1687 - corresponding POW_WQ_INT[IQ_DIS<*>] is written
1688 with a 1 by SW
1689 - corresponding POW_WQ_INT_THR* is written by SW
1690 - TC_CNT==1 and periodic counter
1691 POW_WQ_INT_PC[PC]==0
1692 Otherwise, HW decrements TC_CNT whenever the
1693 periodic counter POW_WQ_INT_PC[PC]==0.
1694 TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
1695 uint64_t reserved_21_23 : 3;
1696 uint64_t ds_cnt : 9; /**< De-schedule executable count for group X */
1697 uint64_t reserved_9_11 : 3;
1698 uint64_t iq_cnt : 9; /**< Input queue executable count for group X */
1699 #else
1700 uint64_t iq_cnt : 9;
1701 uint64_t reserved_9_11 : 3;
1702 uint64_t ds_cnt : 9;
1703 uint64_t reserved_21_23 : 3;
1704 uint64_t tc_cnt : 4;
1705 uint64_t reserved_28_63 : 36;
1706 #endif
1707 } cn31xx;
1708 struct cvmx_pow_wq_int_cntx_s cn38xx;
1709 struct cvmx_pow_wq_int_cntx_s cn38xxp2;
1710 struct cvmx_pow_wq_int_cntx_cn31xx cn50xx;
1711 struct cvmx_pow_wq_int_cntx_cn52xx {
1712 #ifdef __BIG_ENDIAN_BITFIELD
1713 uint64_t reserved_28_63 : 36;
1714 uint64_t tc_cnt : 4; /**< Time counter current value for group X
1715 HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
1716 - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
1717 corresponding POW_WQ_INT_CNT*[DS_CNT]==0
1718 - corresponding POW_WQ_INT[WQ_INT<*>] is written
1719 with a 1 by SW
1720 - corresponding POW_WQ_INT[IQ_DIS<*>] is written
1721 with a 1 by SW
1722 - corresponding POW_WQ_INT_THR* is written by SW
1723 - TC_CNT==1 and periodic counter
1724 POW_WQ_INT_PC[PC]==0
1725 Otherwise, HW decrements TC_CNT whenever the
1726 periodic counter POW_WQ_INT_PC[PC]==0.
1727 TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
1728 uint64_t reserved_22_23 : 2;
1729 uint64_t ds_cnt : 10; /**< De-schedule executable count for group X */
1730 uint64_t reserved_10_11 : 2;
1731 uint64_t iq_cnt : 10; /**< Input queue executable count for group X */
1732 #else
1733 uint64_t iq_cnt : 10;
1734 uint64_t reserved_10_11 : 2;
1735 uint64_t ds_cnt : 10;
1736 uint64_t reserved_22_23 : 2;
1737 uint64_t tc_cnt : 4;
1738 uint64_t reserved_28_63 : 36;
1739 #endif
1740 } cn52xx;
1741 struct cvmx_pow_wq_int_cntx_cn52xx cn52xxp1;
1742 struct cvmx_pow_wq_int_cntx_s cn56xx;
1743 struct cvmx_pow_wq_int_cntx_s cn56xxp1;
1744 struct cvmx_pow_wq_int_cntx_s cn58xx;
1745 struct cvmx_pow_wq_int_cntx_s cn58xxp1;
1746 struct cvmx_pow_wq_int_cntx_cn52xx cn61xx;
1747 struct cvmx_pow_wq_int_cntx_cn63xx {
1748 #ifdef __BIG_ENDIAN_BITFIELD
1749 uint64_t reserved_28_63 : 36;
1750 uint64_t tc_cnt : 4; /**< Time counter current value for group X
1751 HW sets TC_CNT to POW_WQ_INT_THR*[TC_THR] whenever:
1752 - corresponding POW_WQ_INT_CNT*[IQ_CNT]==0 and
1753 corresponding POW_WQ_INT_CNT*[DS_CNT]==0
1754 - corresponding POW_WQ_INT[WQ_INT<*>] is written
1755 with a 1 by SW
1756 - corresponding POW_WQ_INT[IQ_DIS<*>] is written
1757 with a 1 by SW
1758 - corresponding POW_WQ_INT_THR* is written by SW
1759 - TC_CNT==1 and periodic counter
1760 POW_WQ_INT_PC[PC]==0
1761 Otherwise, HW decrements TC_CNT whenever the
1762 periodic counter POW_WQ_INT_PC[PC]==0.
1763 TC_CNT is 0 whenever POW_WQ_INT_THR*[TC_THR]==0. */
1764 uint64_t reserved_23_23 : 1;
1765 uint64_t ds_cnt : 11; /**< De-schedule executable count for group X */
1766 uint64_t reserved_11_11 : 1;
1767 uint64_t iq_cnt : 11; /**< Input queue executable count for group X */
1768 #else
1769 uint64_t iq_cnt : 11;
1770 uint64_t reserved_11_11 : 1;
1771 uint64_t ds_cnt : 11;
1772 uint64_t reserved_23_23 : 1;
1773 uint64_t tc_cnt : 4;
1774 uint64_t reserved_28_63 : 36;
1775 #endif
1776 } cn63xx;
1777 struct cvmx_pow_wq_int_cntx_cn63xx cn63xxp1;
1778 struct cvmx_pow_wq_int_cntx_cn63xx cn66xx;
1779 struct cvmx_pow_wq_int_cntx_cn52xx cnf71xx;
1780 };
1781 typedef union cvmx_pow_wq_int_cntx cvmx_pow_wq_int_cntx_t;
1782
1783 /**
1784 * cvmx_pow_wq_int_pc
1785 *
1786 * POW_WQ_INT_PC = POW Work Queue Interrupt Periodic Counter Register
1787 *
1788 * Contains the threshold value for the work queue interrupt periodic counter and also a read-only
1789 * copy of the periodic counter. For more information regarding this register, see the interrupt
1790 * section.
1791 */
1792 union cvmx_pow_wq_int_pc {
1793 uint64_t u64;
1794 struct cvmx_pow_wq_int_pc_s {
1795 #ifdef __BIG_ENDIAN_BITFIELD
1796 uint64_t reserved_60_63 : 4;
1797 uint64_t pc : 28; /**< Work queue interrupt periodic counter */
1798 uint64_t reserved_28_31 : 4;
1799 uint64_t pc_thr : 20; /**< Work queue interrupt periodic counter threshold */
1800 uint64_t reserved_0_7 : 8;
1801 #else
1802 uint64_t reserved_0_7 : 8;
1803 uint64_t pc_thr : 20;
1804 uint64_t reserved_28_31 : 4;
1805 uint64_t pc : 28;
1806 uint64_t reserved_60_63 : 4;
1807 #endif
1808 } s;
1809 struct cvmx_pow_wq_int_pc_s cn30xx;
1810 struct cvmx_pow_wq_int_pc_s cn31xx;
1811 struct cvmx_pow_wq_int_pc_s cn38xx;
1812 struct cvmx_pow_wq_int_pc_s cn38xxp2;
1813 struct cvmx_pow_wq_int_pc_s cn50xx;
1814 struct cvmx_pow_wq_int_pc_s cn52xx;
1815 struct cvmx_pow_wq_int_pc_s cn52xxp1;
1816 struct cvmx_pow_wq_int_pc_s cn56xx;
1817 struct cvmx_pow_wq_int_pc_s cn56xxp1;
1818 struct cvmx_pow_wq_int_pc_s cn58xx;
1819 struct cvmx_pow_wq_int_pc_s cn58xxp1;
1820 struct cvmx_pow_wq_int_pc_s cn61xx;
1821 struct cvmx_pow_wq_int_pc_s cn63xx;
1822 struct cvmx_pow_wq_int_pc_s cn63xxp1;
1823 struct cvmx_pow_wq_int_pc_s cn66xx;
1824 struct cvmx_pow_wq_int_pc_s cnf71xx;
1825 };
1826 typedef union cvmx_pow_wq_int_pc cvmx_pow_wq_int_pc_t;
1827
1828 /**
1829 * cvmx_pow_wq_int_thr#
1830 *
1831 * POW_WQ_INT_THRX = POW Work Queue Interrupt Threshold Register (1 per group)
1832 *
1833 * Contains the thresholds for enabling and setting work queue interrupts. For more information
1834 * regarding this register, see the interrupt section.
1835 *
1836 * Note: Up to 4 of the POW's internal storage buffers can be allocated for hardware use and are
1837 * therefore not available for incoming work queue entries. Additionally, any PP that is not in the
1838 * NULL_NULL state consumes a buffer. Thus in a 4 PP system, it is not advisable to set either
1839 * IQ_THR or DS_THR to greater than 512 - 4 - 4 = 504. Doing so may prevent the interrupt from
1840 * ever triggering.
1841 */
1842 union cvmx_pow_wq_int_thrx {
1843 uint64_t u64;
1844 struct cvmx_pow_wq_int_thrx_s {
1845 #ifdef __BIG_ENDIAN_BITFIELD
1846 uint64_t reserved_29_63 : 35;
1847 uint64_t tc_en : 1; /**< Time counter interrupt enable for group X
1848 TC_EN must be zero when TC_THR==0 */
1849 uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X
1850 When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
1851 uint64_t reserved_23_23 : 1;
1852 uint64_t ds_thr : 11; /**< De-schedule count threshold for group X
1853 DS_THR==0 disables the threshold interrupt */
1854 uint64_t reserved_11_11 : 1;
1855 uint64_t iq_thr : 11; /**< Input queue count threshold for group X
1856 IQ_THR==0 disables the threshold interrupt */
1857 #else
1858 uint64_t iq_thr : 11;
1859 uint64_t reserved_11_11 : 1;
1860 uint64_t ds_thr : 11;
1861 uint64_t reserved_23_23 : 1;
1862 uint64_t tc_thr : 4;
1863 uint64_t tc_en : 1;
1864 uint64_t reserved_29_63 : 35;
1865 #endif
1866 } s;
1867 struct cvmx_pow_wq_int_thrx_cn30xx {
1868 #ifdef __BIG_ENDIAN_BITFIELD
1869 uint64_t reserved_29_63 : 35;
1870 uint64_t tc_en : 1; /**< Time counter interrupt enable for group X
1871 TC_EN must be zero when TC_THR==0 */
1872 uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X
1873 When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
1874 uint64_t reserved_18_23 : 6;
1875 uint64_t ds_thr : 6; /**< De-schedule count threshold for group X
1876 DS_THR==0 disables the threshold interrupt */
1877 uint64_t reserved_6_11 : 6;
1878 uint64_t iq_thr : 6; /**< Input queue count threshold for group X
1879 IQ_THR==0 disables the threshold interrupt */
1880 #else
1881 uint64_t iq_thr : 6;
1882 uint64_t reserved_6_11 : 6;
1883 uint64_t ds_thr : 6;
1884 uint64_t reserved_18_23 : 6;
1885 uint64_t tc_thr : 4;
1886 uint64_t tc_en : 1;
1887 uint64_t reserved_29_63 : 35;
1888 #endif
1889 } cn30xx;
1890 struct cvmx_pow_wq_int_thrx_cn31xx {
1891 #ifdef __BIG_ENDIAN_BITFIELD
1892 uint64_t reserved_29_63 : 35;
1893 uint64_t tc_en : 1; /**< Time counter interrupt enable for group X
1894 TC_EN must be zero when TC_THR==0 */
1895 uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X
1896 When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
1897 uint64_t reserved_20_23 : 4;
1898 uint64_t ds_thr : 8; /**< De-schedule count threshold for group X
1899 DS_THR==0 disables the threshold interrupt */
1900 uint64_t reserved_8_11 : 4;
1901 uint64_t iq_thr : 8; /**< Input queue count threshold for group X
1902 IQ_THR==0 disables the threshold interrupt */
1903 #else
1904 uint64_t iq_thr : 8;
1905 uint64_t reserved_8_11 : 4;
1906 uint64_t ds_thr : 8;
1907 uint64_t reserved_20_23 : 4;
1908 uint64_t tc_thr : 4;
1909 uint64_t tc_en : 1;
1910 uint64_t reserved_29_63 : 35;
1911 #endif
1912 } cn31xx;
1913 struct cvmx_pow_wq_int_thrx_s cn38xx;
1914 struct cvmx_pow_wq_int_thrx_s cn38xxp2;
1915 struct cvmx_pow_wq_int_thrx_cn31xx cn50xx;
1916 struct cvmx_pow_wq_int_thrx_cn52xx {
1917 #ifdef __BIG_ENDIAN_BITFIELD
1918 uint64_t reserved_29_63 : 35;
1919 uint64_t tc_en : 1; /**< Time counter interrupt enable for group X
1920 TC_EN must be zero when TC_THR==0 */
1921 uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X
1922 When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
1923 uint64_t reserved_21_23 : 3;
1924 uint64_t ds_thr : 9; /**< De-schedule count threshold for group X
1925 DS_THR==0 disables the threshold interrupt */
1926 uint64_t reserved_9_11 : 3;
1927 uint64_t iq_thr : 9; /**< Input queue count threshold for group X
1928 IQ_THR==0 disables the threshold interrupt */
1929 #else
1930 uint64_t iq_thr : 9;
1931 uint64_t reserved_9_11 : 3;
1932 uint64_t ds_thr : 9;
1933 uint64_t reserved_21_23 : 3;
1934 uint64_t tc_thr : 4;
1935 uint64_t tc_en : 1;
1936 uint64_t reserved_29_63 : 35;
1937 #endif
1938 } cn52xx;
1939 struct cvmx_pow_wq_int_thrx_cn52xx cn52xxp1;
1940 struct cvmx_pow_wq_int_thrx_s cn56xx;
1941 struct cvmx_pow_wq_int_thrx_s cn56xxp1;
1942 struct cvmx_pow_wq_int_thrx_s cn58xx;
1943 struct cvmx_pow_wq_int_thrx_s cn58xxp1;
1944 struct cvmx_pow_wq_int_thrx_cn52xx cn61xx;
1945 struct cvmx_pow_wq_int_thrx_cn63xx {
1946 #ifdef __BIG_ENDIAN_BITFIELD
1947 uint64_t reserved_29_63 : 35;
1948 uint64_t tc_en : 1; /**< Time counter interrupt enable for group X
1949 TC_EN must be zero when TC_THR==0 */
1950 uint64_t tc_thr : 4; /**< Time counter interrupt threshold for group X
1951 When TC_THR==0, POW_WQ_INT_CNT*[TC_CNT] is zero */
1952 uint64_t reserved_22_23 : 2;
1953 uint64_t ds_thr : 10; /**< De-schedule count threshold for group X
1954 DS_THR==0 disables the threshold interrupt */
1955 uint64_t reserved_10_11 : 2;
1956 uint64_t iq_thr : 10; /**< Input queue count threshold for group X
1957 IQ_THR==0 disables the threshold interrupt */
1958 #else
1959 uint64_t iq_thr : 10;
1960 uint64_t reserved_10_11 : 2;
1961 uint64_t ds_thr : 10;
1962 uint64_t reserved_22_23 : 2;
1963 uint64_t tc_thr : 4;
1964 uint64_t tc_en : 1;
1965 uint64_t reserved_29_63 : 35;
1966 #endif
1967 } cn63xx;
1968 struct cvmx_pow_wq_int_thrx_cn63xx cn63xxp1;
1969 struct cvmx_pow_wq_int_thrx_cn63xx cn66xx;
1970 struct cvmx_pow_wq_int_thrx_cn52xx cnf71xx;
1971 };
1972 typedef union cvmx_pow_wq_int_thrx cvmx_pow_wq_int_thrx_t;
1973
1974 /**
1975 * cvmx_pow_ws_pc#
1976 *
1977 * POW_WS_PCX = POW Work Schedule Performance Counter (1 per group)
1978 *
1979 * Counts the number of work schedules for each group. Write to clear.
1980 */
1981 union cvmx_pow_ws_pcx {
1982 uint64_t u64;
1983 struct cvmx_pow_ws_pcx_s {
1984 #ifdef __BIG_ENDIAN_BITFIELD
1985 uint64_t reserved_32_63 : 32;
1986 uint64_t ws_pc : 32; /**< Work schedule performance counter for group X */
1987 #else
1988 uint64_t ws_pc : 32;
1989 uint64_t reserved_32_63 : 32;
1990 #endif
1991 } s;
1992 struct cvmx_pow_ws_pcx_s cn30xx;
1993 struct cvmx_pow_ws_pcx_s cn31xx;
1994 struct cvmx_pow_ws_pcx_s cn38xx;
1995 struct cvmx_pow_ws_pcx_s cn38xxp2;
1996 struct cvmx_pow_ws_pcx_s cn50xx;
1997 struct cvmx_pow_ws_pcx_s cn52xx;
1998 struct cvmx_pow_ws_pcx_s cn52xxp1;
1999 struct cvmx_pow_ws_pcx_s cn56xx;
2000 struct cvmx_pow_ws_pcx_s cn56xxp1;
2001 struct cvmx_pow_ws_pcx_s cn58xx;
2002 struct cvmx_pow_ws_pcx_s cn58xxp1;
2003 struct cvmx_pow_ws_pcx_s cn61xx;
2004 struct cvmx_pow_ws_pcx_s cn63xx;
2005 struct cvmx_pow_ws_pcx_s cn63xxp1;
2006 struct cvmx_pow_ws_pcx_s cn66xx;
2007 struct cvmx_pow_ws_pcx_s cnf71xx;
2008 };
2009 typedef union cvmx_pow_ws_pcx cvmx_pow_ws_pcx_t;
2010
2011 #endif
2012