Searched refs:__vxge_os_cacheline_size (Results 1 – 5 of 5) sorted by relevance
303 #define __vxge_os_cacheline_size CACHE_LINE_SIZE macro304 #define __vxge_os_attr_cacheline_aligned __aligned(__vxge_os_cacheline_size)
600 ((ring->rxd_priv_size + __vxge_os_cacheline_size - 1) / in __hal_ring_create()601 __vxge_os_cacheline_size) * __vxge_os_cacheline_size; in __hal_ring_create()
401 ((fifo->txdl_priv_size + __vxge_os_cacheline_size - 1) / in __hal_fifo_create()402 __vxge_os_cacheline_size) * __vxge_os_cacheline_size; in __hal_fifo_create()
9390 switch (__vxge_os_cacheline_size) { in __hal_vpath_size_quantum_set()
1901 #define VXGE_HAL_DEF_FIFO_ALIGNMENT_SIZE __vxge_os_cacheline_size