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Searched refs:ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK (Results 1 – 2 of 2) sorted by relevance

/NextBSD/sys/arm/xilinx/
HDzy7_slcr.c365 reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK | in zy7_pl_fclk_set_freq()
414 div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >> in zy7_pl_fclk_get_freq()
HDzy7_slcr.h152 #define ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK (0x3f << 20) macro