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Searched refs:X86 (Results 1 – 25 of 120) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrInfo.cpp105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32), in X86InstrInfo()
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)), in X86InstrInfo()
110 { X86::ADC32ri, X86::ADC32mi, 0 }, in X86InstrInfo()
111 { X86::ADC32ri8, X86::ADC32mi8, 0 }, in X86InstrInfo()
112 { X86::ADC32rr, X86::ADC32mr, 0 }, in X86InstrInfo()
113 { X86::ADC64ri32, X86::ADC64mi32, 0 }, in X86InstrInfo()
114 { X86::ADC64ri8, X86::ADC64mi8, 0 }, in X86InstrInfo()
115 { X86::ADC64rr, X86::ADC64mr, 0 }, in X86InstrInfo()
116 { X86::ADD16ri, X86::ADD16mi, 0 }, in X86InstrInfo()
117 { X86::ADD16ri8, X86::ADD16mi8, 0 }, in X86InstrInfo()
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HDX86RegisterInfo.cpp58 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP), in X86RegisterInfo()
61 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) { in X86RegisterInfo()
77 StackPtr = Use64BitReg ? X86::RSP : X86::ESP; in X86RegisterInfo()
78 FramePtr = Use64BitReg ? X86::RBP : X86::EBP; in X86RegisterInfo()
79 BasePtr = Use64BitReg ? X86::RBX : X86::EBX; in X86RegisterInfo()
82 StackPtr = X86::ESP; in X86RegisterInfo()
83 FramePtr = X86::EBP; in X86RegisterInfo()
84 BasePtr = X86::ESI; in X86RegisterInfo()
104 if (!Is64Bit && Idx == X86::sub_8bit) in getSubClassWithSubReg()
105 Idx = X86::sub_8bit_hi; in getSubClassWithSubReg()
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HDX86FloatingPoint.cpp126 if (Reg < X86::FP0 || Reg > X86::FP6) in calcLiveInMask()
128 Mask |= 1 << (Reg - X86::FP0); in calcLiveInMask()
194 return StackTop - 1 - getSlot(RegNo) + X86::ST0; in getSTReg()
223 BuildMI(*MBB, I, dl, TII->get(X86::XCH_F)).addReg(STReg); in moveToTop()
232 BuildMI(*MBB, I, dl, TII->get(X86::LD_Frr)).addReg(STReg); in duplicateToTop()
275 return X86::RFP80RegClass.contains(DstReg) || in isFPCopy()
276 X86::RFP80RegClass.contains(SrcReg); in isFPCopy()
291 assert(Reg >= X86::FP0 && Reg <= X86::FP6 && "Expected FP register!"); in getFPReg()
292 return Reg - X86::FP0; in getFPReg()
303 static_assert(X86::FP6 == X86::FP0+6, "Register enums aren't sorted right!"); in runOnMachineFunction()
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HDX86MCInstLower.cpp310 if (Reg != X86::AL && Reg != X86::AX && Reg != X86::EAX && Reg != X86::RAX) in SimplifyShortImmForm()
328 case X86::MOVSX16rr8: // movsbw %al, %ax --> cbtw in SimplifyMOVSX()
329 if (Op0 == X86::AX && Op1 == X86::AL) in SimplifyMOVSX()
330 NewOpcode = X86::CBW; in SimplifyMOVSX()
332 case X86::MOVSX32rr16: // movswl %ax, %eax --> cwtl in SimplifyMOVSX()
333 if (Op0 == X86::EAX && Op1 == X86::AX) in SimplifyMOVSX()
334 NewOpcode = X86::CWDE; in SimplifyMOVSX()
336 case X86::MOVSX64rr32: // movslq %eax, %rax --> cltq in SimplifyMOVSX()
337 if (Op0 == X86::RAX && Op1 == X86::EAX) in SimplifyMOVSX()
338 NewOpcode = X86::CDQE; in SimplifyMOVSX()
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HDX86FrameLowering.cpp102 return X86::SUB64ri8; in getSUBriOpcode()
103 return X86::SUB64ri32; in getSUBriOpcode()
106 return X86::SUB32ri8; in getSUBriOpcode()
107 return X86::SUB32ri; in getSUBriOpcode()
114 return X86::ADD64ri8; in getADDriOpcode()
115 return X86::ADD64ri32; in getADDriOpcode()
118 return X86::ADD32ri8; in getADDriOpcode()
119 return X86::ADD32ri; in getADDriOpcode()
124 return isLP64 ? X86::SUB64rr : X86::SUB32rr; in getSUBrrOpcode()
128 return isLP64 ? X86::ADD64rr : X86::ADD32rr; in getADDrrOpcode()
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HDX86FastISel.cpp167 bool foldX86XALUIntrinsic(X86::CondCode &CC, const Instruction *I,
176 static std::pair<X86::CondCode, bool>
178 X86::CondCode CC = X86::COND_INVALID; in getX86ConditionCode()
183 case CmpInst::FCMP_UEQ: CC = X86::COND_E; break; in getX86ConditionCode()
185 case CmpInst::FCMP_OGT: CC = X86::COND_A; break; in getX86ConditionCode()
187 case CmpInst::FCMP_OGE: CC = X86::COND_AE; break; in getX86ConditionCode()
189 case CmpInst::FCMP_ULT: CC = X86::COND_B; break; in getX86ConditionCode()
191 case CmpInst::FCMP_ULE: CC = X86::COND_BE; break; in getX86ConditionCode()
192 case CmpInst::FCMP_ONE: CC = X86::COND_NE; break; in getX86ConditionCode()
193 case CmpInst::FCMP_UNO: CC = X86::COND_P; break; in getX86ConditionCode()
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HDX86ISelDAGToDAG.cpp96 return RegNode->getReg() == X86::RIP; in isRIPRelative()
623 if (!X86::isOffsetSuitableForCodeModel(Val, M, in FoldOffsetIntoAddress()
651 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in MatchLoadInAddress()
654 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in MatchLoadInAddress()
721 AM.setBaseReg(CurDAG->getRegister(X86::RIP, MVT::i64)); in MatchWrapper()
788 AM.Base_Reg = CurDAG->getRegister(X86::RIP, MVT::i64); in MatchAddress()
1353 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in SelectVectorAddr()
1355 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in SelectVectorAddr()
1402 AM.Segment = CurDAG->getRegister(X86::GS, MVT::i16); in SelectAddr()
1404 AM.Segment = CurDAG->getRegister(X86::FS, MVT::i16); in SelectAddr()
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HDX86ExpandPseudo.cpp72 case X86::TCRETURNdi: in ExpandMI()
73 case X86::TCRETURNri: in ExpandMI()
74 case X86::TCRETURNmi: in ExpandMI()
75 case X86::TCRETURNdi64: in ExpandMI()
76 case X86::TCRETURNri64: in ExpandMI()
77 case X86::TCRETURNmi64: { in ExpandMI()
78 bool isMem = Opcode == X86::TCRETURNmi || Opcode == X86::TCRETURNmi64; in ExpandMI()
94 if (Opcode == X86::TCRETURNdi || Opcode == X86::TCRETURNdi64) { in ExpandMI()
95 unsigned Op = (Opcode == X86::TCRETURNdi) in ExpandMI()
96 ? X86::TAILJMPd in ExpandMI()
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HDX86FixupLEAs.cpp102 case X86::MOV32rr: in postRAConvertToLEA()
103 case X86::MOV64rr: { in postRAConvertToLEA()
107 TII->get(MI->getOpcode() == X86::MOV32rr ? X86::LEA32r in postRAConvertToLEA()
108 : X86::LEA64r)) in postRAConvertToLEA()
118 case X86::ADD64ri32: in postRAConvertToLEA()
119 case X86::ADD64ri8: in postRAConvertToLEA()
120 case X86::ADD64ri32_DB: in postRAConvertToLEA()
121 case X86::ADD64ri8_DB: in postRAConvertToLEA()
122 case X86::ADD32ri: in postRAConvertToLEA()
123 case X86::ADD32ri8: in postRAConvertToLEA()
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HDX86SelectionDAGInfo.cpp60 const unsigned ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, in EmitTargetCodeForMemset()
61 X86::ECX, X86::EAX, X86::EDI}; in EmitTargetCodeForMemset()
120 ValReg = X86::AX; in EmitTargetCodeForMemset()
125 ValReg = X86::EAX; in EmitTargetCodeForMemset()
130 ValReg = X86::RAX; in EmitTargetCodeForMemset()
136 ValReg = X86::AL; in EmitTargetCodeForMemset()
153 Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag); in EmitTargetCodeForMemset()
157 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX, in EmitTargetCodeForMemset()
160 Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI, in EmitTargetCodeForMemset()
175 Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : in EmitTargetCodeForMemset()
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HDX86RegisterInfo.td1 //===- X86RegisterInfo.td - Describe the X86 Register File --*- tablegen -*-==//
10 // This file describes the X86 Register file, defining the registers themselves,
17 let Namespace = "X86";
23 let Namespace = "X86" in {
42 // variations by target as well. Currently the first entry is for X86-64,
43 // second - for EH on X86-32/Darwin and third is 'generic' one (X86-32/Linux
44 // and debug information on X86-32/Darwin)
60 // X86-64 only, requires REX.
91 // X86-64 only, requires REX.
115 // X86-64 only, requires REX
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HDX86CallFrameOptimization.cpp254 if (Opcode == X86::MOV32mi || Opcode == X86::MOV32mr) in classifyInstruction()
331 while (I->getOpcode() == X86::LEA32r) in collectCallInfo()
369 if (!I->getOperand(X86::AddrBaseReg).isReg() || in collectCallInfo()
370 (I->getOperand(X86::AddrBaseReg).getReg() != StackPtr) || in collectCallInfo()
371 !I->getOperand(X86::AddrScaleAmt).isImm() || in collectCallInfo()
372 (I->getOperand(X86::AddrScaleAmt).getImm() != 1) || in collectCallInfo()
373 (I->getOperand(X86::AddrIndexReg).getReg() != X86::NoRegister) || in collectCallInfo()
374 (I->getOperand(X86::AddrSegmentReg).getReg() != X86::NoRegister) || in collectCallInfo()
375 !I->getOperand(X86::AddrDisp).isImm()) in collectCallInfo()
378 int64_t StackDisp = I->getOperand(X86::AddrDisp).getImm(); in collectCallInfo()
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HDX86IntrinsicsInfo.h59 X86_INTRINSIC_DATA(avx512_gather3div2_df, GATHER, X86::VGATHERQPDZ128rm, 0),
60 X86_INTRINSIC_DATA(avx512_gather3div2_di, GATHER, X86::VPGATHERQQZ128rm, 0),
61 X86_INTRINSIC_DATA(avx512_gather3div4_df, GATHER, X86::VGATHERQPDZ256rm, 0),
62 X86_INTRINSIC_DATA(avx512_gather3div4_di, GATHER, X86::VPGATHERQQZ256rm, 0),
63 X86_INTRINSIC_DATA(avx512_gather3div4_sf, GATHER, X86::VGATHERQPSZ128rm, 0),
64 X86_INTRINSIC_DATA(avx512_gather3div4_si, GATHER, X86::VPGATHERQDZ128rm, 0),
65 X86_INTRINSIC_DATA(avx512_gather3div8_sf, GATHER, X86::VGATHERQPSZ256rm, 0),
66 X86_INTRINSIC_DATA(avx512_gather3div8_si, GATHER, X86::VPGATHERQDZ256rm, 0),
67 X86_INTRINSIC_DATA(avx512_gather3siv2_df, GATHER, X86::VGATHERDPDZ128rm, 0),
68 X86_INTRINSIC_DATA(avx512_gather3siv2_di, GATHER, X86::VPGATHERDQZ128rm, 0),
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HDX86ISelLowering.cpp144 addRegisterClass(MVT::i8, &X86::GR8RegClass); in X86TargetLowering()
145 addRegisterClass(MVT::i16, &X86::GR16RegClass); in X86TargetLowering()
146 addRegisterClass(MVT::i32, &X86::GR32RegClass); in X86TargetLowering()
148 addRegisterClass(MVT::i64, &X86::GR64RegClass); in X86TargetLowering()
477 setExceptionPointerRegister(X86::RAX); in X86TargetLowering()
478 setExceptionSelectorRegister(X86::RDX); in X86TargetLowering()
480 setExceptionPointerRegister(X86::EAX); in X86TargetLowering()
481 setExceptionSelectorRegister(X86::EDX); in X86TargetLowering()
517 addRegisterClass(MVT::f32, &X86::FR32RegClass); in X86TargetLowering()
518 addRegisterClass(MVT::f64, &X86::FR64RegClass); in X86TargetLowering()
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/NextBSD/contrib/llvm/lib/Target/X86/Disassembler/
HDX86Disassembler.cpp59 namespace X86 { namespace
84 if (FB[X86::Mode16Bit]) { in X86GenericDisassembler()
87 } else if (FB[X86::Mode32Bit]) { in X86GenericDisassembler()
90 } else if (FB[X86::Mode64Bit]) { in X86GenericDisassembler()
174 #define ENTRY(x) X86::x, in translateRegister()
227 X86::CS,
228 X86::SS,
229 X86::DS,
230 X86::ES,
231 X86::FS,
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/NextBSD/contrib/llvm/lib/Target/X86/InstPrinter/
HDX86InstComments.cpp33 case X86::PMOVZXBWrm: in getZeroExtensionTypes()
34 case X86::PMOVZXBWrr: in getZeroExtensionTypes()
35 case X86::VPMOVZXBWrm: in getZeroExtensionTypes()
36 case X86::VPMOVZXBWrr: in getZeroExtensionTypes()
40 case X86::VPMOVZXBWYrm: in getZeroExtensionTypes()
41 case X86::VPMOVZXBWYrr: in getZeroExtensionTypes()
45 case X86::PMOVZXBDrm: in getZeroExtensionTypes()
46 case X86::PMOVZXBDrr: in getZeroExtensionTypes()
47 case X86::VPMOVZXBDrm: in getZeroExtensionTypes()
48 case X86::VPMOVZXBDrr: in getZeroExtensionTypes()
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HDX86ATTInstPrinter.cpp59 if (MI->getOpcode() == X86::CALLpcrel32 && in printInst()
60 (STI.getFeatureBits()[X86::Mode64Bit])) { in printInst()
189 const MCOperand &BaseReg = MI->getOperand(Op + X86::AddrBaseReg); in printMemReference()
190 const MCOperand &IndexReg = MI->getOperand(Op + X86::AddrIndexReg); in printMemReference()
191 const MCOperand &DispSpec = MI->getOperand(Op + X86::AddrDisp); in printMemReference()
192 const MCOperand &SegReg = MI->getOperand(Op + X86::AddrSegmentReg); in printMemReference()
198 printOperand(MI, Op + X86::AddrSegmentReg, O); in printMemReference()
214 printOperand(MI, Op + X86::AddrBaseReg, O); in printMemReference()
218 printOperand(MI, Op + X86::AddrIndexReg, O); in printMemReference()
219 unsigned ScaleVal = MI->getOperand(Op + X86::AddrScaleAmt).getImm(); in printMemReference()
/NextBSD/contrib/llvm/lib/Target/X86/MCTargetDesc/
HDX86AsmBackend.cpp45 case X86::reloc_riprel_4byte: in getFixupKindLog2Size()
46 case X86::reloc_riprel_4byte_movq_load: in getFixupKindLog2Size()
47 case X86::reloc_signed_4byte: in getFixupKindLog2Size()
48 case X86::reloc_global_offset_table: in getFixupKindLog2Size()
55 case X86::reloc_global_offset_table8: in getFixupKindLog2Size()
84 return X86::NumTargetFixupKinds; in getNumFixupKinds()
88 const static MCFixupKindInfo Infos[X86::NumTargetFixupKinds] = { in getFixupKindInfo()
138 case X86::JAE_1: return X86::JAE_4; in getRelaxedOpcodeBranch()
139 case X86::JA_1: return X86::JA_4; in getRelaxedOpcodeBranch()
140 case X86::JBE_1: return X86::JBE_4; in getRelaxedOpcodeBranch()
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HDX86BaseInfo.h27 namespace X86 {
723 if ((RegNo > X86::XMM7 && RegNo <= X86::XMM15) || in isX86_64ExtendedReg()
724 (RegNo > X86::XMM23 && RegNo <= X86::XMM31) || in isX86_64ExtendedReg()
725 (RegNo > X86::YMM7 && RegNo <= X86::YMM15) || in isX86_64ExtendedReg()
726 (RegNo > X86::YMM23 && RegNo <= X86::YMM31) || in isX86_64ExtendedReg()
727 (RegNo > X86::ZMM7 && RegNo <= X86::ZMM15) || in isX86_64ExtendedReg()
728 (RegNo > X86::ZMM23 && RegNo <= X86::ZMM31)) in isX86_64ExtendedReg()
733 case X86::R8: case X86::R9: case X86::R10: case X86::R11: in isX86_64ExtendedReg()
734 case X86::R12: case X86::R13: case X86::R14: case X86::R15: in isX86_64ExtendedReg()
735 case X86::R8D: case X86::R9D: case X86::R10D: case X86::R11D: in isX86_64ExtendedReg()
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HDX86MCCodeEmitter.cpp45 return STI.getFeatureBits()[X86::Mode64Bit]; in is64BitMode()
49 return STI.getFeatureBits()[X86::Mode32Bit]; in is32BitMode()
53 return STI.getFeatureBits()[X86::Mode16Bit]; in is16BitMode()
60 const MCOperand &BaseReg = MI.getOperand(Op+X86::AddrBaseReg); in Is16BitMemOperand()
61 const MCOperand &IndexReg = MI.getOperand(Op+X86::AddrIndexReg); in Is16BitMemOperand()
62 const MCOperand &Disp = MI.getOperand(Op+X86::AddrDisp); in Is16BitMemOperand()
68 X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg.getReg())) || in Is16BitMemOperand()
70 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg.getReg()))) in Is16BitMemOperand()
102 assert(X86::K0 != MI.getOperand(OpNum).getReg() && in getWriteMaskRegisterEncoding()
217 case 4: return MCFixupKind(X86::reloc_signed_4byte); in getImmFixupKind()
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HDX86WinCOFFObjectWriter.cpp54 case X86::reloc_riprel_4byte: in getRelocType()
55 case X86::reloc_riprel_4byte_movq_load: in getRelocType()
58 case X86::reloc_signed_4byte: in getRelocType()
74 case X86::reloc_riprel_4byte: in getRelocType()
75 case X86::reloc_riprel_4byte_movq_load: in getRelocType()
78 case X86::reloc_signed_4byte: in getRelocType()
/NextBSD/contrib/llvm/lib/Target/X86/AsmParser/
HDX86AsmInstrumentation.cpp117 bool IsStackReg(unsigned Reg) { return Reg == X86::RSP || Reg == X86::ESP; } in IsStackReg()
157 if (Reg != X86::NoRegister) in AddBusyReg()
167 static const MCPhysReg Candidates[] = { X86::RBP, X86::RAX, X86::RBX, in ChooseFrameReg()
168 X86::RCX, X86::RDX, X86::RDI, in ChooseFrameReg()
169 X86::RSI }; in ChooseFrameReg()
174 return X86::NoRegister; in ChooseFrameReg()
179 return Reg == X86::NoRegister ? Reg : getX86SubSuperRegister(Reg, VT); in convReg()
198 EmitInstruction(Out, MCInstBuilder(X86::REP_PREFIX)); in InstrumentAndEmitInstruction()
202 RepPrefix = (Inst.getOpcode() == X86::REP_PREFIX); in InstrumentAndEmitInstruction()
247 Inst.setOpcode(VT == MVT::i32 ? X86::LEA32r : X86::LEA64r); in EmitLEA()
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HDX86Operand.h239 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15; in isMemVX32()
243 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM31; in isMemVX32X()
247 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15; in isMemVY32()
251 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM31; in isMemVY32X()
255 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM15; in isMemVX64()
259 getMemIndexReg() >= X86::XMM0 && getMemIndexReg() <= X86::XMM31; in isMemVX64X()
263 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM15; in isMemVY64()
267 getMemIndexReg() >= X86::YMM0 && getMemIndexReg() <= X86::YMM31; in isMemVY64X()
271 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31; in isMemVZ32()
275 getMemIndexReg() >= X86::ZMM0 && getMemIndexReg() <= X86::ZMM31; in isMemVZ64()
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HDX86AsmParser.cpp761 return STI.getFeatureBits()[X86::Mode64Bit]; in is64BitMode()
765 return STI.getFeatureBits()[X86::Mode32Bit]; in is32BitMode()
769 return STI.getFeatureBits()[X86::Mode16Bit]; in is16BitMode()
772 FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit}); in SwitchMode()
835 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) && in CheckBaseRegAndIndexReg()
836 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) || in CheckBaseRegAndIndexReg()
837 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) && in CheckBaseRegAndIndexReg()
838 IndexReg != X86::RIZ) { in CheckBaseRegAndIndexReg()
842 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) && in CheckBaseRegAndIndexReg()
843 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) || in CheckBaseRegAndIndexReg()
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/NextBSD/share/colldef/
HDel_GR.UTF-8.src23 collating-symbol <X86>
183 <X86>
496 <GREEK_SMALL_LETTER_ALPHA_WITH_DASIA> <X5F06>;"<X05><X86>";"<X05><X05>";<GREEK_SMALL_LETTER_ALPHA_W…
497 <GREEK_CAPITAL_LETTER_ALPHA_WITH_DASIA> <X5F06>;"<X05><X86>";"<XA6><X05>";<GREEK_CAPITAL_LETTER_ALP…
498 <GREEK_SMALL_LETTER_ALPHA_WITH_DASIA_AND_OXIA> <X5F06>;"<X05><X86><X88>";"<X05><X05><X05>";<GREEK_S…
499 <GREEK_CAPITAL_LETTER_ALPHA_WITH_DASIA_AND_OXIA> <X5F06>;"<X05><X86><X88>";"<XA6><X05><X05>";<GREEK…
500 <GREEK_SMALL_LETTER_ALPHA_WITH_DASIA_AND_OXIA_AND_YPOGEGRAMMENI> <X5F06>;"<X05><X86><X88><XD8>";"<X…
501 <GREEK_CAPITAL_LETTER_ALPHA_WITH_DASIA_AND_OXIA_AND_PROSGEGRAMMENI> <X5F06>;"<X05><X86><X88><XD8>";…
502 <GREEK_SMALL_LETTER_ALPHA_WITH_DASIA_AND_VARIA> <X5F06>;"<X05><X86><X8A>";"<X05><X05><X05>";<GREEK_…
503 <GREEK_CAPITAL_LETTER_ALPHA_WITH_DASIA_AND_VARIA> <X5F06>;"<X05><X86><X8A>";"<XA6><X05><X05>";<GREE…
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