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Searched refs:Vd (Results 1 – 10 of 10) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMInstrNEON.td275 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
285 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
295 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
306 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
316 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
326 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
336 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
346 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
358 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
368 let MIOperandInfo = (ops DPR:$Vd, i32imm:$idx);
[all …]
HDARMInstrFormats.td1939 bits<5> Vd;
1943 let Inst{22} = Vd{4};
1944 let Inst{15-12} = Vd{3-0};
2009 bits<5> Vd;
2012 let Inst{15-12} = Vd{3-0};
2013 let Inst{22} = Vd{4};
2035 bits<5> Vd;
2038 let Inst{15-12} = Vd{3-0};
2039 let Inst{22} = Vd{4};
2049 OpcodeStr, Dt, "$Vd, $Vm", "", pattern> {
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HDARMInstrVFP.td1212 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
1224 // if dp_operation then UInt(D:Vd) else UInt(Vd:D);
/NextBSD/contrib/llvm/tools/clang/include/clang/Analysis/Analyses/
HDThreadSafetyTIL.h364 Variable(const Variable &Vd, SExpr *D) // rewrite constructor in Variable() argument
365 : SExpr(Vd), Name(Vd.Name), Definition(D), Cvdecl(Vd.Cvdecl) { in Variable()
366 Flags = Vd.kind(); in Variable()
659 Function(Variable *Vd, SExpr *Bd) in Function() argument
660 : SExpr(COP_Function), VarDecl(Vd), Body(Bd) { in Function()
661 Vd->setKind(Variable::VK_Fun); in Function()
663 Function(const Function &F, Variable *Vd, SExpr *Bd) // rewrite constructor in Function() argument
664 : SExpr(F), VarDecl(Vd), Body(Bd) { in Function()
665 Vd->setKind(Variable::VK_Fun); in Function()
710 SFunction(Variable *Vd, SExpr *B) in SFunction() argument
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/NextBSD/contrib/llvm/tools/clang/lib/Analysis/
HDThreadSafety.cpp243 bool containsMutexDecl(FactManager &FM, const ValueDecl* Vd) const { in containsMutexDecl()
245 return FM[ID].valueDecl() == Vd; in containsMutexDecl()
276 BeforeInfo* insertAttrExprs(const ValueDecl* Vd,
279 void checkBeforeAfter(const ValueDecl* Vd,
965 BeforeSet::BeforeInfo* BeforeSet::insertAttrExprs(const ValueDecl* Vd, in insertAttrExprs() argument
968 auto& Entry = BMap.FindAndConstruct(Vd); in insertAttrExprs()
972 for (Attr* At : Vd->attrs()) { in insertAttrExprs()
1017 ArgBv->push_back(Vd); in insertAttrExprs()
1040 std::function<bool (const ValueDecl*)> traverse = [&](const ValueDecl* Vd) { in checkBeforeAfter() argument
1041 if (!Vd) in checkBeforeAfter()
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/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.td2689 def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}",
2690 (NOTv8i8 V64:$Vd, V64:$Vn)>;
2691 def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}",
2692 (NOTv16i8 V128:$Vd, V128:$Vn)>;
3838 (v16i8 V128:$Vd), VectorIndexB:$idx, (v16i8 V128:$Vs),
3841 V128:$Vd, VectorIndexB:$idx, V128:$Vs, VectorIndexB:$idx2)
3844 (v8i16 V128:$Vd), VectorIndexH:$idx, (v8i16 V128:$Vs),
3847 V128:$Vd, VectorIndexH:$idx, V128:$Vs, VectorIndexH:$idx2)
3850 (v4i32 V128:$Vd), VectorIndexS:$idx, (v4i32 V128:$Vs),
3853 V128:$Vd, VectorIndexS:$idx, V128:$Vs, VectorIndexS:$idx2)
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HDAArch64SchedCyclone.td320 // FMOVv2f64ns Vd.2d, #0.0
329 // ORR.16b Vd,Vn,Vn
630 // Vd is read 5 cycles after issuing the vector load.
HDAArch64InstrFormats.td4772 def : InstAlias<asm # " $Vd.2s, $Vn.2s, #0",
4773 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4774 def : InstAlias<asm # " $Vd.4s, $Vn.4s, #0",
4775 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
4776 def : InstAlias<asm # " $Vd.2d, $Vn.2d, #0",
4777 (!cast<Instruction>(NAME # v2i64rz) V128:$Vd, V128:$Vn), 0>;
4778 def : InstAlias<asm # ".2s $Vd, $Vn, #0",
4779 (!cast<Instruction>(NAME # v2i32rz) V64:$Vd, V64:$Vn), 0>;
4780 def : InstAlias<asm # ".4s $Vd, $Vn, #0",
4781 (!cast<Instruction>(NAME # v4i32rz) V128:$Vd, V128:$Vn), 0>;
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/NextBSD/contrib/llvm/lib/Target/ARM/Disassembler/
HDARMDisassembler.cpp1254 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeSPRRegListOperand() local
1258 if (regs == 0 || (Vd + regs) > 32) { in DecodeSPRRegListOperand()
1259 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeSPRRegListOperand()
1264 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1267 if (!Check(S, DecodeSPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeSPRRegListOperand()
1278 unsigned Vd = fieldFromInstruction(Val, 8, 5); in DecodeDPRRegListOperand() local
1282 if (regs == 0 || regs > 16 || (Vd + regs) > 32) { in DecodeDPRRegListOperand()
1283 regs = Vd + regs > 32 ? 32 - Vd : regs; in DecodeDPRRegListOperand()
1289 if (!Check(S, DecodeDPRRegisterClass(Inst, Vd, Address, Decoder))) in DecodeDPRRegListOperand()
1292 if (!Check(S, DecodeDPRRegisterClass(Inst, ++Vd, Address, Decoder))) in DecodeDPRRegListOperand()
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/NextBSD/contrib/llvm/tools/llvm-objdump/
HDMachODump.cpp8370 MachO::version_min_command Vd = Obj->getVersionMinLoadCommand(Command); in PrintLoadCommands() local
8371 PrintVersionMinLoadCommand(Vd); in PrintLoadCommands()