Searched refs:VR1 (Results 1 – 4 of 4) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsSEFrameLowering.cpp | 190 unsigned VR1 = MRI.createVirtualRegister(RC); in expandLoadACC() local
199 TII.loadRegFromStack(MBB, I, VR1, FI, RC, &RegInfo, RegSize); in expandLoadACC()
200 BuildMI(MBB, I, DL, Desc, Hi).addReg(VR1, RegState::Kill); in expandLoadACC()
215 unsigned VR1 = MRI.createVirtualRegister(RC); in expandStoreACC() local
222 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandStoreACC()
223 TII.storeRegToStack(MBB, I, VR1, true, FI, RC, &RegInfo, RegSize); in expandStoreACC()
247 unsigned VR1 = MRI.createVirtualRegister(RC); in expandCopyACC() local
256 BuildMI(MBB, I, DL, TII.get(MFHiOpc), VR1).addReg(Src, SrcKill); in expandCopyACC()
258 .addReg(VR1, RegState::Kill); in expandCopyACC()
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| HD | MipsSEISelLowering.cpp | 2946 unsigned VR1 = RegInfo.createVirtualRegister(RC); in emitBPOSGE32() local
2947 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) in emitBPOSGE32()
2953 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); in emitBPOSGE32()
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| /NextBSD/contrib/llvm/lib/Target/Hexagon/ |
| HD | HexagonGenInsert.cpp | 204 bool operator() (unsigned VR1, unsigned VR2) const { in operator ()()
205 return operator[](VR1) < operator[](VR2); in operator ()()
280 bool operator() (unsigned VR1, unsigned VR2) const;
296 bool operator() (unsigned VR1, unsigned VR2) const;
306 bool RegisterCellLexCompare::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
316 if (VR1 == VR2) in operator ()()
319 const BitTracker::RegisterCell &RC1 = CM.lookup(VR1), &RC2 = CM.lookup(VR2); in operator ()()
330 return BitOrd.BaseOrd[VR1] < BitOrd.BaseOrd[VR2]; in operator ()()
334 bool RegisterCellBitCompareSel::operator() (unsigned VR1, unsigned VR2) const { in operator ()() argument
335 if (VR1 == VR2) in operator ()()
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| /NextBSD/contrib/gcc/ |
| HD | ChangeLog-2005 | 3891 than VR1 or vice-versa.
5677 sets VR0->EQUIV and VR1->EQUIV when meeting a range and an
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