Home
last modified time | relevance | path

Searched refs:V0 (Results 1 – 25 of 47) sorted by relevance

12

/NextBSD/contrib/gcc/config/arm/
HDcirrus.md38 "cfadd64%?\\t%V0, %V1, %V2"
48 "cfadd32%?\\t%V0, %V1, %V2"
58 "cfadds%?\\t%V0, %V1, %V2"
68 "cfaddd%?\\t%V0, %V1, %V2"
78 "cfsub64%?\\t%V0, %V1, %V2"
88 "cfsub32%?\\t%V0, %V1, %V2"
98 "cfsubs%?\\t%V0, %V1, %V2"
108 "cfsubd%?\\t%V0, %V1, %V2"
118 "cfmul32%?\\t%V0, %V1, %V2"
128 "cfmul64%?\\t%V0, %V1, %V2"
[all …]
/NextBSD/contrib/groff/src/roff/troff/
HDdiv.cpp55 : prev(0), nm(s), vertical_position(V0), high_water_mark(V0), in diversion()
58 marked_place(V0) in diversion()
68 : pre_extra(V0), post_extra(V0), pre(vs), post(post_vs) in vertical_size()
78 if (n < V0) { in set_vertical_size()
88 if (n < V0) in set_vertical_size()
320 else if (n + vertical_position < V0) in space()
347 if (pt->position >= V0) { in find_next_trap()
407 else if (v.post > V0) { in output()
471 else if (y < V0) { in space()
472 vertical_position = V0; in space()
[all …]
HDcolumn.cpp174 return V0; in distance()
179 return V0; in height()
184 return V0; in extra_space()
230 current = V0; in reset()
281 : bottom(V0), col(0), tail(&col), out(0) in column()
398 bottom = V0; in reset()
419 vunits vpos(V0); in output()
430 bottom = V0; in output()
439 return V0; in get_last_extra_space()
473 if (v <= V0) { in append()
[all …]
HDnode.cpp1484 if (page_length > V0) { in really_begin_page()
1546 if (page_length > V0) { in trailer()
3005 *min = V0; in node_list_vertical_extent()
3006 *max = V0; in node_list_vertical_extent()
3007 vunits cur_vpos = V0; in node_list_vertical_extent()
3341 return V0; in vertical_width()
3389 if (v < V0) { in vertical_extent()
3391 *max = V0; in vertical_extent()
3395 *min = V0; in vertical_extent()
3407 if (x < V0) { in vertical_extent()
[all …]
HDdiv.h140 int begin_page(vunits = V0);
HDenv.cpp1005 return V0; in get_prev_char_height()
1015 return V0; in get_prev_char_depth()
1051 vunits real_min = V0; in width_registers()
1052 vunits real_max = V0; in width_registers()
1386 if (temp < V0) { in vertical_spacing()
1402 if (temp < V0) { in post_vertical_spacing()
1405 temp = V0; in post_vertical_spacing()
HDhvunits.h48 extern vunits V0;
/NextBSD/lib/msun/src/
HDe_j1f.c97 static const float V0[5] = { variable
149 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in __ieee754_y1f()
HDe_j1.c136 static const double V0[5] = { variable
195 v = one+z*(V0[0]+z*(V0[1]+z*(V0[2]+z*(V0[3]+z*V0[4])))); in __ieee754_y1()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsSEISelDAGToDAG.cpp140 unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg(); in initGlobalBaseReg() local
145 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
156 BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0) in initGlobalBaseReg()
158 BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0) in initGlobalBaseReg()
170 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
172 BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0) in initGlobalBaseReg()
185 BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0) in initGlobalBaseReg()
187 BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9); in initGlobalBaseReg()
212 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
213 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
[all …]
HDMips16ISelDAGToDAG.cpp77 unsigned V0, V1, V2, GlobalBaseReg = MipsFI->getGlobalBaseReg(); in initGlobalBaseReg() local
80 V0 = RegInfo.createVirtualRegister(RC); in initGlobalBaseReg()
84 BuildMI(MBB, I, DL, TII.get(Mips::GotPrologue16), V0). in initGlobalBaseReg()
89 BuildMI(MBB, I, DL, TII.get(Mips::SllX16), V2).addReg(V0).addImm(16); in initGlobalBaseReg()
HDMipsRegisterInfo.td90 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
124 def V0_64 : Mips64GPRReg< 2, "2", [V0]>, DwarfRegNum<[2]>;
282 V0, V1, A0, A1, A2, A3,
299 V0, V1, A0, A1, A2, A3)>;
307 V0, V1, A0, A1, A2, A3)>;
315 V0, V1,
335 V0, V1, A0, A1, A2, A3,
341 V0, V1, A0, A1, A2, A3,
HDMipsCallingConv.td96 // i32 are returned in registers V0, V1, A0, A1
97 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>,
246 // i32 are returned in registers V0, V1
247 CCIfType<[i32], CCAssignToReg<[V0, V1]>>,
305 // except for AT, V0 and T9, are available to be used as argument registers.
353 CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
427 CalleeSavedRegs<(add V0, V1, FP,
HDMipsLongBranch.cpp444 BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::V0) in emitGPDisp()
446 BuildMI(MBB, I, DL, TII->get(Mips::ADDiu), Mips::V0) in emitGPDisp()
447 .addReg(Mips::V0).addExternalSymbol("_gp_disp", MipsII::MO_ABS_LO); in emitGPDisp()
448 MBB.removeLiveIn(Mips::V0); in emitGPDisp()
HDMipsAsmPrinter.cpp874 EmitInstrRegReg(STI, MovOpc, Mips::V0, Mips::F0); in EmitSwapFPIntRetval()
877 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
880 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
883 EmitMovFPIntPair(STI, MovOpc, Mips::V0, Mips::V1, Mips::F0, Mips::F1, LE); in EmitSwapFPIntRetval()
/NextBSD/usr.bin/truss/
HDmips-freebsd.c74 switch (regs.r_regs[V0]) { in mips_fetch_args()
122 retval[0] = regs.r_regs[V0]; in mips_fetch_retval()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelDAGToDAG.cpp268 SDNode *createGPRPairNode(EVT VT, SDValue V0, SDValue V1);
269 SDNode *createSRegPairNode(EVT VT, SDValue V0, SDValue V1);
270 SDNode *createDRegPairNode(EVT VT, SDValue V0, SDValue V1);
271 SDNode *createQRegPairNode(EVT VT, SDValue V0, SDValue V1);
274 SDNode *createQuadSRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
275 SDNode *createQuadDRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
276 SDNode *createQuadQRegsNode(EVT VT, SDValue V0, SDValue V1, SDValue V2, SDValue V3);
1591 SDNode *ARMDAGToDAGISel::createGPRPairNode(EVT VT, SDValue V0, SDValue V1) { in createGPRPairNode() argument
1592 SDLoc dl(V0.getNode()); in createGPRPairNode()
1597 const SDValue Ops[] = { RegClass, V0, SubReg0, V1, SubReg1 }; in createGPRPairNode()
[all …]
/NextBSD/sys/mips/include/
HDregnum.h52 #define V0 2 macro
/NextBSD/contrib/llvm/tools/clang/lib/Driver/
HDToolChains.h393 bool isIPhoneOSVersionLT(unsigned V0, unsigned V1 = 0,
396 return TargetVersion < VersionTuple(V0, V1, V2);
399 bool isMacosxVersionLT(unsigned V0, unsigned V1 = 0, unsigned V2 = 0) const {
401 return TargetVersion < VersionTuple(V0, V1, V2);
/NextBSD/sys/mips/mips/
HDexception.S280 SAVE_REG(v0, V0, sp) ;\
341 RESTORE_REG(v0, V0, sp) ;\
439 SAVE_U_PCB_REG(v0, V0, k1)
534 RESTORE_U_PCB_REG(v0, V0, k1)
696 SAVE_U_PCB_REG(v0, V0, k1)
811 RESTORE_U_PCB_REG(v0, V0, k1)
/NextBSD/contrib/llvm/lib/Transforms/Scalar/
HDReassociate.cpp210 Value *V0 = I->getOperand(0); in XorOpnd() local
212 if (isa<ConstantInt>(V0)) in XorOpnd()
213 std::swap(V0, V1); in XorOpnd()
217 SymbolicPart = V0; in XorOpnd()
1009 Value *V0 = Sub->getOperand(0); in ShouldBreakUpSubtract() local
1010 if (isReassociableOp(V0, Instruction::Add, Instruction::FAdd) || in ShouldBreakUpSubtract()
1011 isReassociableOp(V0, Instruction::Sub, Instruction::FSub)) in ShouldBreakUpSubtract()
/NextBSD/contrib/llvm/lib/Transforms/InstCombine/
HDInstCombineAddSub.cpp395 Value *V0 = I->getOperand(0); in drillValueDownOneStep() local
397 if (ConstantFP *C = dyn_cast<ConstantFP>(V0)) { in drillValueDownOneStep()
403 Addend0.set(C, V0); in drillValueDownOneStep()
558 Value *V0 = I->getOperand(0); in simplify() local
560 InstQuota = ((!isa<Constant>(V0) && V0->hasOneUse()) && in simplify()
/NextBSD/sys/geom/raid/
HDmd_ddf.h267 uint8_t V0[32]; member
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelLowering.cpp1851 SDValue V0 = BVN->getOperand(0); in isCommonSplatElement() local
1854 if (BVN->getOperand(i) != V0) in isCommonSplatElement()
1948 SDValue V0 = BVN->getOperand(0); in LowerBUILD_VECTOR() local
1951 if (V0.getOpcode() == ISD::UNDEF) in LowerBUILD_VECTOR()
1952 V0 = DAG.getConstant(0, dl, MVT::i32); in LowerBUILD_VECTOR()
1956 ConstantSDNode *C0 = dyn_cast<ConstantSDNode>(V0); in LowerBUILD_VECTOR()
1961 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0); in LowerBUILD_VECTOR()
1967 return DAG.getNode(HexagonISD::COMBINE, dl, VT, V1, V0); in LowerBUILD_VECTOR()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeIntegerTypes.cpp3050 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_VECTOR_SHUFFLE() local
3052 EVT OutVT = V0.getValueType(); in PromoteIntRes_VECTOR_SHUFFLE()
3054 return DAG.getVectorShuffle(OutVT, dl, V0, V1, NewMask); in PromoteIntRes_VECTOR_SHUFFLE()
3141 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_INSERT_VECTOR_ELT() local
3146 V0, ConvElem, N->getOperand(2)); in PromoteIntRes_INSERT_VECTOR_ELT()
3151 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntOp_EXTRACT_VECTOR_ELT() local
3155 V0->getValueType(0).getScalarType(), V0, V1); in PromoteIntOp_EXTRACT_VECTOR_ELT()
3165 SDValue V0 = GetPromotedInteger(N->getOperand(0)); in PromoteIntOp_EXTRACT_SUBVECTOR() local
3166 MVT InVT = V0.getValueType().getSimpleVT(); in PromoteIntOp_EXTRACT_SUBVECTOR()
3169 SDValue Ext = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, OutVT, V0, N->getOperand(1)); in PromoteIntOp_EXTRACT_SUBVECTOR()

12