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Searched refs:Undef (Results 1 – 25 of 58) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIPrepareScratchRegs.cpp103 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in runOnMachineFunction()
104 .addReg(AMDGPU::SGPR0, RegState::Undef); in runOnMachineFunction()
167 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in runOnMachineFunction()
168 .addReg(AMDGPU::SGPR0, RegState::Undef); in runOnMachineFunction()
HDSIInstrInfo.cpp517 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in storeRegToStackSlot()
518 .addReg(AMDGPU::SGPR0, RegState::Undef); in storeRegToStackSlot()
564 .addReg(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3, RegState::Undef) in loadRegFromStackSlot()
565 .addReg(AMDGPU::SGPR0, RegState::Undef); in loadRegFromStackSlot()
/NextBSD/contrib/llvm/lib/Transforms/Scalar/
HDStructurizeCFG.cpp582 Value *Undef = UndefValue::get(Phi.getType()); in addPhiValues() local
583 Phi.addIncoming(Undef, From); in addPhiValues()
605 Value *Undef = UndefValue::get(Phi->getType()); in setPhiValues() local
607 Updater.AddAvailableValue(&Func->getEntryBlock(), Undef); in setPhiValues()
608 Updater.AddAvailableValue(To, Undef); in setPhiValues()
620 Updater.AddAvailableValue(Dominator.getResult(), Undef); in setPhiValues()
910 Value *Undef = UndefValue::get(II->getType()); in rebuildSSA() local
912 Updater.AddAvailableValue(&Func->getEntryBlock(), Undef); in rebuildSSA()
HDReassociate.cpp869 Constant *Undef = UndefValue::get(I->getType()); in RewriteExprTree() local
871 Undef, Undef, "", I); in RewriteExprTree()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineInstrBuilder.h35 Undef = 0x20, enumerator
39 DefineNoRead = Define | Undef,
77 flags & RegState::Undef,
412 return B ? RegState::Undef : 0; in getUndefRegState()
/NextBSD/contrib/llvm/lib/Transforms/InstCombine/
HDInstCombinePHI.cpp778 Value *Undef = UndefValue::get(FirstPhi.getType()); in SliceUpIllegalIntegerPHI() local
780 ReplaceInstUsesWith(*PHIsToSlice[i], Undef); in SliceUpIllegalIntegerPHI()
781 return ReplaceInstUsesWith(FirstPhi, Undef); in SliceUpIllegalIntegerPHI()
HDInstCombineSimplifyDemanded.cpp904 Constant *Undef = UndefValue::get(EltTy); in SimplifyDemandedVectorElts() local
909 Elts.push_back(Undef); in SimplifyDemandedVectorElts()
918 Elts.push_back(Undef); in SimplifyDemandedVectorElts()
HDInstCombineCalls.cpp828 Value *Undef = UndefValue::get(Vec->getType()); in visitCallInst() local
833 Vec, Undef, ConstantDataVector::get( in visitCallInst()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonExpandCondsets.cpp475 bool Undef = false; in addInstrToLiveness() local
477 Undef = true; in addInstrToLiveness()
486 Undef = true; in addInstrToLiveness()
488 if (!Undef) { in addInstrToLiveness()
HDHexagonInstrInfo.cpp709 .addReg(Reg, RegState::Undef) in expandPostRAPseudo()
710 .addReg(Reg, RegState::Undef); in expandPostRAPseudo()
717 .addReg(Reg, RegState::Undef) in expandPostRAPseudo()
718 .addReg(Reg, RegState::Undef); in expandPostRAPseudo()
2013 PredRegFlags |= RegState::Undef; in getPredReg()
/NextBSD/contrib/llvm/lib/CodeGen/MIRParser/
HDMIParser.cpp347 Flags |= RegState::Undef; in parseRegisterFlag()
390 Flags & RegState::Kill, Flags & RegState::Dead, Flags & RegState::Undef, in parseRegisterOperand()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAG.cpp4994 SDValue Undef = getUNDEF(Ptr.getValueType()); in getLoad() local
4995 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
5003 SDValue Undef = getUNDEF(Ptr.getValueType()); in getLoad() local
5004 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
5014 SDValue Undef = getUNDEF(Ptr.getValueType()); in getExtLoad() local
5015 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
5024 SDValue Undef = getUNDEF(Ptr.getValueType()); in getExtLoad() local
5025 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
5074 SDValue Undef = getUNDEF(Ptr.getValueType()); in getStore() local
5075 SDValue Ops[] = { Chain, Val, Ptr, Undef }; in getStore()
[all …]
/NextBSD/contrib/llvm/include/llvm/IR/
HDIRBuilder.h1604 Value *Undef = UndefValue::get(VectorType::get(V->getType(), NumElts)); variable
1605 V = CreateInsertElement(Undef, V, ConstantInt::get(I32Ty, 0),
1610 return CreateShuffleVector(V, Undef, Zeros, Name + ".splat");
/NextBSD/contrib/llvm/lib/CodeGen/
HDIfConversion.cpp1025 MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef); in UpdatePredRedefs()
1042 MIB.addReg(Reg.first, RegState::Implicit | RegState::Undef); in UpdatePredRedefs()
/NextBSD/contrib/llvm/tools/clang/lib/CodeGen/
HDCodeGenFunction.cpp668 llvm::Value *Undef = llvm::UndefValue::get(Int32Ty); in StartFunction() local
669 AllocaInsertPt = new llvm::BitCastInst(Undef, Int32Ty, "", EntryBB); in StartFunction()
HDCGBuiltin.cpp6653 Value *Undef = ConstantInt::get(Builder.getInt1Ty(), false); in EmitPPCBuiltinExpr() local
6655 return Builder.CreateCall(F, {X, Undef}); in EmitPPCBuiltinExpr()
6911 Value *Undef = ConstantInt::get(Builder.getInt1Ty(), false); in EmitSystemZBuiltinExpr() local
6913 return Builder.CreateCall(F, {X, Undef}); in EmitSystemZBuiltinExpr()
6922 Value *Undef = ConstantInt::get(Builder.getInt1Ty(), false); in EmitSystemZBuiltinExpr() local
6924 return Builder.CreateCall(F, {X, Undef}); in EmitSystemZBuiltinExpr()
HDItaniumCXXABI.cpp1555 RValue Undef = RValue::get(llvm::UndefValue::get(T)); in EmitReturnFromThunk() local
1556 return ItaniumCXXABI::EmitReturnFromThunk(CGF, Undef, ResultType); in EmitReturnFromThunk()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrInfo.cpp2521 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit) in classifyLEAReg()
4721 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); in Expand2AddrUndef()
5217 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); in breakPartialRegDependency()
5223 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) in breakPartialRegDependency()
HDX86ISelDAGToDAG.cpp1930 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectAtomicLoadArith() local
1932 SDValue RetVals[] = { Undef, Ret }; in SelectAtomicLoadArith()
HDX86ISelLowering.cpp4277 SDValue Undef = DAG.getUNDEF(ResultVT); in Insert128BitVector() local
4278 SDValue Vec256 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Undef, in Insert128BitVector()
6239 SDValue Undef = DAG.getUNDEF(ResVT); in LowerCONCAT_VECTORSvXi1() local
6243 V2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V2, ZeroIdx); in LowerCONCAT_VECTORSvXi1()
6248 V1 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResVT, Undef, V1, ZeroIdx); in LowerCONCAT_VECTORSvXi1()
11225 SDValue Undef = DAG.getUNDEF(OpVT); in LowerINSERT_SUBVECTOR() local
11234 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, in LowerINSERT_SUBVECTOR()
11240 SDValue Vec2 = DAG.getNode(ISD::INSERT_SUBVECTOR, dl, OpVT, Undef, in LowerINSERT_SUBVECTOR()
12361 SDValue Undef = DAG.getUNDEF(InVT); in LowerAVXExtend() local
12363 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef); in LowerAVXExtend()
[all …]
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.cpp1545 .addReg(SrcRegX, RegState::Undef) in copyPhysReg()
1571 .addReg(SrcRegX, RegState::Undef) in copyPhysReg()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrInfo.cpp183 .addReg(DestReg, RegState::Undef) in emitGRX32Move()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsISelLowering.cpp2184 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); in lowerLOAD() local
2194 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, in lowerLOAD()
2200 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, in lowerLOAD()
/NextBSD/contrib/llvm/lib/Transforms/Vectorize/
HDSLPVectorizer.cpp2570 Value *Undef = UndefValue::get(Ty); in vectorizeTree() local
2571 Scalar->replaceAllUsesWith(Undef); in vectorizeTree()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMExpandPseudoInsts.cpp1079 .addReg(ARM::CPSR, RegState::Undef); in ExpandMI()

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