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Searched refs:UNINDEXED (Results 1 – 15 of 15) sorted by relevance

/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h762 UNINDEXED = 0, enumerator
HDSelectionDAGNodes.h1931 bool isIndexed() const { return getAddressingMode() != ISD::UNINDEXED; }
1934 bool isUnindexed() const { return getAddressingMode() == ISD::UNINDEXED; }
2247 Ld->getAddressingMode() == ISD::UNINDEXED;
2277 cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
2285 St->getAddressingMode() == ISD::UNINDEXED;
2301 cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonISelDAGToDAG.cpp467 if (AM != ISD::UNINDEXED) { in SelectLoad()
558 if (AM != ISD::UNINDEXED) { in SelectStore()
598 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()
624 LD->getAddressingMode() != ISD::UNINDEXED) { in SelectMul()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAG.cpp4960 bool Indexed = AM != ISD::UNINDEXED; in getLoad()
4995 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
5004 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
5015 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
5025 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
5079 ID.AddInteger(encodeMemSDNodeFlags(false, ISD::UNINDEXED, MMO->isVolatile(), in getStore()
5089 ISD::UNINDEXED, false, VT, MMO); in getStore()
5148 ID.AddInteger(encodeMemSDNodeFlags(true, ISD::UNINDEXED, MMO->isVolatile(), in getTruncStore()
5158 ISD::UNINDEXED, true, SVT, MMO); in getTruncStore()
5201 ID.AddInteger(encodeMemSDNodeFlags(ExtTy, ISD::UNINDEXED, in getMaskedLoad()
[all …]
HDLegalizeVectorTypes.cpp219 SDValue Result = DAG.getLoad(ISD::UNINDEXED, in ScalarizeVecRes_LOAD()
975 Lo = DAG.getLoad(ISD::UNINDEXED, ExtType, LoVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
982 Hi = DAG.getLoad(ISD::UNINDEXED, ExtType, HiVT, dl, Ch, Ptr, Offset, in SplitVecRes_LOAD()
HDLegalizeDAG.cpp294 assert(ST->getAddressingMode() == ISD::UNINDEXED && in ExpandUnalignedStore()
422 assert(LD->getAddressingMode() == ISD::UNINDEXED && in ExpandUnalignedLoad()
HDDAGCombiner.cpp9200 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPreIndexedLoadStore()
9427 ISD::MemIndexedMode AM = ISD::UNINDEXED; in CombineToPostIndexedLoadStore()
9508 assert(AM != ISD::UNINDEXED); in SplitIndexingFromLoad()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetSelectionDAG.td675 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
785 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED;
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIISelLowering.cpp467 SDValue Load = DAG.getLoad(ISD::UNINDEXED, ISD::ZEXTLOAD, in LowerParameter()
482 return DAG.getLoad(ISD::UNINDEXED, ExtTy, in LowerParameter()
HDSIInstrInfo.td141 return cast<LoadSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
179 return cast<StoreSDNode>(N)->getAddressingMode() == ISD::UNINDEXED &&
HDR600ISelLowering.cpp1690 SDValue Arg = DAG.getLoad(ISD::UNINDEXED, Ext, VT, DL, Chain, in LowerFormalArguments()
HDAMDGPUISelLowering.cpp2404 SDValue NewLoad = DAG.getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, in performStoreCombine()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrFragmentsSIMD.td620 ST->getAddressingMode() == ISD::UNINDEXED &&
HDX86ISelDAGToDAG.cpp436 LD->getAddressingMode() != ISD::UNINDEXED || in isCalleeLoad()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelDAGToDAG.cpp1472 if (AM == ISD::UNINDEXED) in SelectARMIndexedLoad()
1545 if (AM == ISD::UNINDEXED) in SelectT2IndexedLoad()