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Searched refs:UMULO (Results 1 – 11 of 11) sorted by relevance

/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDISDOpcodes.h234 SMULO, UMULO, enumerator
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAGDumper.cpp222 case ISD::UMULO: return "umulo"; in getOperationName()
HDLegalizeIntegerTypes.cpp127 case ISD::UMULO: Res = PromoteIntRes_XMULO(N, ResNo); break; in PromoteIntegerResult()
748 if (N->getOpcode() == ISD::UMULO) { in PromoteIntRes_XMULO()
1342 case ISD::UMULO: in ExpandIntegerResult()
2399 if (N->getOpcode() == ISD::UMULO) { in ExpandIntRes_XMULO()
HDSelectionDAG.cpp2126 case ISD::UMULO: in computeKnownBits()
2581 case ISD::UMULO: in ComputeNumSignBits()
HDLegalizeDAG.cpp3739 case ISD::UMULO: in ExpandNode()
HDSelectionDAGBuilder.cpp4863 case Intrinsic::umul_with_overflow: Op = ISD::UMULO; break; in visitIntrinsicCall()
HDDAGCombiner.cpp1343 case ISD::UMULO: return visitUMULO(N); in visit()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelLowering.cpp1560 setOperationAction(ISD::UMULO, MVT::i64, Custom); in SparcTargetLowering()
2735 assert((opcode == ISD::UMULO || opcode == ISD::SMULO) && "Invalid Opcode."); in LowerUMULO_SMULO()
2841 case ISD::UMULO: in LowerOperation()
/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp829 setOperationAction(ISD::UMULO, VT, Expand); in initActions()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64ISelLowering.cpp273 setOperationAction(ISD::UMULO, MVT::i32, Custom); in AArch64TargetLowering()
274 setOperationAction(ISD::UMULO, MVT::i64, Custom); in AArch64TargetLowering()
1306 case ISD::UMULO: { in getAArch64XALUOOp()
1976 case ISD::UMULO: in LowerOperation()
3283 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerBR_CC()
3762 Opc == ISD::USUBO || Opc == ISD::SMULO || Opc == ISD::UMULO)) { in LowerSELECT()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp1615 setOperationAction(ISD::UMULO, VT, Custom); in X86TargetLowering()
14105 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerSELECT()
14117 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerSELECT()
14121 if (CondOpcode == ISD::UMULO) in LowerSELECT()
14129 if (CondOpcode == ISD::UMULO) in LowerSELECT()
14608 Cond.getOperand(0).getOpcode() == ISD::UMULO)) { in LowerBRCOND()
14663 ((CondOpcode == ISD::UMULO || CondOpcode == ISD::SMULO) && in LowerBRCOND()
14690 case ISD::UMULO: X86Opcode = X86ISD::UMUL; X86Cond = X86::COND_O; break; in LowerBRCOND()
14696 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
14704 if (CondOpcode == ISD::UMULO) in LowerBRCOND()
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