1 /*- 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD$ 33 */ 34 35 struct tl_type { 36 u_int16_t tl_vid; 37 u_int16_t tl_did; 38 const char *tl_name; 39 }; 40 41 /* 42 * ThunderLAN TX/RX list format. The TX and RX lists are pretty much 43 * identical: the list begins with a 32-bit forward pointer which points 44 * at the next list in the chain, followed by 16 bits for the total 45 * frame size, and a 16 bit status field. This is followed by a series 46 * of 10 32-bit data count/data address pairs that point to the fragments 47 * that make up the complete frame. 48 */ 49 50 #define TL_MAXFRAGS 10 51 #define TL_RX_LIST_CNT 64 52 #define TL_TX_LIST_CNT 128 53 #define TL_MIN_FRAMELEN 64 54 55 struct tl_frag { 56 u_int32_t tlist_dcnt; 57 u_int32_t tlist_dadr; 58 }; 59 60 struct tl_list { 61 u_int32_t tlist_fptr; /* phys address of next list */ 62 u_int16_t tlist_cstat; /* status word */ 63 u_int16_t tlist_frsize; /* size of data in frame */ 64 struct tl_frag tl_frag[TL_MAXFRAGS]; 65 }; 66 67 /* 68 * This is a special case of an RX list. By setting the One_Frag 69 * bit in the NETCONFIG register, the driver can force the ThunderLAN 70 * chip to use only one fragment when DMAing RX frames. 71 */ 72 73 struct tl_list_onefrag { 74 u_int32_t tlist_fptr; 75 u_int16_t tlist_cstat; 76 u_int16_t tlist_frsize; 77 struct tl_frag tl_frag; 78 }; 79 80 struct tl_list_data { 81 struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT]; 82 struct tl_list tl_tx_list[TL_TX_LIST_CNT]; 83 unsigned char tl_pad[TL_MIN_FRAMELEN]; 84 }; 85 86 struct tl_chain { 87 struct tl_list *tl_ptr; 88 struct mbuf *tl_mbuf; 89 struct tl_chain *tl_next; 90 }; 91 92 struct tl_chain_onefrag { 93 struct tl_list_onefrag *tl_ptr; 94 struct mbuf *tl_mbuf; 95 struct tl_chain_onefrag *tl_next; 96 }; 97 98 struct tl_chain_data { 99 struct tl_chain_onefrag tl_rx_chain[TL_RX_LIST_CNT]; 100 struct tl_chain tl_tx_chain[TL_TX_LIST_CNT]; 101 102 struct tl_chain_onefrag *tl_rx_head; 103 struct tl_chain_onefrag *tl_rx_tail; 104 105 struct tl_chain *tl_tx_head; 106 struct tl_chain *tl_tx_tail; 107 struct tl_chain *tl_tx_free; 108 }; 109 110 struct tl_softc { 111 struct ifnet *tl_ifp; 112 device_t tl_dev; 113 struct ifmedia ifmedia; /* media info */ 114 void *tl_intrhand; 115 struct resource *tl_irq; 116 struct resource *tl_res; 117 device_t tl_miibus; 118 u_int8_t tl_eeaddr; 119 struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */ 120 struct tl_chain_data tl_cdata; 121 u_int8_t tl_txeoc; 122 u_int8_t tl_bitrate; 123 int tl_if_flags; 124 struct callout tl_stat_callout; 125 struct mtx tl_mtx; 126 int tl_timer; 127 }; 128 129 #define TL_LOCK(_sc) mtx_lock(&(_sc)->tl_mtx) 130 #define TL_UNLOCK(_sc) mtx_unlock(&(_sc)->tl_mtx) 131 #define TL_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tl_mtx, MA_OWNED) 132 133 /* 134 * Transmit interrupt threshold. 135 */ 136 #define TX_THR 0x00000004 137 138 /* 139 * General constants that are fun to know. 140 * 141 * The ThunderLAN controller is made by Texas Instruments. The 142 * manual indicates that if the EEPROM checksum fails, the PCI 143 * vendor and device ID registers will be loaded with TI-specific 144 * values. 145 */ 146 #define TI_VENDORID 0x104C 147 #define TI_DEVICEID_THUNDERLAN 0x0500 148 149 /* 150 * These are the PCI vendor and device IDs for Compaq ethernet 151 * adapters based on the ThunderLAN controller. 152 */ 153 #define COMPAQ_VENDORID 0x0E11 154 #define COMPAQ_DEVICEID_NETEL_10_100 0xAE32 155 #define COMPAQ_DEVICEID_NETEL_UNKNOWN 0xAE33 156 #define COMPAQ_DEVICEID_NETEL_10 0xAE34 157 #define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35 158 #define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40 159 #define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43 160 #define COMPAQ_DEVICEID_NETEL_10_100_EMBEDDED 0xB011 161 #define COMPAQ_DEVICEID_NETEL_10_T2_UTP_COAX 0xB012 162 #define COMPAQ_DEVICEID_NETEL_10_100_TX_UTP 0xB030 163 #define COMPAQ_DEVICEID_NETFLEX_3P 0xF130 164 #define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150 165 166 /* 167 * These are the PCI vendor and device IDs for Olicom 168 * adapters based on the ThunderLAN controller. 169 */ 170 #define OLICOM_VENDORID 0x108D 171 #define OLICOM_DEVICEID_OC2183 0x0013 172 #define OLICOM_DEVICEID_OC2325 0x0012 173 #define OLICOM_DEVICEID_OC2326 0x0014 174 175 /* 176 * PCI low memory base and low I/O base 177 */ 178 #define TL_PCI_LOIO 0x10 179 #define TL_PCI_LOMEM 0x14 180 181 /* 182 * PCI latency timer (it's actually 0x0D, but we want a value 183 * that's longword aligned). 184 */ 185 #define TL_PCI_LATENCY_TIMER 0x0C 186 187 #define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */ 188 #define TL_DIO_RAM_SEL 0x4000 /* RAM address select */ 189 #define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */ 190 191 /* 192 * Interrupt types 193 */ 194 #define TL_INTR_INVALID 0x0 195 #define TL_INTR_TXEOF 0x1 196 #define TL_INTR_STATOFLOW 0x2 197 #define TL_INTR_RXEOF 0x3 198 #define TL_INTR_DUMMY 0x4 199 #define TL_INTR_TXEOC 0x5 200 #define TL_INTR_ADCHK 0x6 201 #define TL_INTR_RXEOC 0x7 202 203 #define TL_INT_MASK 0x001C 204 #define TL_VEC_MASK 0x1FE0 205 206 /* 207 * Host command register bits 208 */ 209 #define TL_CMD_GO 0x80000000 210 #define TL_CMD_STOP 0x40000000 211 #define TL_CMD_ACK 0x20000000 212 #define TL_CMD_CHSEL7 0x10000000 213 #define TL_CMD_CHSEL6 0x08000000 214 #define TL_CMD_CHSEL5 0x04000000 215 #define TL_CMD_CHSEL4 0x02000000 216 #define TL_CMD_CHSEL3 0x01000000 217 #define TL_CMD_CHSEL2 0x00800000 218 #define TL_CMD_CHSEL1 0x00400000 219 #define TL_CMD_CHSEL0 0x00200000 220 #define TL_CMD_EOC 0x00100000 221 #define TL_CMD_RT 0x00080000 222 #define TL_CMD_NES 0x00040000 223 #define TL_CMD_ZERO0 0x00020000 224 #define TL_CMD_ZERO1 0x00010000 225 #define TL_CMD_ADRST 0x00008000 226 #define TL_CMD_LDTMR 0x00004000 227 #define TL_CMD_LDTHR 0x00002000 228 #define TL_CMD_REQINT 0x00001000 229 #define TL_CMD_INTSOFF 0x00000800 230 #define TL_CMD_INTSON 0x00000400 231 #define TL_CMD_RSVD0 0x00000200 232 #define TL_CMD_RSVD1 0x00000100 233 #define TL_CMD_ACK7 0x00000080 234 #define TL_CMD_ACK6 0x00000040 235 #define TL_CMD_ACK5 0x00000020 236 #define TL_CMD_ACK4 0x00000010 237 #define TL_CMD_ACK3 0x00000008 238 #define TL_CMD_ACK2 0x00000004 239 #define TL_CMD_ACK1 0x00000002 240 #define TL_CMD_ACK0 0x00000001 241 242 #define TL_CMD_CHSEL_MASK 0x01FE0000 243 #define TL_CMD_ACK_MASK 0xFF 244 245 /* 246 * EEPROM address where station address resides. 247 */ 248 #define TL_EEPROM_EADDR 0x83 249 #define TL_EEPROM_EADDR2 0x99 250 #define TL_EEPROM_EADDR3 0xAF 251 #define TL_EEPROM_EADDR_OC 0xF8 /* Olicom cards use a different 252 address than Compaqs. */ 253 /* 254 * ThunderLAN host command register offsets. 255 * (Can be accessed either by IO ports or memory map.) 256 */ 257 #define TL_HOSTCMD 0x00 258 #define TL_CH_PARM 0x04 259 #define TL_DIO_ADDR 0x08 260 #define TL_HOST_INT 0x0A 261 #define TL_DIO_DATA 0x0C 262 263 /* 264 * ThunderLAN internal registers 265 */ 266 #define TL_NETCMD 0x00 267 #define TL_NETSIO 0x01 268 #define TL_NETSTS 0x02 269 #define TL_NETMASK 0x03 270 271 #define TL_NETCONFIG 0x04 272 #define TL_MANTEST 0x06 273 274 #define TL_VENID_LSB 0x08 275 #define TL_VENID_MSB 0x09 276 #define TL_DEVID_LSB 0x0A 277 #define TL_DEVID_MSB 0x0B 278 279 #define TL_REVISION 0x0C 280 #define TL_SUBCLASS 0x0D 281 #define TL_MINLAT 0x0E 282 #define TL_MAXLAT 0x0F 283 284 #define TL_AREG0_B5 0x10 285 #define TL_AREG0_B4 0x11 286 #define TL_AREG0_B3 0x12 287 #define TL_AREG0_B2 0x13 288 289 #define TL_AREG0_B1 0x14 290 #define TL_AREG0_B0 0x15 291 #define TL_AREG1_B5 0x16 292 #define TL_AREG1_B4 0x17 293 294 #define TL_AREG1_B3 0x18 295 #define TL_AREG1_B2 0x19 296 #define TL_AREG1_B1 0x1A 297 #define TL_AREG1_B0 0x1B 298 299 #define TL_AREG2_B5 0x1C 300 #define TL_AREG2_B4 0x1D 301 #define TL_AREG2_B3 0x1E 302 #define TL_AREG2_B2 0x1F 303 304 #define TL_AREG2_B1 0x20 305 #define TL_AREG2_B0 0x21 306 #define TL_AREG3_B5 0x22 307 #define TL_AREG3_B4 0x23 308 309 #define TL_AREG3_B3 0x24 310 #define TL_AREG3_B2 0x25 311 #define TL_AREG3_B1 0x26 312 #define TL_AREG3_B0 0x27 313 314 #define TL_HASH1 0x28 315 #define TL_HASH2 0x2C 316 #define TL_TXGOODFRAMES 0x30 317 #define TL_TXUNDERRUN 0x33 318 #define TL_RXGOODFRAMES 0x34 319 #define TL_RXOVERRUN 0x37 320 #define TL_DEFEREDTX 0x38 321 #define TL_CRCERROR 0x3A 322 #define TL_CODEERROR 0x3B 323 #define TL_MULTICOLTX 0x3C 324 #define TL_SINGLECOLTX 0x3E 325 #define TL_EXCESSIVECOL 0x40 326 #define TL_LATECOL 0x41 327 #define TL_CARRIERLOSS 0x42 328 #define TL_ACOMMIT 0x43 329 #define TL_LDREG 0x44 330 #define TL_BSIZEREG 0x45 331 #define TL_MAXRX 0x46 332 333 /* 334 * ThunderLAN SIO register bits 335 */ 336 #define TL_SIO_MINTEN 0x80 337 #define TL_SIO_ECLOK 0x40 338 #define TL_SIO_ETXEN 0x20 339 #define TL_SIO_EDATA 0x10 340 #define TL_SIO_NMRST 0x08 341 #define TL_SIO_MCLK 0x04 342 #define TL_SIO_MTXEN 0x02 343 #define TL_SIO_MDATA 0x01 344 345 /* 346 * Thunderlan NETCONFIG bits 347 */ 348 #define TL_CFG_RCLKTEST 0x8000 349 #define TL_CFG_TCLKTEST 0x4000 350 #define TL_CFG_BITRATE 0x2000 351 #define TL_CFG_RXCRC 0x1000 352 #define TL_CFG_PEF 0x0800 353 #define TL_CFG_ONEFRAG 0x0400 354 #define TL_CFG_ONECHAN 0x0200 355 #define TL_CFG_MTEST 0x0100 356 #define TL_CFG_PHYEN 0x0080 357 #define TL_CFG_MACSEL6 0x0040 358 #define TL_CFG_MACSEL5 0x0020 359 #define TL_CFG_MACSEL4 0x0010 360 #define TL_CFG_MACSEL3 0x0008 361 #define TL_CFG_MACSEL2 0x0004 362 #define TL_CFG_MACSEL1 0x0002 363 #define TL_CFG_MACSEL0 0x0001 364 365 /* 366 * ThunderLAN NETSTS bits 367 */ 368 #define TL_STS_MIRQ 0x80 369 #define TL_STS_HBEAT 0x40 370 #define TL_STS_TXSTOP 0x20 371 #define TL_STS_RXSTOP 0x10 372 373 /* 374 * ThunderLAN NETCMD bits 375 */ 376 #define TL_CMD_NRESET 0x80 377 #define TL_CMD_NWRAP 0x40 378 #define TL_CMD_CSF 0x20 379 #define TL_CMD_CAF 0x10 380 #define TL_CMD_NOBRX 0x08 381 #define TL_CMD_DUPLEX 0x04 382 #define TL_CMD_TRFRAM 0x02 383 #define TL_CMD_TXPACE 0x01 384 385 /* 386 * ThunderLAN NETMASK bits 387 */ 388 #define TL_MASK_MASK7 0x80 389 #define TL_MASK_MASK6 0x40 390 #define TL_MASK_MASK5 0x20 391 #define TL_MASK_MASK4 0x10 392 393 #define TL_LAST_FRAG 0x80000000 394 #define TL_CSTAT_UNUSED 0x8000 395 #define TL_CSTAT_FRAMECMP 0x4000 396 #define TL_CSTAT_READY 0x3000 397 #define TL_CSTAT_UNUSED13 0x2000 398 #define TL_CSTAT_UNUSED12 0x1000 399 #define TL_CSTAT_EOC 0x0800 400 #define TL_CSTAT_RXERROR 0x0400 401 #define TL_CSTAT_PASSCRC 0x0200 402 #define TL_CSTAT_DPRIO 0x0100 403 404 #define TL_FRAME_MASK 0x00FFFFFF 405 #define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK) 406 #define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24) 407 #define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK) 408 #define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24) 409 410 struct tl_stats { 411 u_int32_t tl_txstat; 412 u_int32_t tl_rxstat; 413 u_int16_t tl_deferred; 414 u_int8_t tl_crc_errors; 415 u_int8_t tl_code_errors; 416 u_int16_t tl_tx_multi_collision; 417 u_int16_t tl_tx_single_collision; 418 u_int8_t tl_excessive_collision; 419 u_int8_t tl_late_collision; 420 u_int8_t tl_carrier_loss; 421 u_int8_t acommit; 422 }; 423 424 /* 425 * ACOMMIT register bits. These are used only when a bitrate 426 * PHY is selected ('bitrate' bit in netconfig register is set). 427 */ 428 #define TL_AC_MTXER 0x01 /* reserved */ 429 #define TL_AC_MTXD1 0x02 /* 0 == 10baseT 1 == AUI */ 430 #define TL_AC_MTXD2 0x04 /* loopback disable */ 431 #define TL_AC_MTXD3 0x08 /* full duplex disable */ 432 433 #define TL_AC_TXTHRESH 0xF0 434 #define TL_AC_TXTHRESH_16LONG 0x00 435 #define TL_AC_TXTHRESH_32LONG 0x10 436 #define TL_AC_TXTHRESH_64LONG 0x20 437 #define TL_AC_TXTHRESH_128LONG 0x30 438 #define TL_AC_TXTHRESH_256LONG 0x40 439 #define TL_AC_TXTHRESH_WHOLEPKT 0x50 440 441 /* 442 * PCI burst size register (TL_BSIZEREG). 443 */ 444 #define TL_RXBURST 0x0F 445 #define TL_TXBURST 0xF0 446 447 #define TL_RXBURST_4LONG 0x00 448 #define TL_RXBURST_8LONG 0x01 449 #define TL_RXBURST_16LONG 0x02 450 #define TL_RXBURST_32LONG 0x03 451 #define TL_RXBURST_64LONG 0x04 452 #define TL_RXBURST_128LONG 0x05 453 454 #define TL_TXBURST_4LONG 0x00 455 #define TL_TXBURST_8LONG 0x10 456 #define TL_TXBURST_16LONG 0x20 457 #define TL_TXBURST_32LONG 0x30 458 #define TL_TXBURST_64LONG 0x40 459 #define TL_TXBURST_128LONG 0x50 460 461 /* 462 * register space access macros 463 */ 464 #define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->tl_res, reg, val) 465 #define CSR_WRITE_2(sc, reg, val) bus_write_2(sc->tl_res, reg, val) 466 #define CSR_WRITE_1(sc, reg, val) bus_write_1(sc->tl_res, reg, val) 467 468 #define CSR_READ_4(sc, reg) bus_read_4(sc->tl_res, reg) 469 #define CSR_READ_2(sc, reg) bus_read_2(sc->tl_res, reg) 470 #define CSR_READ_1(sc, reg) bus_read_1(sc->tl_res, reg) 471 472 #define CSR_BARRIER(sc, reg, length, flags) \ 473 bus_barrier(sc->tl_res, reg, length, flags) 474 475 #define CMD_PUT(sc, x) CSR_WRITE_4(sc, TL_HOSTCMD, x) 476 #define CMD_SET(sc, x) \ 477 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) | (x)) 478 #define CMD_CLR(sc, x) \ 479 CSR_WRITE_4(sc, TL_HOSTCMD, CSR_READ_4(sc, TL_HOSTCMD) & ~(x)) 480 481 /* 482 * ThunderLAN adapters typically have a serial EEPROM containing 483 * configuration information. The main reason we're interested in 484 * it is because it also contains the adapters's station address. 485 * 486 * Access to the EEPROM is a bit goofy since it is a serial device: 487 * you have to do reads and writes one bit at a time. The state of 488 * the DATA bit can only change while the CLOCK line is held low. 489 * Transactions work basically like this: 490 * 491 * 1) Send the EEPROM_START sequence to prepare the EEPROM for 492 * accepting commands. This pulls the clock high, sets 493 * the data bit to 0, enables transmission to the EEPROM, 494 * pulls the data bit up to 1, then pulls the clock low. 495 * The idea is to do a 0 to 1 transition of the data bit 496 * while the clock pin is held high. 497 * 498 * 2) To write a bit to the EEPROM, set the TXENABLE bit, then 499 * set the EDATA bit to send a 1 or clear it to send a 0. 500 * Finally, set and then clear ECLOK. Strobing the clock 501 * transmits the bit. After 8 bits have been written, the 502 * EEPROM should respond with an ACK, which should be read. 503 * 504 * 3) To read a bit from the EEPROM, clear the TXENABLE bit, 505 * then set ECLOK. The bit can then be read by reading EDATA. 506 * ECLOCK should then be cleared again. This can be repeated 507 * 8 times to read a whole byte, after which the 508 * 509 * 4) We need to send the address byte to the EEPROM. For this 510 * we have to send the write control byte to the EEPROM to 511 * tell it to accept data. The byte is 0xA0. The EEPROM should 512 * ack this. The address byte can be send after that. 513 * 514 * 5) Now we have to tell the EEPROM to send us data. For that we 515 * have to transmit the read control byte, which is 0xA1. This 516 * byte should also be acked. We can then read the data bits 517 * from the EEPROM. 518 * 519 * 6) When we're all finished, send the EEPROM_STOP sequence. 520 * 521 * Note that we use the ThunderLAN's NetSio register to access the 522 * EEPROM, however there is an alternate method. There is a PCI NVRAM 523 * register at PCI offset 0xB4 which can also be used with minor changes. 524 * The difference is that access to PCI registers via pci_conf_read() 525 * and pci_conf_write() is done using programmed I/O, which we want to 526 * avoid. 527 */ 528 529 /* 530 * Note that EEPROM_START leaves transmission enabled. 531 */ 532 #define EEPROM_START \ 533 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock pin high */\ 534 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Set DATA bit to 1 */ \ 535 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit to write bit */\ 536 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA bit to 0 again */\ 537 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 538 539 /* 540 * EEPROM_STOP ends access to the EEPROM and clears the ETXEN bit so 541 * that no further data can be written to the EEPROM I/O pin. 542 */ 543 #define EEPROM_STOP \ 544 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit */ \ 545 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Pull DATA to 0 */ \ 546 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock high */ \ 547 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Enable xmit */ \ 548 tl_dio_setbit(sc, TL_NETSIO, TL_SIO_EDATA); /* Toggle DATA to 1 */ \ 549 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ETXEN); /* Disable xmit. */ \ 550 tl_dio_clrbit(sc, TL_NETSIO, TL_SIO_ECLOK); /* Pull clock low again */ 551 552 553 /* 554 * Microchip Technology 24Cxx EEPROM control bytes 555 */ 556 #define EEPROM_CTL_READ 0xA1 /* 0101 0001 */ 557 #define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */ 558