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Searched refs:SubReg (Results 1 – 25 of 34) sorted by relevance

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/NextBSD/contrib/llvm/lib/CodeGen/
HDLiveVariables.cpp198 unsigned SubReg = *SubRegs; in FindLastPartialDef() local
199 MachineInstr *Def = PhysRegDef[SubReg]; in FindLastPartialDef()
204 LastDefReg = SubReg; in FindLastPartialDef()
252 unsigned SubReg = *SubRegs; in HandlePhysRegUse() local
253 if (Processed.count(SubReg)) in HandlePhysRegUse()
255 if (PartDefRegs.count(SubReg)) in HandlePhysRegUse()
259 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg, in HandlePhysRegUse()
262 PhysRegDef[SubReg] = LastPartialDef; in HandlePhysRegUse()
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS) in HandlePhysRegUse()
291 unsigned SubReg = *SubRegs; in FindLastRefOrPartRef() local
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HDLiveRangeCalc.cpp65 unsigned SubReg = MO.getSubReg(); in calculate() local
66 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) { in calculate()
67 unsigned Mask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg) in calculate()
158 unsigned SubReg = MO.getSubReg(); in extendToUses() local
159 if (SubReg != 0) { in extendToUses()
160 unsigned SubRegMask = TRI.getSubRegIndexLaneMask(SubReg); in extendToUses()
HDPeepholeOptimizer.cpp144 bool findNextSource(unsigned &Reg, unsigned &SubReg);
544 bool PeepholeOptimizer::findNextSource(unsigned &Reg, unsigned &SubReg) { in findNextSource() argument
553 unsigned DefSubReg = SubReg; in findNextSource()
589 SubReg = SrcSubReg; in findNextSource()
956 if (!findNextSource(Src.Reg, Src.SubReg)) in optimizeUncoalescableCopy()
971 NewVR).addReg(Src.Reg, 0, Src.SubReg); in optimizeUncoalescableCopy()
972 NewCopy->getOperand(0).setSubReg(Def.SubReg); in optimizeUncoalescableCopy()
973 if (Def.SubReg) in optimizeUncoalescableCopy()
1281 if (RegSeqInput.SubReg) in getNextSourceFromRegSequence()
1286 SrcSubReg = RegSeqInput.SubReg; in getNextSourceFromRegSequence()
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HDVirtRegMap.cpp262 unsigned SubReg = SR.getSubReg(); in addMBBLiveIns() local
268 LiveIn[i]->addLiveIn(SubReg); in addMBBLiveIns()
396 unsigned SubReg = MO.getSubReg(); in rewrite() local
397 if (SubReg != 0) { in rewrite()
426 unsigned LaneMask = TRI->getSubRegIndexLaneMask(SubReg); in rewrite()
440 PhysReg = TRI->getSubReg(PhysReg, SubReg); in rewrite()
HDMachineInstrBundle.cpp187 unsigned SubReg = *SubRegs; in finalizeBundle() local
188 if (LocalDefSet.insert(SubReg).second) in finalizeBundle()
189 LocalDefs.push_back(SubReg); in finalizeBundle()
HDLiveIntervalAnalysis.cpp513 unsigned SubReg = MO.getSubReg(); in shrinkToUses() local
514 if (SubReg != 0) { in shrinkToUses()
515 unsigned SubRegMask = TRI->getSubRegIndexLaneMask(SubReg); in shrinkToUses()
946 unsigned SubReg = MO.getSubReg(); in updateAllRanges() local
947 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in updateAllRanges()
1183 unsigned SubReg = MO.getSubReg(); in findLastUseBefore() local
1184 if (SubReg != 0 && LaneMask != 0 in findLastUseBefore()
1185 && (TRI.getSubRegIndexLaneMask(SubReg) & LaneMask) == 0) in findLastUseBefore()
1284 unsigned SubReg = MO.getSubReg(); in repairOldRegInRange() local
1285 unsigned Mask = TRI->getSubRegIndexLaneMask(SubReg); in repairOldRegInRange()
HDLiveRangeEdit.cpp228 unsigned SubReg = MO.getSubReg(); in useIsKill() local
229 unsigned LaneMask = TRI.getSubRegIndexLaneMask(SubReg); in useIsKill()
HDTargetInstrInfo.cpp929 InputReg.SubReg = MOReg.getSubReg(); in getExtractSubregInputs()
952 BaseReg.SubReg = MOBaseReg.getSubReg(); in getInsertSubregInputs()
955 InsertedReg.SubReg = MOInsertedReg.getSubReg(); in getInsertSubregInputs()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64AdvSIMDScalarPass.cpp101 static bool isGPR64(unsigned Reg, unsigned SubReg, in isGPR64() argument
103 if (SubReg) in isGPR64()
110 static bool isFPR64(unsigned Reg, unsigned SubReg, in isFPR64() argument
114 SubReg == 0) || in isFPR64()
116 SubReg == AArch64::dsub); in isFPR64()
118 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) || in isFPR64()
119 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub); in isFPR64()
126 unsigned &SubReg) { in getSrcFromCopy() argument
127 SubReg = 0; in getSrcFromCopy()
135 SubReg = AArch64::dsub; in getSrcFromCopy()
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HDAArch64ISelDAGToDAG.cpp539 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in narrowIfNeeded() local
541 dl, MVT::i32, N, SubReg); in narrowIfNeeded()
703 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in Widen() local
707 TargetOpcode::INSERT_SUBREG, dl, MVT::i64, ImpDef, N, SubReg); in Widen()
1058 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in SelectIndexedLoad() local
1063 SubReg), in SelectIndexedLoad()
1617 SDValue SubReg = CurDAG->getTargetConstant(AArch64::sub_32, dl, MVT::i32); in SelectBitfieldExtractOp() local
1620 SDValue(BFM, 0), SubReg); in SelectBitfieldExtractOp()
2305 unsigned SubReg; in Select() local
2313 SubReg = AArch64::dsub; in Select()
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HDAArch64InstrInfo.cpp1509 int SubReg = 0, End = NumRegs, Incr = 1; in copyPhysRegTuple() local
1511 SubReg = NumRegs - 1; in copyPhysRegTuple()
1516 for (; SubReg != End; SubReg += Incr) { in copyPhysRegTuple()
1518 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI); in copyPhysRegTuple()
1519 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI); in copyPhysRegTuple()
1520 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); in copyPhysRegTuple()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIFixSGPRCopies.cpp91 unsigned SubReg) const;
95 unsigned SubReg) const;
138 unsigned SubReg) const { in inferRegClassFromUses()
145 RC = TRI->getSubRegClass(RC, SubReg); in inferRegClassFromUses()
164 unsigned SubReg) const { in inferRegClassFromDef()
167 return TRI->getSubRegClass(RC, SubReg); in inferRegClassFromDef()
171 return TRI->getSubRegClass(MRI.getRegClass(Reg), SubReg); in inferRegClassFromDef()
HDSIRegisterInfo.cpp174 unsigned SubReg = NumSubRegs > 1 ? in buildScratchLoadStore() local
180 .addReg(SubReg, getDefRegState(IsLoad)) in buildScratchLoadStore()
215 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), in eliminateFrameIndex() local
228 .addReg(SubReg) in eliminateFrameIndex()
245 unsigned SubReg = getPhysRegSubReg(MI->getOperand(0).getReg(), in eliminateFrameIndex() local
257 SubReg) in eliminateFrameIndex()
HDSILowerControlFlow.cpp409 unsigned SubReg = TRI->getSubReg(VecReg, AMDGPU::sub0); in computeIndirectRegAndOffset() local
410 if (!SubReg) in computeIndirectRegAndOffset()
411 SubReg = VecReg; in computeIndirectRegAndOffset()
413 const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg); in computeIndirectRegAndOffset()
414 int RegIdx = TRI->getHWRegIndex(SubReg) + Offset; in computeIndirectRegAndOffset()
HDR600OptimizeVectorRegisters.cpp192 unsigned SubReg = (*It).first; in RebuildVector() local
199 .addReg(SubReg) in RebuildVector()
201 UpdatedRegToChan[SubReg] = Chan; in RebuildVector()
HDSIInstrInfo.cpp826 unsigned SubReg = Src0.getSubReg(); in commuteInstruction() local
833 Src1.setSubReg(SubReg); in commuteInstruction()
1568 unsigned SubReg = MRI.createVirtualRegister(SubRC); in buildExtractSubReg() local
1580 BuildMI(*MBB, MI, DL, get(TargetOpcode::COPY), SubReg) in buildExtractSubReg()
1583 return SubReg; in buildExtractSubReg()
1603 unsigned SubReg = buildExtractSubReg(MII, MRI, Op, SuperRC, in buildExtractSubRegOrImm() local
1605 return MachineOperand::CreateReg(SubReg, false); in buildExtractSubRegOrImm()
/NextBSD/contrib/llvm/lib/MC/
HDMCRegisterInfo.cpp38 unsigned MCRegisterInfo::getSubRegIndex(unsigned Reg, unsigned SubReg) const { in getSubRegIndex()
39 assert(SubReg && SubReg < getNumRegs() && "This is not a register"); in getSubRegIndex()
44 if (*Subs == SubReg) in getSubRegIndex()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCRegisterInfo.td36 class GP8<GPR SubReg, string n> : PPCReg<n> {
37 let HWEncoding = SubReg.HWEncoding;
38 let SubRegs = [SubReg];
53 class QFPR<FPR SubReg, string n> : PPCReg<n> {
54 let HWEncoding = SubReg.HWEncoding;
55 let SubRegs = [SubReg];
67 class VR<VF SubReg, string n> : PPCReg<n> {
68 let HWEncoding{4-0} = SubReg.HWEncoding{4-0};
70 let SubRegs = [SubReg];
76 class VSRL<FPR SubReg, string n> : PPCReg<n> {
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/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetRegisterInfo.h860 unsigned SubReg, in shouldCoalesce() argument
893 unsigned SubReg; variable
904 SubReg(0),
915 unsigned getSubReg() const { return SubReg; } in getSubReg()
925 SubReg = *Idx++;
926 if (!SubReg)
HDTargetInstrInfo.h274 unsigned SubReg; member
275 RegSubRegPair(unsigned Reg = 0, unsigned SubReg = 0)
276 : Reg(Reg), SubReg(SubReg) {} in Reg()
283 RegSubRegPairAndIdx(unsigned Reg = 0, unsigned SubReg = 0,
285 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
/NextBSD/contrib/llvm/lib/CodeGen/MIRParser/
HDMIParser.cpp85 bool parseSubRegisterIndex(unsigned &SubReg);
358 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) { in parseSubRegisterIndex() argument
364 SubReg = getSubRegIndex(Name); in parseSubRegisterIndex()
365 if (!SubReg) in parseSubRegisterIndex()
383 unsigned SubReg = 0; in parseRegisterOperand() local
385 if (parseSubRegisterIndex(SubReg)) in parseRegisterOperand()
391 /*isEarlyClobber=*/false, SubReg); in parseRegisterOperand()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZElimCompare.cpp109 static bool resultTests(MachineInstr *MI, unsigned Reg, unsigned SubReg) { in resultTests() argument
114 MI->getOperand(0).getSubReg() == SubReg) in resultTests()
131 MI->getOperand(1).getSubReg() == SubReg) in resultTests()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMBaseRegisterInfo.h183 unsigned SubReg,
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineOperand.h601 unsigned SubReg = 0,
619 Op.setSubReg(SubReg);
HDMachineInstrBuilder.h69 unsigned SubReg = 0) const {
79 SubReg,

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