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Searched refs:SubIdx (Results 1 – 25 of 46) sorted by relevance

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/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetRegisterInfo.h345 const char *getSubRegIndexName(unsigned SubIdx) const { in getSubRegIndexName() argument
346 assert(SubIdx && SubIdx < getNumSubRegIndices() && in getSubRegIndexName()
348 return SubRegIndexNames[SubIdx-1]; in getSubRegIndexName()
371 unsigned getSubRegIndexLaneMask(unsigned SubIdx) const { in getSubRegIndexLaneMask() argument
372 assert(SubIdx < getNumSubRegIndices() && "This is not a subregister index"); in getSubRegIndexLaneMask()
373 return SubRegIndexLaneMasks[SubIdx]; in getSubRegIndexLaneMask()
489 unsigned getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
491 return MCRegisterInfo::getMatchingSuperReg(Reg, SubIdx, RC->MC); in getMatchingSuperReg()
953 unsigned SubIdx; variable
957 : TRI(tri), Reg(reg), SubIdx(subidx) {} in TRI()
HDTargetInstrInfo.h127 unsigned &SubIdx) const { in isCoalescableExtInstr() argument
206 virtual bool getStackSlotRange(const TargetRegisterClass *RC, unsigned SubIdx,
225 unsigned DestReg, unsigned SubIdx,
282 unsigned SubIdx; member
284 unsigned SubIdx = 0)
285 : RegSubRegPair(Reg, SubReg), SubIdx(SubIdx) {} in RegSubRegPair()
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenRegisters.h349 getSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx) const { in getSubClassWithSubReg() argument
350 return SubClassWithSubReg.lookup(SubIdx); in getSubClassWithSubReg()
353 void setSubClassWithSubReg(const CodeGenSubRegIndex *SubIdx, in setSubClassWithSubReg() argument
355 SubClassWithSubReg[SubIdx] = SubRC; in setSubClassWithSubReg()
360 void getSuperRegClasses(const CodeGenSubRegIndex *SubIdx,
364 void addSuperRegClass(CodeGenSubRegIndex *SubIdx, in addSuperRegClass() argument
366 SuperRegClasses[SubIdx].insert(SuperRC); in addSuperRegClass()
HDCodeGenRegisters.cpp469 CodeGenSubRegIndex *SubIdx = getSubRegIndex(SI->second); in computeSecondarySubRegs() local
470 if (!SubIdx) in computeSecondarySubRegs()
473 NewIdx->addComposite(SI->first, SubIdx); in computeSecondarySubRegs()
899 void CodeGenRegisterClass::getSuperRegClasses(const CodeGenSubRegIndex *SubIdx, in getSuperRegClasses() argument
901 auto FindI = SuperRegClasses.find(SubIdx); in getSuperRegClasses()
1555 for (unsigned SubIdx = 0, EndIdx = RegUnitSets.size(); in pruneUnitSets() local
1556 SubIdx != EndIdx; ++SubIdx) { in pruneUnitSets()
1557 const RegUnitSet &SubSet = RegUnitSets[SubIdx]; in pruneUnitSets()
1560 if (SuperIdx == SubIdx) in pruneUnitSets()
1569 DEBUG(dbgs() << "UnitSet " << SubIdx << " subsumed by " << SuperIdx in pruneUnitSets()
[all …]
/NextBSD/contrib/llvm/lib/CodeGen/
HDPeepholeOptimizer.cpp318 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
319 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
333 DstRC = TRI->getSubClassWithSubReg(DstRC, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
343 TRI->getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != nullptr; in INITIALIZE_PASS_DEPENDENCY()
369 if (UseSrcSubIdx && UseMO.getSubReg() != SubIdx) in INITIALIZE_PASS_DEPENDENCY()
446 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
449 Copy->getOperand(0).setSubReg(SubIdx); in INITIALIZE_PASS_DEPENDENCY()
1280 if (RegSeqInput.SubIdx == DefSubReg) { in getNextSourceFromRegSequence()
1325 if (InsertedReg.SubIdx == DefSubReg) { in getNextSourceFromInsertSubreg()
1346 TRI->getSubRegIndexLaneMask(InsertedReg.SubIdx)) != 0) in getNextSourceFromInsertSubreg()
[all …]
HDExpandPostRAPseudos.cpp90 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg() local
92 assert(SubIdx != 0 && "Invalid index for insert_subreg"); in LowerSubregToReg()
93 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
HDTargetInstrInfo.cpp294 unsigned SubIdx, unsigned &Size, in getStackSlotRange() argument
297 if (!SubIdx) { in getStackSlotRange()
303 unsigned BitSize = TRI->getSubRegIdxSize(SubIdx); in getStackSlotRange()
309 int BitOffset = TRI->getSubRegIdxOffset(SubIdx); in getStackSlotRange()
327 unsigned SubIdx, in reMaterialize() argument
331 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
930 InputReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getExtractSubregInputs()
956 InsertedReg.SubIdx = (unsigned)MOSubIdx.getImm(); in getInsertSubregInputs()
HDTargetRegisterInfo.cpp48 if (SubIdx) { in print()
50 OS << ':' << TRI->getSubRegIndexName(SubIdx); in print()
52 OS << ":sub(" << SubIdx << ')'; in print()
HDMachineInstr.cpp70 void MachineOperand::substVirtReg(unsigned Reg, unsigned SubIdx, in substVirtReg() argument
73 if (SubIdx && getSubReg()) in substVirtReg()
74 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg()); in substVirtReg()
76 if (SubIdx) in substVirtReg()
77 setSubReg(SubIdx); in substVirtReg()
1129 if (unsigned SubIdx = MO.getSubReg()) { in getRegClassConstraintEffect() local
1131 CurRC = TRI->getMatchingSuperRegClass(CurRC, OpRC, SubIdx); in getRegClassConstraintEffect()
1133 CurRC = TRI->getSubClassWithSubReg(CurRC, SubIdx); in getRegClassConstraintEffect()
1355 unsigned SubIdx, in substituteRegister() argument
1358 if (SubIdx) in substituteRegister()
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HDMachineCopyPropagation.cpp120 unsigned SubIdx = TRI->getSubRegIndex(SrcSrc, Def); in isNopCopy() local
121 if (!SubIdx) in isNopCopy()
123 return SubIdx == TRI->getSubRegIndex(SrcDef, Src); in isNopCopy()
HDRegisterCoalescer.cpp207 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
1174 unsigned SubIdx) { in updateRegDefsUses() argument
1198 if (DstInt && !Reads && SubIdx) in updateRegDefsUses()
1208 if (SubIdx && MO.isDef()) in updateRegDefsUses()
1213 if (SubIdx != 0 && MO.isUse() && MRI->shouldTrackSubRegLiveness(DstReg)) { in updateRegDefsUses()
1219 unsigned Mask = TRI->getSubRegIndexLaneMask(SubIdx); in updateRegDefsUses()
1248 MO.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
1644 const unsigned SubIdx; member in __anon44ea2fb90211::JoinVals
1799 JoinVals(LiveRange &LR, unsigned Reg, unsigned SubIdx, unsigned LaneMask, in JoinVals() argument
1803 : LR(LR), Reg(Reg), SubIdx(SubIdx), LaneMask(LaneMask), in JoinVals()
[all …]
HDLiveDebugVariables.h49 void renameRegister(unsigned OldReg, unsigned NewReg, unsigned SubIdx);
HDMachineVerifier.cpp902 unsigned SubIdx = MO->getSubReg(); in visitMachineOperand() local
905 if (SubIdx) { in visitMachineOperand()
920 if (SubIdx) { in visitMachineOperand()
922 TRI->getSubClassWithSubReg(RC, SubIdx); in visitMachineOperand()
926 << " does not support subreg index " << SubIdx << "\n"; in visitMachineOperand()
932 << " does not fully support subreg index " << SubIdx << "\n"; in visitMachineOperand()
938 if (SubIdx) { in visitMachineOperand()
945 DRC = TRI->getMatchingSuperRegClass(SuperRC, DRC, SubIdx); in visitMachineOperand()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIMachineFunctionInfo.cpp40 unsigned SubIdx) { in getSpilledReg() argument
46 Offset += SubIdx * 4; in getSpilledReg()
HDSILoadStoreOptimizer.cpp74 unsigned SubIdx);
198 unsigned SubIdx) { in updateRegDefsUses() argument
203 O.substVirtReg(DstReg, SubIdx, *TRI); in updateRegDefsUses()
HDSIMachineFunctionInfo.h48 unsigned SubIdx);
HDSIRegisterInfo.h80 unsigned SubIdx) const;
HDSIInstrInfo.h33 unsigned SubIdx,
39 unsigned SubIdx,
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDInstrEmitter.cpp442 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() argument
445 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx); in ConstrainForSubReg()
458 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()
491 unsigned SubIdx = cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue(); in EmitSubregNode() local
500 SubIdx == DefSubIdx && in EmitSubregNode()
515 VReg = ConstrainForSubReg(VReg, SubIdx, in EmitSubregNode()
525 TII->get(TargetOpcode::COPY), VRBase).addReg(VReg, 0, SubIdx); in EmitSubregNode()
532 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode() local
549 SRC = TRI->getSubClassWithSubReg(SRC, SubIdx); in EmitSubregNode()
570 MIB.addImm(SubIdx); in EmitSubregNode()
[all …]
HDInstrEmitter.h86 unsigned ConstrainForSubReg(unsigned VReg, unsigned SubIdx,
/NextBSD/contrib/llvm/lib/Target/ARM/
HDThumbRegisterInfo.cpp65 unsigned SubIdx, int Val, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
85 unsigned SubIdx, int Val, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 unsigned DestReg, unsigned SubIdx, int Val, ARMCC::CondCodes Pred, in emitLoadConstPool() argument
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
HDThumbRegisterInfo.h42 DebugLoc dl, unsigned DestReg, unsigned SubIdx, int Val,
/NextBSD/contrib/llvm/lib/MC/
HDMCRegisterInfo.cpp18 unsigned MCRegisterInfo::getMatchingSuperReg(unsigned Reg, unsigned SubIdx, in getMatchingSuperReg() argument
21 if (RC->contains(*Supers) && Reg == getSubReg(*Supers, SubIdx)) in getMatchingSuperReg()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrInfo.cpp192 unsigned &SubIdx) const { in isCoalescableExtInstr()
199 SubIdx = PPC::sub_32; in isCoalescableExtInstr()
690 unsigned SubIdx; in insertSelect() local
694 case PPC::PRED_EQ: SubIdx = PPC::sub_eq; SwapOps = false; break; in insertSelect()
695 case PPC::PRED_NE: SubIdx = PPC::sub_eq; SwapOps = true; break; in insertSelect()
696 case PPC::PRED_LT: SubIdx = PPC::sub_lt; SwapOps = false; break; in insertSelect()
697 case PPC::PRED_GE: SubIdx = PPC::sub_lt; SwapOps = true; break; in insertSelect()
698 case PPC::PRED_GT: SubIdx = PPC::sub_gt; SwapOps = false; break; in insertSelect()
699 case PPC::PRED_LE: SubIdx = PPC::sub_gt; SwapOps = true; break; in insertSelect()
700 case PPC::PRED_UN: SubIdx = PPC::sub_un; SwapOps = false; break; in insertSelect()
[all …]
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrInfo.h210 unsigned &SubIdx) const override;
231 unsigned DestReg, unsigned SubIdx,

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