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Searched refs:SrcRC (Results 1 – 22 of 22) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSILowerI1Copies.cpp107 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src.getReg()); in runOnMachineFunction() local
110 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) { in runOnMachineFunction()
137 SrcRC == &AMDGPU::VReg_1RegClass) { in runOnMachineFunction()
HDSIFixSGPRCopies.cpp194 const TargetRegisterClass *SrcRC; in isVGPRToSGPRCopy() local
200 SrcRC = TRI->getSubRegClass(MRI.getRegClass(SrcReg), SrcSubReg); in isVGPRToSGPRCopy()
201 return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC); in isVGPRToSGPRCopy()
HDSIInstrInfo.cpp2521 const TargetRegisterClass *SrcRC = Src.isReg() ? in splitScalar64BitBCNT() local
2528 const TargetRegisterClass *SrcSubRC = RI.getSubRegClass(SrcRC, AMDGPU::sub0); in splitScalar64BitBCNT()
2530 MachineOperand SrcRegSub0 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, in splitScalar64BitBCNT()
2532 MachineOperand SrcRegSub1 = buildExtractSubRegOrImm(MII, MRI, Src, SrcRC, in splitScalar64BitBCNT()
/NextBSD/contrib/llvm/lib/CodeGen/
HDPeepholeOptimizer.cpp514 const TargetRegisterClass *SrcRC, in shareSameRegisterFile() argument
517 if (DefRC == SrcRC) in shareSameRegisterFile()
523 return TRI.getCommonSuperRegClass(SrcRC, SrcSubReg, DefRC, DefSubReg, in shareSameRegisterFile()
529 std::swap(DefRC, SrcRC); in shareSameRegisterFile()
534 return TRI.getMatchingSuperRegClass(SrcRC, DefRC, SrcSubReg) != nullptr; in shareSameRegisterFile()
536 return TRI.getCommonSubClass(DefRC, SrcRC) != nullptr; in shareSameRegisterFile()
577 const TargetRegisterClass *SrcRC = MRI->getRegClass(Src); in findNextSource() local
580 ShouldRewrite = shareSameRegisterFile(*TRI, DefRC, DefSubReg, SrcRC, in findNextSource()
HDRegisterCoalescer.cpp358 const TargetRegisterClass *SrcRC = MRI.getRegClass(Src); in setRegisters() local
367 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub, in setRegisters()
374 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub); in setRegisters()
378 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub); in setRegisters()
381 NewRC = TRI.getCommonSubClass(DstRC, SrcRC); in setRegisters()
396 CrossClass = NewRC != DstRC || NewRC != SrcRC; in setRegisters()
1289 auto SrcRC = MRI->getRegClass(CP.getSrcReg()); in joinCopy() local
1295 std::swap(SrcRC, DstRC); in joinCopy()
1297 if (!TRI->shouldCoalesce(CopyMI, SrcRC, SrcIdx, DstRC, DstIdx, in joinCopy()
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsInstrFPU.td121 class ABSS_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
123 InstSE<(outs DstRC:$fd), (ins SrcRC:$fs), !strconcat(opstr, "\t$fd, $fs"),
124 [(set DstRC:$fd, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>,
144 class MFC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
146 InstSE<(outs DstRC:$rt), (ins SrcRC:$fs), !strconcat(opstr, "\t$rt, $fs"),
147 [(set DstRC:$rt, (OpNode SrcRC:$fs))], Itin, FrmFR, opstr>, HARDFLOAT;
149 class MTC1_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
151 InstSE<(outs DstRC:$fs), (ins SrcRC:$rt), !strconcat(opstr, "\t$rt, $fs"),
152 [(set DstRC:$fs, (OpNode SrcRC:$rt))], Itin, FrmFR, opstr>, HARDFLOAT;
154 class MTC1_64_FT<string opstr, RegisterOperand DstRC, RegisterOperand SrcRC,
[all …]
HDMipsInstrInfo.td953 class PseudoMFLOHI<RegisterClass DstRC, RegisterClass SrcRC, SDNode OpNode>
954 : PseudoSE<(outs DstRC:$rd), (ins SrcRC:$hilo),
955 [(set DstRC:$rd, (OpNode SrcRC:$hilo))], II_MFHI_MFLO>;
964 class PseudoMTLOHI<RegisterClass DstRC, RegisterClass SrcRC>
965 : PseudoSE<(outs DstRC:$lohi), (ins SrcRC:$lo, SrcRC:$hi),
966 [(set DstRC:$lohi, (MipsMTLOHI SrcRC:$lo, SrcRC:$hi))],
HDMipsDSPInstrInfo.td1279 RegisterClass SrcRC> :
1280 DSPPat<(DstVT (bitconvert (SrcVT SrcRC:$src))),
1281 (COPY_TO_REGCLASS SrcRC:$src, DstRC)>;
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCVSXCopy.cpp99 const TargetRegisterClass *SrcRC = in processBlock() local
106 unsigned NewVReg = MRI.createVirtualRegister(SrcRC); in processBlock()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXInstrInfo.cpp38 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in copyPhysReg() local
40 if (DestRC != SrcRC) in copyPhysReg()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrMMX.td185 multiclass sse12_cvt_pint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
188 def irr : MMXPI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
189 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr, d>,
196 multiclass sse12_cvt_pint_3addr<bits<8> opc, RegisterClass SrcRC,
200 (ins DstRC:$src1, SrcRC:$src2), asm,
201 [(set DstRC:$dst, (Int DstRC:$src1, SrcRC:$src2))],
HDX86InstrAVX512.td697 multiclass avx512_fp_broadcast<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
700 (ins SrcRC:$src), "vbroadcast"## !subst("p", "s", _.Suffix),
701 "$src", "$src", (_.VT (OpNode (svt SrcRC:$src)))>,
789 RegisterClass SrcRC> {
791 (ins SrcRC:$src), "vpbroadcast"##_.Suffix,
796 RegisterClass SrcRC, Predicate prd> {
798 defm Z : avx512_int_broadcast_reg<opc, _.info512, SrcRC>, EVEX_V512;
800 defm Z256 : avx512_int_broadcast_reg<opc, _.info256, SrcRC>, EVEX_V256;
801 defm Z128 : avx512_int_broadcast_reg<opc, _.info128, SrcRC>, EVEX_V128;
4318 multiclass avx512_vcvtsi<bits<8> opc, SDNode OpNode, RegisterClass SrcRC,
[all …]
HDX86InstrSSE.td1478 multiclass sse12_cvt_s<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1481 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1482 [(set DstRC:$dst, (OpNode SrcRC:$src))],
1489 multiclass sse12_cvt_p<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1493 def rr : I<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src), asm,
1501 multiclass sse12_vcvt_avx<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1504 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins DstRC:$src1, SrcRC:$src),
1638 multiclass sse12_cvt_sint<bits<8> opc, RegisterClass SrcRC, RegisterClass DstRC,
1641 def rr : SI<opc, MRMSrcReg, (outs DstRC:$dst), (ins SrcRC:$src),
1643 [(set DstRC:$dst, (Int SrcRC:$src))], itins.rr>,
[all …]
HDX86FastISel.cpp1061 const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg); in X86SelectRet() local
1063 if (!SrcRC->contains(DstReg)) in X86SelectRet()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMBaseRegisterInfo.cpp767 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
780 if (NewRC->getSize() < 32 && DstRC->getSize() < 32 && SrcRC->getSize() < 32) in shouldCoalesce()
786 MRI.getTargetRegisterInfo()->getRegClassWeight(SrcRC); in shouldCoalesce()
HDARMBaseRegisterInfo.h182 const TargetRegisterClass *SrcRC,
HDARMFastISel.cpp2145 const TargetRegisterClass* SrcRC = MRI.getRegClass(SrcReg); in SelectRet() local
2147 if (!SrcRC->contains(DstReg)) in SelectRet()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDScheduleDAGFast.cpp389 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
392 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
397 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()
HDInstrEmitter.cpp156 const TargetRegisterClass *SrcRC = nullptr, *DstRC = nullptr; in EmitCopyFromReg() local
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg()
171 if (MatchReg && SrcRC->getCopyCost() < 0) { in EmitCopyFromReg()
HDScheduleDAGRRList.cpp1146 const TargetRegisterClass *SrcRC, in InsertCopiesAndMoveSuccs() argument
1149 CopyFromSU->CopySrcRC = SrcRC; in InsertCopiesAndMoveSuccs()
1154 CopyToSU->CopyDstRC = SrcRC; in InsertCopiesAndMoveSuccs()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetRegisterInfo.h859 const TargetRegisterClass *SrcRC, in shouldCoalesce() argument
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonGenInsert.cpp643 const TargetRegisterClass *SrcRC = MRI->getRegClass(SrcR); in isValidInsertForm() local
646 if (!isIntClass(DstRC) || !isIntClass(SrcRC) || !isIntClass(InsRC)) in isValidInsertForm()
649 if (DstRC != SrcRC) in isValidInsertForm()