Searched refs:SrcLane (Results 1 – 2 of 2) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMBaseInstrInfo.cpp | 4297 unsigned DstLane = 0, SrcLane = 0, DDst, DSrc; in setExecutionDomain() local
4299 DSrc = getCorrespondingDRegAndLane(TRI, SrcReg, SrcLane); in setExecutionDomain()
4302 if (!getImplicitSPRUseForDPRUse(TRI, MI, DSrc, SrcLane, ImplicitSReg)) in setExecutionDomain()
4314 .addImm(SrcLane); in setExecutionDomain()
4345 unsigned CurReg = SrcLane == 1 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
4349 CurReg = SrcLane == 0 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
4356 if (SrcLane == DstLane) in setExecutionDomain()
4364 CurReg = SrcLane == 1 && DstLane == 0 ? DSrc : DDst; in setExecutionDomain()
4368 CurReg = SrcLane == 0 && DstLane == 1 ? DSrc : DDst; in setExecutionDomain()
4375 if (SrcLane != DstLane) in setExecutionDomain()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64ISelLowering.cpp | 5284 int SrcLane = ShuffleMask[Anomaly]; in LowerVECTOR_SHUFFLE() local
5285 if (SrcLane >= NumInputElements) { in LowerVECTOR_SHUFFLE()
5287 SrcLane -= VT.getVectorNumElements(); in LowerVECTOR_SHUFFLE()
5289 SDValue SrcLaneV = DAG.getConstant(SrcLane, dl, MVT::i64); in LowerVECTOR_SHUFFLE()
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