Searched refs:ShiftBits (Results 1 – 4 of 4) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPCRegisterInfo.cpp | 515 unsigned ShiftBits = getEncodingValue(DestReg)*4; in lowerCRRestore() local
518 .addReg(Reg1, RegState::Kill).addImm(32-ShiftBits).addImm(0) in lowerCRRestore()
602 unsigned ShiftBits = getEncodingValue(DestReg); in lowerCRBitRestore() local
606 .addImm(ShiftBits ? 32-ShiftBits : 0) in lowerCRBitRestore()
607 .addImm(ShiftBits).addImm(ShiftBits); in lowerCRBitRestore()
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| /NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/ |
| HD | TargetLowering.cpp | 1735 unsigned ShiftBits = AndRHSC.countTrailingZeros(); in SimplifySetCC() local
1742 DAG.getConstant(ShiftBits, dl, in SimplifySetCC()
1744 SDValue CmpRHS = DAG.getConstant(C1.lshr(ShiftBits), dl, CmpTy); in SimplifySetCC()
1755 unsigned ShiftBits; in SimplifySetCC() local
1759 ShiftBits = C1.countTrailingOnes(); in SimplifySetCC()
1763 ShiftBits = C1.countTrailingZeros(); in SimplifySetCC()
1765 NewC = NewC.lshr(ShiftBits); in SimplifySetCC()
1766 if (ShiftBits && NewC.getMinSignedBits() <= 64 && in SimplifySetCC()
1774 DAG.getConstant(ShiftBits, dl, ShiftTy)); in SimplifySetCC()
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| /NextBSD/contrib/llvm/lib/Analysis/ |
| HD | BasicAliasAnalysis.cpp | 390 if (unsigned ShiftBits = 64 - DL.getPointerSizeInBits(AS)) { in DecomposeGEPExpression() local
391 Scale <<= ShiftBits; in DecomposeGEPExpression()
392 Scale = (int64_t)Scale >> ShiftBits; in DecomposeGEPExpression()
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 6241 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8); in LowerCONCAT_VECTORSvXi1() local
6244 V2 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V2, ShiftBits); in LowerCONCAT_VECTORSvXi1()
6250 V1 = DAG.getNode(X86ISD::VSHLI, dl, ResVT, V1, ShiftBits); in LowerCONCAT_VECTORSvXi1()
6251 V1 = DAG.getNode(X86ISD::VSRLI, dl, ResVT, V1, ShiftBits); in LowerCONCAT_VECTORSvXi1()
11227 SDValue ShiftBits = DAG.getConstant(NumElems/2, dl, MVT::i8); in LowerINSERT_SUBVECTOR() local
11231 Vec = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec, ShiftBits); in LowerINSERT_SUBVECTOR()
11232 Vec = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec, ShiftBits); in LowerINSERT_SUBVECTOR()
11236 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits); in LowerINSERT_SUBVECTOR()
11243 Vec2 = DAG.getNode(X86ISD::VSHLI, dl, OpVT, Vec2, ShiftBits); in LowerINSERT_SUBVECTOR()
11244 Vec2 = DAG.getNode(X86ISD::VSRLI, dl, OpVT, Vec2, ShiftBits); in LowerINSERT_SUBVECTOR()
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