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Searched refs:SSE2 (Results 1 – 25 of 35) sorted by relevance

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/NextBSD/crypto/openssl/doc/crypto/
HDOPENSSL_ia32cap.pod37 =item bit #26 denoting SSE2 support;
61 SSE2 code present in the crypto library, while clearing bit #24
62 disables SSE2 code operating on 128-bit XMM register bank. You might
63 have to do the latter if target OpenSSL application is executed on SSE2
HDOPENSSL_instrument_bus.pod40 line' was introduced with the SSE2 extensions.
/NextBSD/contrib/gcc/config/i386/
HDi386.opt193 Target Report Mask(SSE2)
194 Support MMX, SSE and SSE2 built-in functions and code generation
198 Support MMX, SSE, SSE2 and SSE3 built-in functions and code generation
202 Support MMX, SSE, SSE2, SSE3 and SSSE3 built-in functions and code generation
206 Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
HDconstraints.md87 "@internal Any SSE2 register.")
HDsse.md48 ;; All of these patterns are enabled for SSE1 as well as SSE2.
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86.td48 def FeatureSSE2 : SubtargetFeature<"sse2", "X86SSELevel", "SSE2",
49 "Enable SSE2 instructions",
69 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
70 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
486 // basic SSE2 and 64-bit ones. It disables slow things from any mainstream and
HDX86Subtarget.h50 NoMMXSSE, MMX, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
324 bool hasSSE2() const { return X86SSELevel >= SSE2; } in hasSSE2()
HDX86InstrFormats.td546 // SSE2 Instruction Templates:
548 // SDI - SSE2 instructions with XD prefix.
549 // SDIi8 - SSE2 instructions with ImmT == Imm8 and XD prefix.
550 // S2SI - SSE2 instructions with XS prefix.
551 // SSDIi8 - SSE2 instructions with ImmT == Imm8 and XS prefix.
552 // PDI - SSE2 instructions with PD prefix, packed double domain.
553 // PDIi8 - SSE2 instructions with ImmT == Imm8 and PD prefix.
554 // VSDI - SSE2 scalar instructions with XD prefix in AVX form.
555 // VPDI - SSE2 vector instructions with PD prefix in AVX form,
557 // VS2I - SSE2 scalar instructions with PD prefix in AVX form.
[all …]
HDX86CallingConv.td95 // SSE2.
508 // is not a vararg call and if SSE2 is available, are passed in SSE registers.
648 // call and if SSE2 is available, are passed in SSE registers.
HDX86InstrSSE.td1883 // SSE2 instructions with XS prefix
1948 let Constraints = "$src1 = $dst" in { // SSE2 instructions with XS prefix
2042 // SSE2 packed instructions with XS prefix
2172 // SSE2 instructions without OpSize prefix
2250 // SSE2 register conversion intrinsics
2816 // SSE2 - Packed Integer Logical Instructions
2821 /// PDI_binop_rm - Simple SSE2 binary operator.
2978 // SSE1, but only on SSE2.
3486 /// sse2_fp_unop_p - SSE2 unops in vector forms.
3734 // was introduced with SSE2, it's backward compatible.
[all …]
HDX86InstrFPStack.td119 // f64 instructions can use SSE2 and are predicated on FPStackf64 == !SSE2.
HDX86RegisterInfo.td421 // Scalar SSE2 floating point registers.
HDX86InstrCompiler.td501 // SSE1/SSE2.
/NextBSD/crypto/openssl/
HDINSTALL82 no-sse2 Exclude SSE2 code pathes. Normally SSE2 extention is
86 kernel which does not support SSE2 extension on Intel P4
91 disengage SSE2 code pathes upon application start-up,
HDNEWS277 o Add support for AES and SSE2 assembly lanugauge optimization
/NextBSD/contrib/llvm/tools/clang/lib/Basic/
HDTargets.cpp2025 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F enumerator
2685 case SSE2: in setSSELevel()
2699 case SSE2: in setSSELevel()
2792 setSSELevel(Features, SSE2, Enabled); in setFeatureEnabledImpl()
2807 setSSELevel(Features, SSE2, Enabled); in setFeatureEnabledImpl()
2810 setSSELevel(Features, SSE2, Enabled); in setFeatureEnabledImpl()
2835 setSSELevel(Features, SSE2, Enabled); in setFeatureEnabledImpl()
2984 .Case("sse2", SSE2) in handleTargetFeatures()
3312 case SSE2: in getTargetDefines()
3331 case SSE2: in getTargetDefines()
[all …]
/NextBSD/contrib/binutils/include/opcode/
HDChangeLog528 available only with SSE2. Change the MMX additions introduced by SSE
HDChangeLog-9103395 Put them before SSE2 insns, so that rep prefix works.
/NextBSD/contrib/llvm/tools/clang/include/clang/Basic/
HDBuiltinsX86.def146 // MMX+SSE2
/NextBSD/contrib/binutils/opcodes/
HDChangeLog-00011168 (dis386_twobyt): Add SSE2 instructions.
1172 (prefix_user_table): Add two new slots; add SSE2 instructions.
/NextBSD/contrib/jemalloc/
HDChangeLog294 - Add a configure test for SSE2 rather than assuming it is usable on i686
/NextBSD/contrib/gcc/doc/
HDinvoke.texi9237 Low power version of Intel Pentium3 CPU with MMX, SSE and SSE2 instruction set
9240 Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set support.
9242 Improved version of Intel Pentium4 CPU with MMX, SSE, SSE2 and SSE3 instruction
9246 SSE2 and SSE3 instruction set support.
9248 Intel Core2 CPU with 64-bit extensions, MMX, SSE, SSE2, SSE3 and SSSE3
9262 MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
9267 supersets MMX, SSE, SSE2, SSE3, SSE4A, 3dNOW!, enhanced 3dNOW!, ABM and 64-bit
9580 SSE, SSE2, SSE3, SSSE3, SSE4A, ABM, AES or 3DNow! extended
9585 To have SSE/SSE2 instructions generated automatically from floating-point
/NextBSD/contrib/llvm/tools/clang/lib/CodeGen/
HDCGBuiltin.cpp6112 SSE2, in EmitX86BuiltinExpr() enumerator
6134 .Case("sse2", X86Features::SSE2) in EmitX86BuiltinExpr()
/NextBSD/contrib/gcc/
HDChangeLog-200124174 * i386.h (VALID_SSE_REG_MODE): Accept MMX modes if SSE2
24175 * i386.md (movsi_1, movdi2, movdi_1_rex64): Handle SSE2 moves.
28731 * i386.md (sse_andti3, sse_nandti_3, sse_xorti3): Add SSE2 versions;
29670 (sqrtextendsfdf2): Disable for SSE2.
29677 (sqrtextendsfdf2): Disable for SSE2.
29747 * i386.md (dummy_extendsfdf2): Support SSE2
29748 (extendsfdf2): Enable if 80387 or SSE2.
29749 (extendsfdf2_1): Support SSE2. Disable if SSE2 is avialble
29752 (truncdfsf2): Enable if SSE2 or 80387; Always use SSE only version
29778 (TARGET_SSE): SSE2 imply SSE.
[all …]
HDChangeLog-2006894 SSE builtin documentation. Document SSE2 builtins.
5359 (ix86_builtins): Add function codes for SSE2 ABI builtins.
7156 special case code to implement V8HImode and V16QImode with SSE2.
8087 * config/i386/i386.c: Remove builtins for SSE2 ABI intrinsic
13261 (ix86_builtins): Add function codes for SSE2 ABI builtins.

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