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Searched refs:SI (Results 1 – 25 of 397) sorted by relevance

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/NextBSD/contrib/llvm/lib/Object/
HDObject.cpp31 inline section_iterator *unwrap(LLVMSectionIteratorRef SI) { in unwrap() argument
32 return reinterpret_cast<section_iterator*>(SI); in unwrap()
36 wrap(const section_iterator *SI) { in wrap() argument
38 (const_cast<section_iterator*>(SI)); in wrap()
41 inline symbol_iterator *unwrap(LLVMSymbolIteratorRef SI) { in unwrap() argument
42 return reinterpret_cast<symbol_iterator*>(SI); in unwrap()
46 wrap(const symbol_iterator *SI) { in wrap() argument
48 (const_cast<symbol_iterator*>(SI)); in wrap()
51 inline relocation_iterator *unwrap(LLVMRelocationIteratorRef SI) { in unwrap() argument
52 return reinterpret_cast<relocation_iterator*>(SI); in unwrap()
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/NextBSD/contrib/gcc/config/rs6000/
HDrs6000.md138 (define_mode_macro GPR [SI (DI "TARGET_POWERPC64")])
141 (define_mode_macro INT [QI HI SI DI TI])
144 (define_mode_macro INT1 [QI HI SI (DI "TARGET_POWERPC64")])
147 (define_mode_macro QHSI [QI HI SI])
150 (define_mode_macro SDI [SI DI])
154 (define_mode_macro P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")])
162 ; Various instructions that come in SI and DI forms.
164 (define_mode_attr wd [(QI "b") (HI "h") (SI "w") (DI "d")])
167 (define_mode_attr dbits [(QI "56") (HI "48") (SI "32")])
367 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))]
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HDsync.md22 (define_mode_attr larx [(SI "lwarx") (DI "ldarx")])
23 (define_mode_attr stcx [(SI "stwcx.") (DI "stdcx.")])
114 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
115 (match_operand:SI 4 "memory_operand" "+Z"))
117 (unspec:SI
118 [(match_operand:SI 1 "gpc_reg_operand" "r")
119 (match_operand:SI 2 "gpc_reg_operand" "r")
120 (match_operand:SI 3 "gpc_reg_operand" "r")]
122 (clobber (match_scratch:SI 5 "=&r"))
176 [(set (match_operand:SI 0 "memory_operand" "+Z")
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HDdarwin.md32 (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
82 [(set (mem:DF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
101 (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
122 [(set (mem:SF (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,b")
154 [(set (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b")
156 (match_operand:SI 0 "gpc_reg_operand" "r"))]
186 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r")
187 (high:SI (match_operand 1 "" "")))]
213 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
214 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r")
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HDspe.md94 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
95 (unsigned_fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
108 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
109 (unsigned_fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
115 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
116 (fix:SI (match_operand:SF 1 "gpc_reg_operand" "r")))]
122 [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
123 (fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
130 (unsigned_float:SF (match_operand:SI 1 "gpc_reg_operand" "r")))]
137 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
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/NextBSD/contrib/gcc/config/arm/
HDarm.md401 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
403 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
404 (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
405 (plus:SI (match_dup 4) (match_dup 5))))]
422 (match_operand:SI 2 "s_register_operand" "r,r"))
429 (compare:CC_C (plus:SI (match_dup 1) (match_dup 2))
431 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))])
432 (set (match_dup 3) (plus:SI (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))
433 (plus:SI (ashiftrt:SI (match_dup 2)
451 (match_operand:SI 2 "s_register_operand" "r,r"))
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HDcirrus.md44 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
45 (plus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
46 (match_operand:SI 2 "cirrus_fp_register" "v")))]
84 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
85 (minus:SI (match_operand:SI 1 "cirrus_fp_register" "v")
86 (match_operand:SI 2 "cirrus_fp_register" "v")))]
114 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
115 (mult:SI (match_operand:SI 2 "cirrus_fp_register" "v")
116 (match_operand:SI 1 "cirrus_fp_register" "v")))]
134 [(set (match_operand:SI 0 "cirrus_fp_register" "=v")
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HDiwmmxt.md99 [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r,?z,Uy,z")
100 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z,Uy,z,z"))]
140 (set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m,z,r")
141 (match_operand:SI 1 "general_operand" "rI,K,mi,r,r,z")))]
554 (truncate:QI (match_operand:SI 2 "nonimmediate_operand" "r")))
555 (match_operand:SI 3 "immediate_operand" "i")))]
564 (truncate:HI (match_operand:SI 2 "nonimmediate_operand" "r")))
565 (match_operand:SI 3 "immediate_operand" "i")))]
574 (match_operand:SI 2 "nonimmediate_operand" "r"))
575 (match_operand:SI 3 "immediate_operand" "i")))]
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/NextBSD/contrib/gcc/config/mips/
HDmips-dsp.md10 (define_mode_macro DSP [(SI "TARGET_DSP")
19 (define_mode_macro DSPQ [(SI "TARGET_DSP")
23 (define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")])
27 (define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")])
30 (define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")])
32 ;; DSP shift masks for SI, V2HI, V4QI.
33 (define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")])
48 (set_attr "mode" "SI")])
61 (set_attr "mode" "SI")])
74 (set_attr "mode" "SI")])
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HDmips.md233 (define_attr "mode" "unknown,none,QI,HI,SI,DI,SF,DF,FPSW"
237 ;; I2S integer to float single (SI/DI to SF)
238 ;; I2D integer to float double (SI/DI to DF)
239 ;; S2I float to integer (SF to SI/DI)
240 ;; D2I float to integer (DF to SI/DI)
407 (define_mode_macro GPR [SI (DI "TARGET_64BIT")])
411 (define_mode_macro P [(SI "Pmode == SImode") (DI "Pmode == DImode")])
415 (define_mode_macro MOVECC [SI (DI "TARGET_64BIT") (CC "TARGET_HARD_FLOAT")])
433 (define_mode_attr d [(SI "") (DI "d")])
443 (define_mode_attr load [(SI "lw") (DI "ld")])
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/NextBSD/contrib/gcc/config/sparc/
HDsparc.md344 (compare:CC (match_operand:SI 0 "compare_operand" "")
345 (match_operand:SI 1 "arith_operand" "")))]
410 (compare:CC (match_operand:SI 0 "register_operand" "r")
411 (match_operand:SI 1 "arith_operand" "rI")))]
510 (xor:SI (match_operand:SI 1 "register_operand" "")
511 (match_operand:SI 2 "register_operand" "")))
512 (parallel [(set (match_operand:SI 0 "register_operand" "")
513 (eq:SI (match_dup 3) (const_int 0)))
529 (xor:SI (match_operand:SI 1 "register_operand" "")
530 (match_operand:SI 2 "register_operand" "")))
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/NextBSD/contrib/llvm/lib/Transforms/InstCombine/
HDInstCombineLoadStoreAlloca.cpp384 static StoreInst *combineStoreToNewValue(InstCombiner &IC, StoreInst &SI, Value *V) { in combineStoreToNewValue() argument
385 Value *Ptr = SI.getPointerOperand(); in combineStoreToNewValue()
386 unsigned AS = SI.getPointerAddressSpace(); in combineStoreToNewValue()
388 SI.getAllMetadata(MD); in combineStoreToNewValue()
392 SI.getAlignment()); in combineStoreToNewValue()
466 auto *SI = dyn_cast<StoreInst>(U); in combineLoadToOperationType() local
467 return SI && SI->getPointerOperand() != &LI; in combineLoadToOperationType()
474 auto *SI = cast<StoreInst>(*UI++); in combineLoadToOperationType() local
475 IC.Builder->SetInsertPoint(SI); in combineLoadToOperationType()
476 combineStoreToNewValue(IC, *SI, NewLoad); in combineLoadToOperationType()
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HDInstCombineSelect.cpp115 Instruction *InstCombiner::FoldSelectOpOp(SelectInst &SI, Instruction *TI, in FoldSelectOpOp() argument
126 Type *CondTy = SI.getCondition()->getType(); in FoldSelectOpOp()
135 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0), in FoldSelectOpOp()
136 FI->getOperand(0), SI.getName()+".v"); in FoldSelectOpOp()
175 Value *NewSI = Builder->CreateSelect(SI.getCondition(), OtherOpT, in FoldSelectOpOp()
176 OtherOpF, SI.getName()+".v"); in FoldSelectOpOp()
202 Instruction *InstCombiner::FoldSelectIntoOp(SelectInst &SI, Value *TrueVal, in FoldSelectIntoOp() argument
223 Value *NewSel = Builder->CreateSelect(SI.getCondition(), OOp, C); in FoldSelectIntoOp()
258 Value *NewSel = Builder->CreateSelect(SI.getCondition(), C, OOp); in FoldSelectIntoOp()
292 static Value *foldSelectICmpAndOr(const SelectInst &SI, Value *TrueVal, in foldSelectICmpAndOr() argument
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/NextBSD/contrib/llvm/include/llvm-c/
HDObject.h48 void LLVMDisposeSectionIterator(LLVMSectionIteratorRef SI);
50 LLVMSectionIteratorRef SI);
51 void LLVMMoveToNextSection(LLVMSectionIteratorRef SI);
57 void LLVMDisposeSymbolIterator(LLVMSymbolIteratorRef SI);
59 LLVMSymbolIteratorRef SI);
60 void LLVMMoveToNextSymbol(LLVMSymbolIteratorRef SI);
63 const char *LLVMGetSectionName(LLVMSectionIteratorRef SI);
64 uint64_t LLVMGetSectionSize(LLVMSectionIteratorRef SI);
65 const char *LLVMGetSectionContents(LLVMSectionIteratorRef SI);
66 uint64_t LLVMGetSectionAddress(LLVMSectionIteratorRef SI);
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/NextBSD/contrib/llvm/include/llvm/ADT/
HDSetOperations.h26 for (typename S2Ty::const_iterator SI = S2.begin(), SE = S2.end(); in set_union() local
27 SI != SE; ++SI) in set_union()
28 if (S1.insert(*SI).second) in set_union()
53 for (typename S1Ty::const_iterator SI = S1.begin(), SE = S1.end(); in set_difference() local
54 SI != SE; ++SI) in set_difference()
55 if (!S2.count(*SI)) // if the element is not in set2 in set_difference()
56 Result.insert(*SI); in set_difference()
64 for (typename S2Ty::const_iterator SI = S2.begin(), SE = S2.end(); in set_subtract() local
65 SI != SE; ++SI) in set_subtract()
66 S1.erase(*SI); in set_subtract()
/NextBSD/contrib/gcc/config/i386/
HDi386.md222 "unknown,none,QI,HI,SI,DI,SF,DF,XF,TI,V4SF,V2DF,V2SF,V1DF"
322 (ior (match_operand:SI 1 "register_operand" "")
471 (define_mode_macro X87MODEI [HI SI DI])
474 (define_mode_macro X87MODEI12 [HI SI])
480 (define_mode_macro SSEMODEI24 [SI DI])
532 (compare:CC (match_operand:SI 0 "cmpsi_operand" "")
533 (match_operand:SI 1 "general_operand" "")))]
610 (compare (match_operand:SI 0 "nonimmediate_operand" "r,?mr")
611 (match_operand:SI 1 "const0_operand" "n,n")))]
618 (set_attr "mode" "SI")])
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/NextBSD/contrib/llvm/lib/Transforms/Scalar/
HDCorrelatedValuePropagation.cpp41 bool processSelect(SelectInst *SI);
45 bool processSwitch(SwitchInst *SI);
111 SelectInst *SI = dyn_cast<SelectInst>(Incoming); in processPHI() local
112 if (!SI) continue; in processPHI()
114 Value *Condition = SI->getCondition(); in processPHI()
119 V = SI->getTrueValue(); in processPHI()
121 V = SI->getFalseValue(); in processPHI()
133 Constant *C = dyn_cast<Constant>(SI->getFalseValue()); in processPHI()
136 if (LVI->getPredicateOnEdge(ICmpInst::ICMP_EQ, SI, C, in processPHI()
140 V = SI->getTrueValue(); in processPHI()
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HDSROA.cpp277 iterator SI, SJ; member in __anoncadf9e170311::AllocaSlices::Partition
284 Partition(iterator SI) : SI(SI), SJ(SI) {} in Partition() argument
307 bool empty() const { return SI == SJ; } in empty()
318 iterator begin() const { return SI; } in begin()
357 partition_iterator(AllocaSlices::iterator SI, AllocaSlices::iterator SE) in partition_iterator() argument
358 : P(SI), SE(SE), MaxSplitSliceEndOffset(0) { in partition_iterator()
361 if (SI != SE) in partition_iterator()
369 assert((P.SI != SE || !P.SplitTails.empty()) && in advance()
402 if (P.SI == SE) { in advance()
409 if (P.SI != P.SJ) { in advance()
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/NextBSD/sys/boot/uboot/lib/
HDdisk.c68 #define SI(dev) (stor_info[(dev)->d_unit]) macro
158 if (size % SI(dev).bsize) { in stor_strategy()
160 size, SI(dev).bsize); in stor_strategy()
163 bcount = size / SI(dev).bsize; in stor_strategy()
195 if (SI(dev).opened == 0) { in stor_opendev()
196 err = ub_dev_open(SI(dev).handle); in stor_opendev()
199 "handle=%d\n", err, SI(dev).handle); in stor_opendev()
202 SI(dev).opened++; in stor_opendev()
204 return (disk_open(dev, SI(dev).blocks * SI(dev).bsize, in stor_opendev()
205 SI(dev).bsize, 0)); in stor_opendev()
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/NextBSD/contrib/llvm/lib/Transforms/Utils/
HDSimplifyCFG.cpp128 bool SimplifySwitch(SwitchInst *SI, IRBuilder<> &Builder);
506 if (SwitchInst *SI = dyn_cast<SwitchInst>(TI)) { in EraseTerminatorInstAndDCECond() local
507 Cond = dyn_cast<Instruction>(SI->getCondition()); in EraseTerminatorInstAndDCECond()
523 if (SwitchInst *SI = dyn_cast<SwitchInst>(TI)) { in isValueEqualityComparison() local
526 if (SI->getNumSuccessors()*std::distance(pred_begin(SI->getParent()), in isValueEqualityComparison()
527 pred_end(SI->getParent())) <= 128) in isValueEqualityComparison()
528 CV = SI->getCondition(); in isValueEqualityComparison()
553 if (SwitchInst *SI = dyn_cast<SwitchInst>(TI)) { in GetValueEqualityComparisonCases() local
554 Cases.reserve(SI->getNumCases()); in GetValueEqualityComparisonCases()
555 for (SwitchInst::CaseIt i = SI->case_begin(), e = SI->case_end(); i != e; ++i) in GetValueEqualityComparisonCases()
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HDLocal.cpp115 if (SwitchInst *SI = dyn_cast<SwitchInst>(T)) { in ConstantFoldTerminator() local
118 ConstantInt *CI = dyn_cast<ConstantInt>(SI->getCondition()); in ConstantFoldTerminator()
119 BasicBlock *DefaultDest = SI->getDefaultDest(); in ConstantFoldTerminator()
124 SI->getNumCases() > 0) { in ConstantFoldTerminator()
125 TheOnlyDest = SI->case_begin().getCaseSuccessor(); in ConstantFoldTerminator()
129 for (SwitchInst::CaseIt i = SI->case_begin(), e = SI->case_end(); in ConstantFoldTerminator()
140 MDNode *MD = SI->getMetadata(LLVMContext::MD_prof); in ConstantFoldTerminator()
141 unsigned NCases = SI->getNumCases(); in ConstantFoldTerminator()
160 SI->setMetadata(LLVMContext::MD_prof, in ConstantFoldTerminator()
165 DefaultDest->removePredecessor(SI->getParent()); in ConstantFoldTerminator()
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/NextBSD/contrib/llvm/lib/CodeGen/
HDEdgeBundles.cpp47 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(), in runOnMachineFunction() local
48 SE = MBB.succ_end(); SI != SE; ++SI) in runOnMachineFunction()
49 EC.join(OutE, 2 * (*SI)->getNumber()); in runOnMachineFunction()
84 for (MachineBasicBlock::const_succ_iterator SI = MBB.succ_begin(), in WriteGraph() local
85 SE = MBB.succ_end(); SI != SE; ++SI) in WriteGraph()
86 O << "\t\"BB#" << BB << "\" -> \"BB#" << (*SI)->getNumber() in WriteGraph()
HDLiveIntervalUnion.cpp87 for (LiveSegments::const_iterator SI = Segments.begin(); SI.valid(); ++SI) { in print() local
88 OS << " [" << SI.start() << ' ' << SI.stop() << "):" in print()
89 << PrintReg(SI.value()->reg, TRI); in print()
97 for (SegmentIter SI = Segments.begin(); SI.valid(); ++SI) in verify() local
98 VisitedVRegs.set(SI.value()->reg); in verify()
/NextBSD/contrib/gcc/config/s390/
HDs390.md52 ;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction.
152 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY"
182 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI") (const_int 4)]
219 (define_mode_macro TDSI [(TI "TARGET_64BIT") DI SI])
223 (define_mode_macro GPR [(DI "TARGET_64BIT") SI])
224 (define_mode_macro DSI [DI SI])
229 (define_mode_macro P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")])
237 (define_mode_macro INT [(DI "TARGET_64BIT") SI HI QI])
276 (define_mode_attr d0 [(DI "d") (SI "0")])
281 (define_mode_attr 1 [(DI "%1,") (SI "")])
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/NextBSD/contrib/llvm/utils/TableGen/
HDDFAPacketizerEmitter.cpp187 for (std::set<unsigned>::iterator SI = stateInfo.begin(); in AddInsnClass() local
188 SI != stateInfo.end(); ++SI) { in AddInsnClass()
189 unsigned thisState = *SI; in AddInsnClass()
232 for (std::set<unsigned>::const_iterator SI = stateInfo.begin(); in canAddInsnClass() local
233 SI != stateInfo.end(); ++SI) { in canAddInsnClass()
234 if (~*SI & InsnClass) in canAddInsnClass()
268 DFA::StateSet::iterator SI = states.begin(); in writeTableAndAPI() local
279 for (unsigned i = 0; i < states.size(); ++i, ++SI) { in writeTableAndAPI()
280 assert ((SI->stateNum == (int) i) && "Mismatch in state numbers"); in writeTableAndAPI()
283 II = SI->Transitions.begin(), IE = SI->Transitions.end(); in writeTableAndAPI()
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