Searched refs:REnd (Results 1 – 4 of 4) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MipsInstrInfo.cpp | 146 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); in RemoveBranch() local
151 while (I != REnd && I->isDebugValue()) in RemoveBranch()
158 for (removed = 0; I != REnd && removed < 2; ++I, ++removed) in RemoveBranch()
182 MachineBasicBlock::reverse_iterator I = MBB.rbegin(), REnd = MBB.rend(); in AnalyzeBranch() local
185 while (I != REnd && I->isDebugValue()) in AnalyzeBranch()
188 if (I == REnd || !isUnpredicatedTerminator(&*I)) { in AnalyzeBranch()
207 if (++I != REnd) { in AnalyzeBranch()
231 if (++I != REnd && isUnpredicatedTerminator(&*I)) in AnalyzeBranch()
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| /NextBSD/contrib/llvm/include/llvm/ADT/ |
| HD | ImmutableSet.h | 142 iterator RItr = RHS.begin(), REnd = RHS.end(); in isEqual() local
144 while (LItr != LEnd && RItr != REnd) { in isEqual()
158 return LItr == LEnd && RItr == REnd; in isEqual()
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| /NextBSD/contrib/llvm/utils/TableGen/ |
| HD | CodeGenSchedule.cpp | 312 for (unsigned RIdx = 0, REnd = SchedReads.size(); RIdx != REnd; ++RIdx) { in collectSchedRW()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelLowering.cpp | 2914 unsigned RBegin, REnd; in StoreByValRegs() local
2916 CCInfo.getInRegsParamInfo(InRegsParamRecordIdx, RBegin, REnd); in StoreByValRegs()
2920 REnd = ARM::R4; in StoreByValRegs()
2923 if (REnd != RBegin) in StoreByValRegs()
2934 for (unsigned Reg = RBegin, i = 0; Reg < REnd; ++Reg, ++i) { in StoreByValRegs()
3018 unsigned RBegin, REnd; in LowerFormalArguments() local
3019 CCInfo.getInRegsParamInfo(CCInfo.getInRegsParamsProcessed(), RBegin, REnd); in LowerFormalArguments()
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