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Searched refs:QCA955X_PLL_ETH_SGMII_CONTROL_REG (Results 1 – 2 of 2) sorted by relevance

/NextBSD/sys/mips/atheros/
HDqca955xreg.h108 #define QCA955X_PLL_ETH_SGMII_CONTROL_REG (AR71XX_PLL_CPU_BASE + 0x48) macro
HDqca955x_chip.c200 ATH_WRITE_REG(QCA955X_PLL_ETH_SGMII_CONTROL_REG, pll); in qca955x_chip_set_pll_ge()