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Searched refs:PSL_DR (Results 1 – 13 of 13) sorted by relevance

/NextBSD/sys/powerpc/include/
HDpsl.h73 #define PSL_DR 0x00000010UL /* data address relocation */ macro
96 #define PSL_KERNSET (PSL_SF | PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
98 #define PSL_KERNSET (PSL_EE | PSL_ME | PSL_IR | PSL_DR | PSL_RI)
/NextBSD/sys/boot/powerpc/ps3/
HDps3mmu.c116 mtmsr(PSL_IR | PSL_DR | PSL_RI | PSL_ME); in ps3mmu_init()
HDmain.c156 mtmsr(PSL_IR | PSL_DR | PSL_RI); in ppc_exception()
/NextBSD/sys/powerpc/aim/
HDaim_machdep.c231 mtmsr((msr & ~(PSL_IR | PSL_DR)) | PSL_RI); in aim_cpu_init()
473 mtmsr(msr & ~(PSL_EE | PSL_DR)); in flush_disable_caches()
HDmoea64_native.c178 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
374 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); in moea64_cpu_bootstrap_native()
HDtrap_subr64.S128 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
244 andi. %r3,%r3,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
HDtrap_subr32.S102 ori %r30,%r30,(PSL_DR|PSL_IR|PSL_RI)@l; /* relocation on */ \
219 andi. %r2,%r2,~(PSL_DR|PSL_IR|PSL_ME|PSL_RI)@l; \
HDmmu_oea64.c102 #define DISABLE_TRANS(msr) msr = mfmsr(); mtmsr(msr & ~PSL_DR)
882 mtmsr(mfmsr() | PSL_DR | PSL_IR); in moea64_late_bootstrap()
/NextBSD/sys/powerpc/powerpc/
HDgenassym.c238 ASSYM(PSL_DR, PSL_DR);
/NextBSD/sys/powerpc/ofw/
HDrtas.c92 rtasmsr &= ~(PSL_IR | PSL_DR | PSL_EE | PSL_SE); in rtas_setup()
HDofw_machdep.c354 if (ofmsr[0] & PSL_DR) in OF_initial_setup()
/NextBSD/sys/powerpc/ps3/
HDmmu_ps3.c120 mtmsr(mfmsr() & ~PSL_DR & ~PSL_IR); in mps3_cpu_bootstrap()
/NextBSD/sys/dev/vt/hw/ofwfb/
HDofwfb.c487 if (!(mfmsr() & (PSL_HV | PSL_DR))) in ofwfb_init()