1 /*- 2 * Copyright (c) 2003-2008, Joseph Koshy 3 * Copyright (c) 2007 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * Portions of this software were developed by A. Joseph Koshy under 7 * sponsorship from the FreeBSD Foundation and Google, Inc. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * $FreeBSD$ 31 */ 32 33 #ifndef _SYS_PMC_H_ 34 #define _SYS_PMC_H_ 35 36 #include <dev/hwpmc/pmc_events.h> 37 38 #include <machine/pmc_mdep.h> 39 #include <machine/profile.h> 40 41 #define PMC_MODULE_NAME "hwpmc" 42 #define PMC_NAME_MAX 64 /* HW counter name size */ 43 #define PMC_CLASS_MAX 8 /* max #classes of PMCs per-system */ 44 45 /* 46 * Kernel<->userland API version number [MMmmpppp] 47 * 48 * Major numbers are to be incremented when an incompatible change to 49 * the ABI occurs that older clients will not be able to handle. 50 * 51 * Minor numbers are incremented when a backwards compatible change 52 * occurs that allows older correct programs to run unchanged. For 53 * example, when support for a new PMC type is added. 54 * 55 * The patch version is incremented for every bug fix. 56 */ 57 #define PMC_VERSION_MAJOR 0x03 58 #define PMC_VERSION_MINOR 0x01 59 #define PMC_VERSION_PATCH 0x0000 60 61 #define PMC_VERSION (PMC_VERSION_MAJOR << 24 | \ 62 PMC_VERSION_MINOR << 16 | PMC_VERSION_PATCH) 63 64 /* 65 * Kinds of CPUs known. 66 * 67 * We keep track of CPU variants that need to be distinguished in 68 * some way for PMC operations. CPU names are grouped by manufacturer 69 * and numbered sparsely in order to minimize changes to the ABI involved 70 * when new CPUs are added. 71 */ 72 73 #define __PMC_CPUS() \ 74 __PMC_CPU(AMD_K7, 0x00, "AMD K7") \ 75 __PMC_CPU(AMD_K8, 0x01, "AMD K8") \ 76 __PMC_CPU(INTEL_P5, 0x80, "Intel Pentium") \ 77 __PMC_CPU(INTEL_P6, 0x81, "Intel Pentium Pro") \ 78 __PMC_CPU(INTEL_CL, 0x82, "Intel Celeron") \ 79 __PMC_CPU(INTEL_PII, 0x83, "Intel Pentium II") \ 80 __PMC_CPU(INTEL_PIII, 0x84, "Intel Pentium III") \ 81 __PMC_CPU(INTEL_PM, 0x85, "Intel Pentium M") \ 82 __PMC_CPU(INTEL_PIV, 0x86, "Intel Pentium IV") \ 83 __PMC_CPU(INTEL_CORE, 0x87, "Intel Core Solo/Duo") \ 84 __PMC_CPU(INTEL_CORE2, 0x88, "Intel Core2") \ 85 __PMC_CPU(INTEL_CORE2EXTREME, 0x89, "Intel Core2 Extreme") \ 86 __PMC_CPU(INTEL_ATOM, 0x8A, "Intel Atom") \ 87 __PMC_CPU(INTEL_COREI7, 0x8B, "Intel Core i7") \ 88 __PMC_CPU(INTEL_WESTMERE, 0x8C, "Intel Westmere") \ 89 __PMC_CPU(INTEL_SANDYBRIDGE, 0x8D, "Intel Sandy Bridge") \ 90 __PMC_CPU(INTEL_IVYBRIDGE, 0x8E, "Intel Ivy Bridge") \ 91 __PMC_CPU(INTEL_SANDYBRIDGE_XEON, 0x8F, "Intel Sandy Bridge Xeon") \ 92 __PMC_CPU(INTEL_IVYBRIDGE_XEON, 0x90, "Intel Ivy Bridge Xeon") \ 93 __PMC_CPU(INTEL_HASWELL, 0x91, "Intel Haswell") \ 94 __PMC_CPU(INTEL_ATOM_SILVERMONT, 0x92, "Intel Atom Silvermont") \ 95 __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ 96 __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ 97 __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ 98 __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ 99 __PMC_CPU(INTEL_BROADWELL_XEON, 0x97, "Intel Broadwell Xeon") \ 100 __PMC_CPU(INTEL_SKYLAKE, 0x98, "Intel Skylake") \ 101 __PMC_CPU(INTEL_SKYLAKE_XEON, 0x99, "Intel Skylake Xeon") \ 102 __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ 103 __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ 104 __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \ 105 __PMC_CPU(MIPS_74K, 0x202, "MIPS 74K") \ 106 __PMC_CPU(PPC_7450, 0x300, "PowerPC MPC7450") \ 107 __PMC_CPU(PPC_E500, 0x340, "PowerPC e500 Core") \ 108 __PMC_CPU(PPC_MPC85XX, 0x340, "Freescale PowerPC MPC85XX") \ 109 __PMC_CPU(PPC_970, 0x380, "IBM PowerPC 970") \ 110 __PMC_CPU(GENERIC, 0x400, "Generic") \ 111 __PMC_CPU(ARMV7_CORTEX_A5, 0x500, "ARMv7 Cortex A5") \ 112 __PMC_CPU(ARMV7_CORTEX_A7, 0x501, "ARMv7 Cortex A7") \ 113 __PMC_CPU(ARMV7_CORTEX_A8, 0x502, "ARMv7 Cortex A8") \ 114 __PMC_CPU(ARMV7_CORTEX_A9, 0x503, "ARMv7 Cortex A9") \ 115 __PMC_CPU(ARMV7_CORTEX_A15, 0x504, "ARMv7 Cortex A15") \ 116 __PMC_CPU(ARMV7_CORTEX_A17, 0x505, "ARMv7 Cortex A17") \ 117 __PMC_CPU(ARMV8_CORTEX_A53, 0x600, "ARMv8 Cortex A53") \ 118 __PMC_CPU(ARMV8_CORTEX_A57, 0x601, "ARMv8 Cortex A57") 119 120 enum pmc_cputype { 121 #undef __PMC_CPU 122 #define __PMC_CPU(S,V,D) PMC_CPU_##S = V, 123 __PMC_CPUS() 124 }; 125 126 #define PMC_CPU_FIRST PMC_CPU_AMD_K7 127 #define PMC_CPU_LAST PMC_CPU_GENERIC 128 129 /* 130 * Classes of PMCs 131 */ 132 133 #define __PMC_CLASSES() \ 134 __PMC_CLASS(TSC, 0x00, "CPU Timestamp counter") \ 135 __PMC_CLASS(K7, 0x01, "AMD K7 performance counters") \ 136 __PMC_CLASS(K8, 0x02, "AMD K8 performance counters") \ 137 __PMC_CLASS(P5, 0x03, "Intel Pentium counters") \ 138 __PMC_CLASS(P6, 0x04, "Intel Pentium Pro counters") \ 139 __PMC_CLASS(P4, 0x05, "Intel Pentium-IV counters") \ 140 __PMC_CLASS(IAF, 0x06, "Intel Core2/Atom, fixed function") \ 141 __PMC_CLASS(IAP, 0x07, "Intel Core...Atom, programmable") \ 142 __PMC_CLASS(UCF, 0x08, "Intel Uncore fixed function") \ 143 __PMC_CLASS(UCP, 0x09, "Intel Uncore programmable") \ 144 __PMC_CLASS(XSCALE, 0x0A, "Intel XScale counters") \ 145 __PMC_CLASS(MIPS24K, 0x0B, "MIPS 24K") \ 146 __PMC_CLASS(OCTEON, 0x0C, "Cavium Octeon") \ 147 __PMC_CLASS(PPC7450, 0x0D, "Motorola MPC7450 class") \ 148 __PMC_CLASS(PPC970, 0x0E, "IBM PowerPC 970 class") \ 149 __PMC_CLASS(SOFT, 0x0F, "Software events") \ 150 __PMC_CLASS(ARMV7, 0x10, "ARMv7") \ 151 __PMC_CLASS(ARMV8, 0x11, "ARMv8") \ 152 __PMC_CLASS(MIPS74K, 0x12, "MIPS 74K") \ 153 __PMC_CLASS(E500, 0x13, "Freescale e500 class") 154 155 enum pmc_class { 156 #undef __PMC_CLASS 157 #define __PMC_CLASS(S,V,D) PMC_CLASS_##S = V, 158 __PMC_CLASSES() 159 }; 160 161 #define PMC_CLASS_FIRST PMC_CLASS_TSC 162 #define PMC_CLASS_LAST PMC_CLASS_E500 163 164 /* 165 * A PMC can be in the following states: 166 * 167 * Hardware states: 168 * DISABLED -- administratively prohibited from being used. 169 * FREE -- HW available for use 170 * Software states: 171 * ALLOCATED -- allocated 172 * STOPPED -- allocated, but not counting events 173 * RUNNING -- allocated, and in operation; 'pm_runcount' 174 * holds the number of CPUs using this PMC at 175 * a given instant 176 * DELETED -- being destroyed 177 */ 178 179 #define __PMC_HWSTATES() \ 180 __PMC_STATE(DISABLED) \ 181 __PMC_STATE(FREE) 182 183 #define __PMC_SWSTATES() \ 184 __PMC_STATE(ALLOCATED) \ 185 __PMC_STATE(STOPPED) \ 186 __PMC_STATE(RUNNING) \ 187 __PMC_STATE(DELETED) 188 189 #define __PMC_STATES() \ 190 __PMC_HWSTATES() \ 191 __PMC_SWSTATES() 192 193 enum pmc_state { 194 #undef __PMC_STATE 195 #define __PMC_STATE(S) PMC_STATE_##S, 196 __PMC_STATES() 197 __PMC_STATE(MAX) 198 }; 199 200 #define PMC_STATE_FIRST PMC_STATE_DISABLED 201 #define PMC_STATE_LAST PMC_STATE_DELETED 202 203 /* 204 * An allocated PMC may used as a 'global' counter or as a 205 * 'thread-private' one. Each such mode of use can be in either 206 * statistical sampling mode or in counting mode. Thus a PMC in use 207 * 208 * SS i.e., SYSTEM STATISTICAL -- system-wide statistical profiling 209 * SC i.e., SYSTEM COUNTER -- system-wide counting mode 210 * TS i.e., THREAD STATISTICAL -- thread virtual, statistical profiling 211 * TC i.e., THREAD COUNTER -- thread virtual, counting mode 212 * 213 * Statistical profiling modes rely on the PMC periodically delivering 214 * a interrupt to the CPU (when the configured number of events have 215 * been measured), so the PMC must have the ability to generate 216 * interrupts. 217 * 218 * In counting modes, the PMC counts its configured events, with the 219 * value of the PMC being read whenever needed by its owner process. 220 * 221 * The thread specific modes "virtualize" the PMCs -- the PMCs appear 222 * to be thread private and count events only when the profiled thread 223 * actually executes on the CPU. 224 * 225 * The system-wide "global" modes keep the PMCs running all the time 226 * and are used to measure the behaviour of the whole system. 227 */ 228 229 #define __PMC_MODES() \ 230 __PMC_MODE(SS, 0) \ 231 __PMC_MODE(SC, 1) \ 232 __PMC_MODE(TS, 2) \ 233 __PMC_MODE(TC, 3) 234 235 enum pmc_mode { 236 #undef __PMC_MODE 237 #define __PMC_MODE(M,N) PMC_MODE_##M = N, 238 __PMC_MODES() 239 }; 240 241 #define PMC_MODE_FIRST PMC_MODE_SS 242 #define PMC_MODE_LAST PMC_MODE_TC 243 244 #define PMC_IS_COUNTING_MODE(mode) \ 245 ((mode) == PMC_MODE_SC || (mode) == PMC_MODE_TC) 246 #define PMC_IS_SYSTEM_MODE(mode) \ 247 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_SC) 248 #define PMC_IS_SAMPLING_MODE(mode) \ 249 ((mode) == PMC_MODE_SS || (mode) == PMC_MODE_TS) 250 #define PMC_IS_VIRTUAL_MODE(mode) \ 251 ((mode) == PMC_MODE_TS || (mode) == PMC_MODE_TC) 252 253 /* 254 * PMC row disposition 255 */ 256 257 #define __PMC_DISPOSITIONS(N) \ 258 __PMC_DISP(STANDALONE) /* global/disabled counters */ \ 259 __PMC_DISP(FREE) /* free/available */ \ 260 __PMC_DISP(THREAD) /* thread-virtual PMCs */ \ 261 __PMC_DISP(UNKNOWN) /* sentinel */ 262 263 enum pmc_disp { 264 #undef __PMC_DISP 265 #define __PMC_DISP(D) PMC_DISP_##D , 266 __PMC_DISPOSITIONS() 267 }; 268 269 #define PMC_DISP_FIRST PMC_DISP_STANDALONE 270 #define PMC_DISP_LAST PMC_DISP_THREAD 271 272 /* 273 * Counter capabilities 274 * 275 * __PMC_CAPS(NAME, VALUE, DESCRIPTION) 276 */ 277 278 #define __PMC_CAPS() \ 279 __PMC_CAP(INTERRUPT, 0, "generate interrupts") \ 280 __PMC_CAP(USER, 1, "count user-mode events") \ 281 __PMC_CAP(SYSTEM, 2, "count system-mode events") \ 282 __PMC_CAP(EDGE, 3, "do edge detection of events") \ 283 __PMC_CAP(THRESHOLD, 4, "ignore events below a threshold") \ 284 __PMC_CAP(READ, 5, "read PMC counter") \ 285 __PMC_CAP(WRITE, 6, "reprogram PMC counter") \ 286 __PMC_CAP(INVERT, 7, "invert comparision sense") \ 287 __PMC_CAP(QUALIFIER, 8, "further qualify monitored events") \ 288 __PMC_CAP(PRECISE, 9, "perform precise sampling") \ 289 __PMC_CAP(TAGGING, 10, "tag upstream events") \ 290 __PMC_CAP(CASCADE, 11, "cascade counters") 291 292 enum pmc_caps 293 { 294 #undef __PMC_CAP 295 #define __PMC_CAP(NAME, VALUE, DESCR) PMC_CAP_##NAME = (1 << VALUE) , 296 __PMC_CAPS() 297 }; 298 299 #define PMC_CAP_FIRST PMC_CAP_INTERRUPT 300 #define PMC_CAP_LAST PMC_CAP_CASCADE 301 302 /* 303 * PMC Event Numbers 304 * 305 * These are generated from the definitions in "dev/hwpmc/pmc_events.h". 306 */ 307 308 enum pmc_event { 309 #undef __PMC_EV 310 #undef __PMC_EV_BLOCK 311 #define __PMC_EV_BLOCK(C,V) PMC_EV_ ## C ## __BLOCK_START = (V) - 1 , 312 #define __PMC_EV(C,N) PMC_EV_ ## C ## _ ## N , 313 __PMC_EVENTS() 314 }; 315 316 /* 317 * PMC SYSCALL INTERFACE 318 */ 319 320 /* 321 * "PMC_OPS" -- these are the commands recognized by the kernel 322 * module, and are used when performing a system call from userland. 323 */ 324 #define __PMC_OPS() \ 325 __PMC_OP(CONFIGURELOG, "Set log file") \ 326 __PMC_OP(FLUSHLOG, "Flush log file") \ 327 __PMC_OP(GETCPUINFO, "Get system CPU information") \ 328 __PMC_OP(GETDRIVERSTATS, "Get driver statistics") \ 329 __PMC_OP(GETMODULEVERSION, "Get module version") \ 330 __PMC_OP(GETPMCINFO, "Get per-cpu PMC information") \ 331 __PMC_OP(PMCADMIN, "Set PMC state") \ 332 __PMC_OP(PMCALLOCATE, "Allocate and configure a PMC") \ 333 __PMC_OP(PMCATTACH, "Attach a PMC to a process") \ 334 __PMC_OP(PMCDETACH, "Detach a PMC from a process") \ 335 __PMC_OP(PMCGETMSR, "Get a PMC's hardware address") \ 336 __PMC_OP(PMCRELEASE, "Release a PMC") \ 337 __PMC_OP(PMCRW, "Read/Set a PMC") \ 338 __PMC_OP(PMCSETCOUNT, "Set initial count/sampling rate") \ 339 __PMC_OP(PMCSTART, "Start a PMC") \ 340 __PMC_OP(PMCSTOP, "Stop a PMC") \ 341 __PMC_OP(WRITELOG, "Write a cookie to the log file") \ 342 __PMC_OP(CLOSELOG, "Close log file") \ 343 __PMC_OP(GETDYNEVENTINFO, "Get dynamic events list") 344 345 346 enum pmc_ops { 347 #undef __PMC_OP 348 #define __PMC_OP(N, D) PMC_OP_##N, 349 __PMC_OPS() 350 }; 351 352 353 /* 354 * Flags used in operations on PMCs. 355 */ 356 357 #define PMC_F_FORCE 0x00000001 /*OP ADMIN force operation */ 358 #define PMC_F_DESCENDANTS 0x00000002 /*OP ALLOCATE track descendants */ 359 #define PMC_F_LOG_PROCCSW 0x00000004 /*OP ALLOCATE track ctx switches */ 360 #define PMC_F_LOG_PROCEXIT 0x00000008 /*OP ALLOCATE log proc exits */ 361 #define PMC_F_NEWVALUE 0x00000010 /*OP RW write new value */ 362 #define PMC_F_OLDVALUE 0x00000020 /*OP RW get old value */ 363 #define PMC_F_KGMON 0x00000040 /*OP ALLOCATE kgmon(8) profiling */ 364 /* V2 API */ 365 #define PMC_F_CALLCHAIN 0x00000080 /*OP ALLOCATE capture callchains */ 366 367 /* internal flags */ 368 #define PMC_F_ATTACHED_TO_OWNER 0x00010000 /*attached to owner*/ 369 #define PMC_F_NEEDS_LOGFILE 0x00020000 /*needs log file */ 370 #define PMC_F_ATTACH_DONE 0x00040000 /*attached at least once */ 371 372 #define PMC_CALLCHAIN_DEPTH_MAX 128 373 374 #define PMC_CC_F_USERSPACE 0x01 /*userspace callchain*/ 375 376 /* 377 * Cookies used to denote allocated PMCs, and the values of PMCs. 378 */ 379 380 typedef uint32_t pmc_id_t; 381 typedef uint64_t pmc_value_t; 382 383 #define PMC_ID_INVALID (~ (pmc_id_t) 0) 384 385 /* 386 * PMC IDs have the following format: 387 * 388 * +--------+----------+-----------+-----------+ 389 * | CPU | PMC MODE | PMC CLASS | ROW INDEX | 390 * +--------+----------+-----------+-----------+ 391 * 392 * where each field is 8 bits wide. Field 'CPU' is set to the 393 * requested CPU for system-wide PMCs or PMC_CPU_ANY for process-mode 394 * PMCs. Field 'PMC MODE' is the allocated PMC mode. Field 'PMC 395 * CLASS' is the class of the PMC. Field 'ROW INDEX' is the row index 396 * for the PMC. 397 * 398 * The 'ROW INDEX' ranges over 0..NWPMCS where NHWPMCS is the total 399 * number of hardware PMCs on this cpu. 400 */ 401 402 403 #define PMC_ID_TO_ROWINDEX(ID) ((ID) & 0xFF) 404 #define PMC_ID_TO_CLASS(ID) (((ID) & 0xFF00) >> 8) 405 #define PMC_ID_TO_MODE(ID) (((ID) & 0xFF0000) >> 16) 406 #define PMC_ID_TO_CPU(ID) (((ID) & 0xFF000000) >> 24) 407 #define PMC_ID_MAKE_ID(CPU,MODE,CLASS,ROWINDEX) \ 408 ((((CPU) & 0xFF) << 24) | (((MODE) & 0xFF) << 16) | \ 409 (((CLASS) & 0xFF) << 8) | ((ROWINDEX) & 0xFF)) 410 411 /* 412 * Data structures for system calls supported by the pmc driver. 413 */ 414 415 /* 416 * OP PMCALLOCATE 417 * 418 * Allocate a PMC on the named CPU. 419 */ 420 421 #define PMC_CPU_ANY ~0 422 423 struct pmc_op_pmcallocate { 424 uint32_t pm_caps; /* PMC_CAP_* */ 425 uint32_t pm_cpu; /* CPU number or PMC_CPU_ANY */ 426 enum pmc_class pm_class; /* class of PMC desired */ 427 enum pmc_event pm_ev; /* [enum pmc_event] desired */ 428 uint32_t pm_flags; /* additional modifiers PMC_F_* */ 429 enum pmc_mode pm_mode; /* desired mode */ 430 pmc_id_t pm_pmcid; /* [return] process pmc id */ 431 432 union pmc_md_op_pmcallocate pm_md; /* MD layer extensions */ 433 }; 434 435 /* 436 * OP PMCADMIN 437 * 438 * Set the administrative state (i.e., whether enabled or disabled) of 439 * a PMC 'pm_pmc' on CPU 'pm_cpu'. Note that 'pm_pmc' specifies an 440 * absolute PMC number and need not have been first allocated by the 441 * calling process. 442 */ 443 444 struct pmc_op_pmcadmin { 445 int pm_cpu; /* CPU# */ 446 uint32_t pm_flags; /* flags */ 447 int pm_pmc; /* PMC# */ 448 enum pmc_state pm_state; /* desired state */ 449 }; 450 451 /* 452 * OP PMCATTACH / OP PMCDETACH 453 * 454 * Attach/detach a PMC and a process. 455 */ 456 457 struct pmc_op_pmcattach { 458 pmc_id_t pm_pmc; /* PMC to attach to */ 459 pid_t pm_pid; /* target process */ 460 }; 461 462 /* 463 * OP PMCSETCOUNT 464 * 465 * Set the sampling rate (i.e., the reload count) for statistical counters. 466 * 'pm_pmcid' need to have been previously allocated using PMCALLOCATE. 467 */ 468 469 struct pmc_op_pmcsetcount { 470 pmc_value_t pm_count; /* initial/sample count */ 471 pmc_id_t pm_pmcid; /* PMC id to set */ 472 }; 473 474 475 /* 476 * OP PMCRW 477 * 478 * Read the value of a PMC named by 'pm_pmcid'. 'pm_pmcid' needs 479 * to have been previously allocated using PMCALLOCATE. 480 */ 481 482 483 struct pmc_op_pmcrw { 484 uint32_t pm_flags; /* PMC_F_{OLD,NEW}VALUE*/ 485 pmc_id_t pm_pmcid; /* pmc id */ 486 pmc_value_t pm_value; /* new&returned value */ 487 }; 488 489 490 /* 491 * OP GETPMCINFO 492 * 493 * retrieve PMC state for a named CPU. The caller is expected to 494 * allocate 'npmc' * 'struct pmc_info' bytes of space for the return 495 * values. 496 */ 497 498 struct pmc_info { 499 char pm_name[PMC_NAME_MAX]; /* pmc name */ 500 enum pmc_class pm_class; /* enum pmc_class */ 501 int pm_enabled; /* whether enabled */ 502 enum pmc_disp pm_rowdisp; /* FREE, THREAD or STANDLONE */ 503 pid_t pm_ownerpid; /* owner, or -1 */ 504 enum pmc_mode pm_mode; /* current mode [enum pmc_mode] */ 505 enum pmc_event pm_event; /* current event */ 506 uint32_t pm_flags; /* current flags */ 507 pmc_value_t pm_reloadcount; /* sampling counters only */ 508 }; 509 510 struct pmc_op_getpmcinfo { 511 int32_t pm_cpu; /* 0 <= cpu < mp_maxid */ 512 struct pmc_info pm_pmcs[]; /* space for 'npmc' structures */ 513 }; 514 515 516 /* 517 * OP GETCPUINFO 518 * 519 * Retrieve system CPU information. 520 */ 521 522 523 struct pmc_classinfo { 524 enum pmc_class pm_class; /* class id */ 525 uint32_t pm_caps; /* counter capabilities */ 526 uint32_t pm_width; /* width of the PMC */ 527 uint32_t pm_num; /* number of PMCs in class */ 528 }; 529 530 struct pmc_op_getcpuinfo { 531 enum pmc_cputype pm_cputype; /* what kind of CPU */ 532 uint32_t pm_ncpu; /* max CPU number */ 533 uint32_t pm_npmc; /* #PMCs per CPU */ 534 uint32_t pm_nclass; /* #classes of PMCs */ 535 struct pmc_classinfo pm_classes[PMC_CLASS_MAX]; 536 }; 537 538 /* 539 * OP CONFIGURELOG 540 * 541 * Configure a log file for writing system-wide statistics to. 542 */ 543 544 struct pmc_op_configurelog { 545 int pm_flags; 546 int pm_logfd; /* logfile fd (or -1) */ 547 }; 548 549 /* 550 * OP GETDRIVERSTATS 551 * 552 * Retrieve pmc(4) driver-wide statistics. 553 */ 554 555 struct pmc_op_getdriverstats { 556 unsigned int pm_intr_ignored; /* #interrupts ignored */ 557 unsigned int pm_intr_processed; /* #interrupts processed */ 558 unsigned int pm_intr_bufferfull; /* #interrupts with ENOSPC */ 559 unsigned int pm_syscalls; /* #syscalls */ 560 unsigned int pm_syscall_errors; /* #syscalls with errors */ 561 unsigned int pm_buffer_requests; /* #buffer requests */ 562 unsigned int pm_buffer_requests_failed; /* #failed buffer requests */ 563 unsigned int pm_log_sweeps; /* #sample buffer processing 564 passes */ 565 }; 566 567 /* 568 * OP RELEASE / OP START / OP STOP 569 * 570 * Simple operations on a PMC id. 571 */ 572 573 struct pmc_op_simple { 574 pmc_id_t pm_pmcid; 575 }; 576 577 /* 578 * OP WRITELOG 579 * 580 * Flush the current log buffer and write 4 bytes of user data to it. 581 */ 582 583 struct pmc_op_writelog { 584 uint32_t pm_userdata; 585 }; 586 587 /* 588 * OP GETMSR 589 * 590 * Retrieve the machine specific address assoicated with the allocated 591 * PMC. This number can be used subsequently with a read-performance-counter 592 * instruction. 593 */ 594 595 struct pmc_op_getmsr { 596 uint32_t pm_msr; /* machine specific address */ 597 pmc_id_t pm_pmcid; /* allocated pmc id */ 598 }; 599 600 /* 601 * OP GETDYNEVENTINFO 602 * 603 * Retrieve a PMC dynamic class events list. 604 */ 605 606 struct pmc_dyn_event_descr { 607 char pm_ev_name[PMC_NAME_MAX]; 608 enum pmc_event pm_ev_code; 609 }; 610 611 struct pmc_op_getdyneventinfo { 612 enum pmc_class pm_class; 613 unsigned int pm_nevent; 614 struct pmc_dyn_event_descr pm_events[PMC_EV_DYN_COUNT]; 615 }; 616 617 #ifdef _KERNEL 618 619 #include <sys/malloc.h> 620 #include <sys/sysctl.h> 621 #include <sys/_cpuset.h> 622 623 #include <machine/frame.h> 624 625 #define PMC_HASH_SIZE 1024 626 #define PMC_MTXPOOL_SIZE 2048 627 #define PMC_LOG_BUFFER_SIZE 4 628 #define PMC_NLOGBUFFERS 1024 629 #define PMC_NSAMPLES 1024 630 #define PMC_CALLCHAIN_DEPTH 32 631 632 #define PMC_SYSCTL_NAME_PREFIX "kern." PMC_MODULE_NAME "." 633 634 /* 635 * Locking keys 636 * 637 * (b) - pmc_bufferlist_mtx (spin lock) 638 * (k) - pmc_kthread_mtx (sleep lock) 639 * (o) - po->po_mtx (spin lock) 640 */ 641 642 /* 643 * PMC commands 644 */ 645 646 struct pmc_syscall_args { 647 register_t pmop_code; /* one of PMC_OP_* */ 648 void *pmop_data; /* syscall parameter */ 649 }; 650 651 /* 652 * Interface to processor specific s1tuff 653 */ 654 655 /* 656 * struct pmc_descr 657 * 658 * Machine independent (i.e., the common parts) of a human readable 659 * PMC description. 660 */ 661 662 struct pmc_descr { 663 char pd_name[PMC_NAME_MAX]; /* name */ 664 uint32_t pd_caps; /* capabilities */ 665 enum pmc_class pd_class; /* class of the PMC */ 666 uint32_t pd_width; /* width in bits */ 667 }; 668 669 /* 670 * struct pmc_target 671 * 672 * This structure records all the target processes associated with a 673 * PMC. 674 */ 675 676 struct pmc_target { 677 LIST_ENTRY(pmc_target) pt_next; 678 struct pmc_process *pt_process; /* target descriptor */ 679 }; 680 681 /* 682 * struct pmc 683 * 684 * Describes each allocated PMC. 685 * 686 * Each PMC has precisely one owner, namely the process that allocated 687 * the PMC. 688 * 689 * A PMC may be attached to multiple target processes. The 690 * 'pm_targets' field links all the target processes being monitored 691 * by this PMC. 692 * 693 * The 'pm_savedvalue' field is protected by a mutex. 694 * 695 * On a multi-cpu machine, multiple target threads associated with a 696 * process-virtual PMC could be concurrently executing on different 697 * CPUs. The 'pm_runcount' field is atomically incremented every time 698 * the PMC gets scheduled on a CPU and atomically decremented when it 699 * get descheduled. Deletion of a PMC is only permitted when this 700 * field is '0'. 701 * 702 */ 703 704 struct pmc { 705 LIST_HEAD(,pmc_target) pm_targets; /* list of target processes */ 706 LIST_ENTRY(pmc) pm_next; /* owner's list */ 707 708 /* 709 * System-wide PMCs are allocated on a CPU and are not moved 710 * around. For system-wide PMCs we record the CPU the PMC was 711 * allocated on in the 'CPU' field of the pmc ID. 712 * 713 * Virtual PMCs run on whichever CPU is currently executing 714 * their targets' threads. For these PMCs we need to save 715 * their current PMC counter values when they are taken off 716 * CPU. 717 */ 718 719 union { 720 pmc_value_t pm_savedvalue; /* Virtual PMCS */ 721 } pm_gv; 722 723 /* 724 * For sampling mode PMCs, we keep track of the PMC's "reload 725 * count", which is the counter value to be loaded in when 726 * arming the PMC for the next counting session. For counting 727 * modes on PMCs that are read-only (e.g., the x86 TSC), we 728 * keep track of the initial value at the start of 729 * counting-mode operation. 730 */ 731 732 union { 733 pmc_value_t pm_reloadcount; /* sampling PMC modes */ 734 pmc_value_t pm_initial; /* counting PMC modes */ 735 } pm_sc; 736 737 volatile cpuset_t pm_stalled; /* marks stalled sampling PMCs */ 738 volatile cpuset_t pm_cpustate; /* CPUs where PMC should be active */ 739 uint32_t pm_caps; /* PMC capabilities */ 740 enum pmc_event pm_event; /* event being measured */ 741 uint32_t pm_flags; /* additional flags PMC_F_... */ 742 struct pmc_owner *pm_owner; /* owner thread state */ 743 int pm_runcount; /* #cpus currently on */ 744 enum pmc_state pm_state; /* current PMC state */ 745 746 /* 747 * The PMC ID field encodes the row-index for the PMC, its 748 * mode, class and the CPU# associated with the PMC. 749 */ 750 751 pmc_id_t pm_id; /* allocated PMC id */ 752 753 /* md extensions */ 754 union pmc_md_pmc pm_md; 755 }; 756 757 /* 758 * Accessor macros for 'struct pmc' 759 */ 760 761 #define PMC_TO_MODE(P) PMC_ID_TO_MODE((P)->pm_id) 762 #define PMC_TO_CLASS(P) PMC_ID_TO_CLASS((P)->pm_id) 763 #define PMC_TO_ROWINDEX(P) PMC_ID_TO_ROWINDEX((P)->pm_id) 764 #define PMC_TO_CPU(P) PMC_ID_TO_CPU((P)->pm_id) 765 766 767 /* 768 * struct pmc_process 769 * 770 * Record a 'target' process being profiled. 771 * 772 * The target process being profiled could be different from the owner 773 * process which allocated the PMCs. Each target process descriptor 774 * is associated with NHWPMC 'struct pmc *' pointers. Each PMC at a 775 * given hardware row-index 'n' will use slot 'n' of the 'pp_pmcs[]' 776 * array. The size of this structure is thus PMC architecture 777 * dependent. 778 * 779 */ 780 781 struct pmc_targetstate { 782 struct pmc *pp_pmc; /* target PMC */ 783 pmc_value_t pp_pmcval; /* per-process value */ 784 }; 785 786 struct pmc_process { 787 LIST_ENTRY(pmc_process) pp_next; /* hash chain */ 788 int pp_refcnt; /* reference count */ 789 uint32_t pp_flags; /* flags PMC_PP_* */ 790 struct proc *pp_proc; /* target thread */ 791 struct pmc_targetstate pp_pmcs[]; /* NHWPMCs */ 792 }; 793 794 #define PMC_PP_ENABLE_MSR_ACCESS 0x00000001 795 796 /* 797 * struct pmc_owner 798 * 799 * We associate a PMC with an 'owner' process. 800 * 801 * A process can be associated with 0..NCPUS*NHWPMC PMCs during its 802 * lifetime, where NCPUS is the numbers of CPUS in the system and 803 * NHWPMC is the number of hardware PMCs per CPU. These are 804 * maintained in the list headed by the 'po_pmcs' to save on space. 805 * 806 */ 807 808 struct pmc_owner { 809 LIST_ENTRY(pmc_owner) po_next; /* hash chain */ 810 LIST_ENTRY(pmc_owner) po_ssnext; /* list of SS PMC owners */ 811 LIST_HEAD(, pmc) po_pmcs; /* owned PMC list */ 812 TAILQ_HEAD(, pmclog_buffer) po_logbuffers; /* (o) logbuffer list */ 813 struct mtx po_mtx; /* spin lock for (o) */ 814 struct proc *po_owner; /* owner proc */ 815 uint32_t po_flags; /* (k) flags PMC_PO_* */ 816 struct proc *po_kthread; /* (k) helper kthread */ 817 struct pmclog_buffer *po_curbuf; /* current log buffer */ 818 struct file *po_file; /* file reference */ 819 int po_error; /* recorded error */ 820 short po_sscount; /* # SS PMCs owned */ 821 short po_logprocmaps; /* global mappings done */ 822 }; 823 824 #define PMC_PO_OWNS_LOGFILE 0x00000001 /* has a log file */ 825 #define PMC_PO_SHUTDOWN 0x00000010 /* in the process of shutdown */ 826 #define PMC_PO_INITIAL_MAPPINGS_DONE 0x00000020 827 828 /* 829 * struct pmc_hw -- describe the state of the PMC hardware 830 * 831 * When in use, a HW PMC is associated with one allocated 'struct pmc' 832 * pointed to by field 'phw_pmc'. When inactive, this field is NULL. 833 * 834 * On an SMP box, one or more HW PMC's in process virtual mode with 835 * the same 'phw_pmc' could be executing on different CPUs. In order 836 * to handle this case correctly, we need to ensure that only 837 * incremental counts get added to the saved value in the associated 838 * 'struct pmc'. The 'phw_save' field is used to keep the saved PMC 839 * value at the time the hardware is started during this context 840 * switch (i.e., the difference between the new (hardware) count and 841 * the saved count is atomically added to the count field in 'struct 842 * pmc' at context switch time). 843 * 844 */ 845 846 struct pmc_hw { 847 uint32_t phw_state; /* see PHW_* macros below */ 848 struct pmc *phw_pmc; /* current thread PMC */ 849 }; 850 851 #define PMC_PHW_RI_MASK 0x000000FF 852 #define PMC_PHW_CPU_SHIFT 8 853 #define PMC_PHW_CPU_MASK 0x0000FF00 854 #define PMC_PHW_FLAGS_SHIFT 16 855 #define PMC_PHW_FLAGS_MASK 0xFFFF0000 856 857 #define PMC_PHW_INDEX_TO_STATE(ri) ((ri) & PMC_PHW_RI_MASK) 858 #define PMC_PHW_STATE_TO_INDEX(state) ((state) & PMC_PHW_RI_MASK) 859 #define PMC_PHW_CPU_TO_STATE(cpu) (((cpu) << PMC_PHW_CPU_SHIFT) & \ 860 PMC_PHW_CPU_MASK) 861 #define PMC_PHW_STATE_TO_CPU(state) (((state) & PMC_PHW_CPU_MASK) >> \ 862 PMC_PHW_CPU_SHIFT) 863 #define PMC_PHW_FLAGS_TO_STATE(flags) (((flags) << PMC_PHW_FLAGS_SHIFT) & \ 864 PMC_PHW_FLAGS_MASK) 865 #define PMC_PHW_STATE_TO_FLAGS(state) (((state) & PMC_PHW_FLAGS_MASK) >> \ 866 PMC_PHW_FLAGS_SHIFT) 867 #define PMC_PHW_FLAG_IS_ENABLED (PMC_PHW_FLAGS_TO_STATE(0x01)) 868 #define PMC_PHW_FLAG_IS_SHAREABLE (PMC_PHW_FLAGS_TO_STATE(0x02)) 869 870 /* 871 * struct pmc_sample 872 * 873 * Space for N (tunable) PC samples and associated control data. 874 */ 875 876 struct pmc_sample { 877 uint16_t ps_nsamples; /* callchain depth */ 878 uint8_t ps_cpu; /* cpu number */ 879 uint8_t ps_flags; /* other flags */ 880 pid_t ps_pid; /* process PID or -1 */ 881 struct thread *ps_td; /* which thread */ 882 struct pmc *ps_pmc; /* interrupting PMC */ 883 uintptr_t *ps_pc; /* (const) callchain start */ 884 }; 885 886 #define PMC_SAMPLE_FREE ((uint16_t) 0) 887 #define PMC_SAMPLE_INUSE ((uint16_t) 0xFFFF) 888 889 struct pmc_samplebuffer { 890 struct pmc_sample * volatile ps_read; /* read pointer */ 891 struct pmc_sample * volatile ps_write; /* write pointer */ 892 uintptr_t *ps_callchains; /* all saved call chains */ 893 struct pmc_sample *ps_fence; /* one beyond ps_samples[] */ 894 struct pmc_sample ps_samples[]; /* array of sample entries */ 895 }; 896 897 898 /* 899 * struct pmc_cpustate 900 * 901 * A CPU is modelled as a collection of HW PMCs with space for additional 902 * flags. 903 */ 904 905 struct pmc_cpu { 906 uint32_t pc_state; /* physical cpu number + flags */ 907 struct pmc_samplebuffer *pc_sb[2]; /* space for samples */ 908 struct pmc_hw *pc_hwpmcs[]; /* 'npmc' pointers */ 909 }; 910 911 #define PMC_PCPU_CPU_MASK 0x000000FF 912 #define PMC_PCPU_FLAGS_MASK 0xFFFFFF00 913 #define PMC_PCPU_FLAGS_SHIFT 8 914 #define PMC_PCPU_STATE_TO_CPU(S) ((S) & PMC_PCPU_CPU_MASK) 915 #define PMC_PCPU_STATE_TO_FLAGS(S) (((S) & PMC_PCPU_FLAGS_MASK) >> PMC_PCPU_FLAGS_SHIFT) 916 #define PMC_PCPU_FLAGS_TO_STATE(F) (((F) << PMC_PCPU_FLAGS_SHIFT) & PMC_PCPU_FLAGS_MASK) 917 #define PMC_PCPU_CPU_TO_STATE(C) ((C) & PMC_PCPU_CPU_MASK) 918 #define PMC_PCPU_FLAG_HTT (PMC_PCPU_FLAGS_TO_STATE(0x1)) 919 920 /* 921 * struct pmc_binding 922 * 923 * CPU binding information. 924 */ 925 926 struct pmc_binding { 927 int pb_bound; /* is bound? */ 928 int pb_cpu; /* if so, to which CPU */ 929 }; 930 931 932 struct pmc_mdep; 933 934 /* 935 * struct pmc_classdep 936 * 937 * PMC class-dependent operations. 938 */ 939 struct pmc_classdep { 940 uint32_t pcd_caps; /* class capabilities */ 941 enum pmc_class pcd_class; /* class id */ 942 int pcd_num; /* number of PMCs */ 943 int pcd_ri; /* row index of the first PMC in class */ 944 int pcd_width; /* width of the PMC */ 945 946 /* configuring/reading/writing the hardware PMCs */ 947 int (*pcd_config_pmc)(int _cpu, int _ri, struct pmc *_pm); 948 int (*pcd_get_config)(int _cpu, int _ri, struct pmc **_ppm); 949 int (*pcd_read_pmc)(int _cpu, int _ri, pmc_value_t *_value); 950 int (*pcd_write_pmc)(int _cpu, int _ri, pmc_value_t _value); 951 952 /* pmc allocation/release */ 953 int (*pcd_allocate_pmc)(int _cpu, int _ri, struct pmc *_t, 954 const struct pmc_op_pmcallocate *_a); 955 int (*pcd_release_pmc)(int _cpu, int _ri, struct pmc *_pm); 956 957 /* starting and stopping PMCs */ 958 int (*pcd_start_pmc)(int _cpu, int _ri); 959 int (*pcd_stop_pmc)(int _cpu, int _ri); 960 961 /* description */ 962 int (*pcd_describe)(int _cpu, int _ri, struct pmc_info *_pi, 963 struct pmc **_ppmc); 964 965 /* class-dependent initialization & finalization */ 966 int (*pcd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 967 int (*pcd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 968 969 /* machine-specific interface */ 970 int (*pcd_get_msr)(int _ri, uint32_t *_msr); 971 }; 972 973 /* 974 * struct pmc_mdep 975 * 976 * Machine dependent bits needed per CPU type. 977 */ 978 979 struct pmc_mdep { 980 uint32_t pmd_cputype; /* from enum pmc_cputype */ 981 uint32_t pmd_npmc; /* number of PMCs per CPU */ 982 uint32_t pmd_nclass; /* number of PMC classes present */ 983 984 /* 985 * Machine dependent methods. 986 */ 987 988 /* per-cpu initialization and finalization */ 989 int (*pmd_pcpu_init)(struct pmc_mdep *_md, int _cpu); 990 int (*pmd_pcpu_fini)(struct pmc_mdep *_md, int _cpu); 991 992 /* thread context switch in/out */ 993 int (*pmd_switch_in)(struct pmc_cpu *_p, struct pmc_process *_pp); 994 int (*pmd_switch_out)(struct pmc_cpu *_p, struct pmc_process *_pp); 995 996 /* handle a PMC interrupt */ 997 int (*pmd_intr)(int _cpu, struct trapframe *_tf); 998 999 /* 1000 * PMC class dependent information. 1001 */ 1002 struct pmc_classdep pmd_classdep[]; 1003 }; 1004 1005 /* 1006 * Per-CPU state. This is an array of 'mp_ncpu' pointers 1007 * to struct pmc_cpu descriptors. 1008 */ 1009 1010 extern struct pmc_cpu **pmc_pcpu; 1011 1012 /* driver statistics */ 1013 extern struct pmc_op_getdriverstats pmc_stats; 1014 1015 #if defined(HWPMC_DEBUG) 1016 #include <sys/ktr.h> 1017 1018 /* debug flags, major flag groups */ 1019 struct pmc_debugflags { 1020 int pdb_CPU; 1021 int pdb_CSW; 1022 int pdb_LOG; 1023 int pdb_MDP; 1024 int pdb_MOD; 1025 int pdb_OWN; 1026 int pdb_PMC; 1027 int pdb_PRC; 1028 int pdb_SAM; 1029 }; 1030 1031 extern struct pmc_debugflags pmc_debugflags; 1032 1033 #define KTR_PMC KTR_SUBSYS 1034 1035 #define PMC_DEBUG_STRSIZE 128 1036 #define PMC_DEBUG_DEFAULT_FLAGS { 0, 0, 0, 0, 0, 0, 0, 0 } 1037 1038 #define PMCDBG0(M, N, L, F) do { \ 1039 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1040 CTR0(KTR_PMC, #M ":" #N ":" #L ": " F); \ 1041 } while (0) 1042 #define PMCDBG1(M, N, L, F, p1) do { \ 1043 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1044 CTR1(KTR_PMC, #M ":" #N ":" #L ": " F, p1); \ 1045 } while (0) 1046 #define PMCDBG2(M, N, L, F, p1, p2) do { \ 1047 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1048 CTR2(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2); \ 1049 } while (0) 1050 #define PMCDBG3(M, N, L, F, p1, p2, p3) do { \ 1051 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1052 CTR3(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3); \ 1053 } while (0) 1054 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) do { \ 1055 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1056 CTR4(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4);\ 1057 } while (0) 1058 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) do { \ 1059 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1060 CTR5(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1061 p5); \ 1062 } while (0) 1063 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) do { \ 1064 if (pmc_debugflags.pdb_ ## M & (1 << PMC_DEBUG_MIN_ ## N)) \ 1065 CTR6(KTR_PMC, #M ":" #N ":" #L ": " F, p1, p2, p3, p4, \ 1066 p5, p6); \ 1067 } while (0) 1068 1069 /* Major numbers */ 1070 #define PMC_DEBUG_MAJ_CPU 0 /* cpu switches */ 1071 #define PMC_DEBUG_MAJ_CSW 1 /* context switches */ 1072 #define PMC_DEBUG_MAJ_LOG 2 /* logging */ 1073 #define PMC_DEBUG_MAJ_MDP 3 /* machine dependent */ 1074 #define PMC_DEBUG_MAJ_MOD 4 /* misc module infrastructure */ 1075 #define PMC_DEBUG_MAJ_OWN 5 /* owner */ 1076 #define PMC_DEBUG_MAJ_PMC 6 /* pmc management */ 1077 #define PMC_DEBUG_MAJ_PRC 7 /* processes */ 1078 #define PMC_DEBUG_MAJ_SAM 8 /* sampling */ 1079 1080 /* Minor numbers */ 1081 1082 /* Common (8 bits) */ 1083 #define PMC_DEBUG_MIN_ALL 0 /* allocation */ 1084 #define PMC_DEBUG_MIN_REL 1 /* release */ 1085 #define PMC_DEBUG_MIN_OPS 2 /* ops: start, stop, ... */ 1086 #define PMC_DEBUG_MIN_INI 3 /* init */ 1087 #define PMC_DEBUG_MIN_FND 4 /* find */ 1088 1089 /* MODULE */ 1090 #define PMC_DEBUG_MIN_PMH 14 /* pmc_hook */ 1091 #define PMC_DEBUG_MIN_PMS 15 /* pmc_syscall */ 1092 1093 /* OWN */ 1094 #define PMC_DEBUG_MIN_ORM 8 /* owner remove */ 1095 #define PMC_DEBUG_MIN_OMR 9 /* owner maybe remove */ 1096 1097 /* PROCESSES */ 1098 #define PMC_DEBUG_MIN_TLK 8 /* link target */ 1099 #define PMC_DEBUG_MIN_TUL 9 /* unlink target */ 1100 #define PMC_DEBUG_MIN_EXT 10 /* process exit */ 1101 #define PMC_DEBUG_MIN_EXC 11 /* process exec */ 1102 #define PMC_DEBUG_MIN_FRK 12 /* process fork */ 1103 #define PMC_DEBUG_MIN_ATT 13 /* attach/detach */ 1104 #define PMC_DEBUG_MIN_SIG 14 /* signalling */ 1105 1106 /* CONTEXT SWITCHES */ 1107 #define PMC_DEBUG_MIN_SWI 8 /* switch in */ 1108 #define PMC_DEBUG_MIN_SWO 9 /* switch out */ 1109 1110 /* PMC */ 1111 #define PMC_DEBUG_MIN_REG 8 /* pmc register */ 1112 #define PMC_DEBUG_MIN_ALR 9 /* allocate row */ 1113 1114 /* MACHINE DEPENDENT LAYER */ 1115 #define PMC_DEBUG_MIN_REA 8 /* read */ 1116 #define PMC_DEBUG_MIN_WRI 9 /* write */ 1117 #define PMC_DEBUG_MIN_CFG 10 /* config */ 1118 #define PMC_DEBUG_MIN_STA 11 /* start */ 1119 #define PMC_DEBUG_MIN_STO 12 /* stop */ 1120 #define PMC_DEBUG_MIN_INT 13 /* interrupts */ 1121 1122 /* CPU */ 1123 #define PMC_DEBUG_MIN_BND 8 /* bind */ 1124 #define PMC_DEBUG_MIN_SEL 9 /* select */ 1125 1126 /* LOG */ 1127 #define PMC_DEBUG_MIN_GTB 8 /* get buf */ 1128 #define PMC_DEBUG_MIN_SIO 9 /* schedule i/o */ 1129 #define PMC_DEBUG_MIN_FLS 10 /* flush */ 1130 #define PMC_DEBUG_MIN_SAM 11 /* sample */ 1131 #define PMC_DEBUG_MIN_CLO 12 /* close */ 1132 1133 #else 1134 #define PMCDBG0(M, N, L, F) /* nothing */ 1135 #define PMCDBG1(M, N, L, F, p1) 1136 #define PMCDBG2(M, N, L, F, p1, p2) 1137 #define PMCDBG3(M, N, L, F, p1, p2, p3) 1138 #define PMCDBG4(M, N, L, F, p1, p2, p3, p4) 1139 #define PMCDBG5(M, N, L, F, p1, p2, p3, p4, p5) 1140 #define PMCDBG6(M, N, L, F, p1, p2, p3, p4, p5, p6) 1141 #endif 1142 1143 /* declare a dedicated memory pool */ 1144 MALLOC_DECLARE(M_PMC); 1145 1146 /* 1147 * Functions 1148 */ 1149 1150 struct pmc_mdep *pmc_md_initialize(void); /* MD init function */ 1151 void pmc_md_finalize(struct pmc_mdep *_md); /* MD fini function */ 1152 int pmc_getrowdisp(int _ri); 1153 int pmc_process_interrupt(int _cpu, int _soft, struct pmc *_pm, 1154 struct trapframe *_tf, int _inuserspace); 1155 int pmc_save_kernel_callchain(uintptr_t *_cc, int _maxsamples, 1156 struct trapframe *_tf); 1157 int pmc_save_user_callchain(uintptr_t *_cc, int _maxsamples, 1158 struct trapframe *_tf); 1159 struct pmc_mdep *pmc_mdep_alloc(int nclasses); 1160 void pmc_mdep_free(struct pmc_mdep *md); 1161 #endif /* _KERNEL */ 1162 #endif /* _SYS_PMC_H_ */ 1163