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Searched refs:OL (Results 1 – 25 of 58) sorted by relevance

123

/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcTargetMachine.cpp61 CodeGenOpt::Level OL, bool is64bit) in SparcTargetMachine() argument
63 RM, CM, OL), in SparcTargetMachine()
113 CodeGenOpt::Level OL) in SparcV8TargetMachine() argument
114 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in SparcV8TargetMachine()
122 CodeGenOpt::Level OL) in SparcV9TargetMachine() argument
123 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in SparcV9TargetMachine()
131 CodeGenOpt::Level OL) in SparcelTargetMachine() argument
132 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in SparcelTargetMachine()
HDSparcTargetMachine.h29 Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
52 CodeGenOpt::Level OL);
63 CodeGenOpt::Level OL);
73 CodeGenOpt::Level OL);
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMTargetMachine.cpp176 CodeGenOpt::Level OL, bool isLittle) in ARMBaseTargetMachine() argument
178 CPU, FS, Options, RM, CM, OL), in ARMBaseTargetMachine()
239 CodeGenOpt::Level OL, bool isLittle) in ARMTargetMachine() argument
240 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) { in ARMTargetMachine()
253 CodeGenOpt::Level OL) in ARMLETargetMachine() argument
254 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in ARMLETargetMachine()
262 CodeGenOpt::Level OL) in ARMBETargetMachine() argument
263 : ARMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in ARMBETargetMachine()
271 CodeGenOpt::Level OL, bool isLittle) in ThumbTargetMachine() argument
272 : ARMBaseTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, isLittle) { in ThumbTargetMachine()
[all …]
HDARMTargetMachine.h42 CodeGenOpt::Level OL, bool isLittle);
67 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
78 CodeGenOpt::Level OL);
89 CodeGenOpt::Level OL);
101 Reloc::Model RM, CodeModel::Model CM, CodeGenOpt::Level OL,
113 CodeGenOpt::Level OL);
124 CodeGenOpt::Level OL);
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCTargetMachine.cpp101 static std::string computeFSAdditions(StringRef FS, CodeGenOpt::Level OL, in computeFSAdditions() argument
113 if (OL >= CodeGenOpt::Default) { in computeFSAdditions()
120 if (OL != CodeGenOpt::None) { in computeFSAdditions()
171 CodeGenOpt::Level OL) in PPCTargetMachine() argument
173 computeFSAdditions(FS, OL, TT), Options, RM, CM, OL), in PPCTargetMachine()
176 Subtarget(TargetTriple, CPU, computeFSAdditions(FS, OL, TT), *this) { in PPCTargetMachine()
206 CodeGenOpt::Level OL) in PPC32TargetMachine() argument
207 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {} in PPC32TargetMachine()
215 CodeGenOpt::Level OL) in PPC64TargetMachine() argument
216 : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL) {} in PPC64TargetMachine()
HDPPCTargetMachine.h39 CodeModel::Model CM, CodeGenOpt::Level OL);
68 CodeGenOpt::Level OL);
79 CodeGenOpt::Level OL);
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXTargetMachine.cpp92 CodeGenOpt::Level OL, bool is64bit) in NVPTXTargetMachine() argument
94 CM, OL), in NVPTXTargetMachine()
112 CodeGenOpt::Level OL) in NVPTXTargetMachine32() argument
113 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in NVPTXTargetMachine32()
121 CodeGenOpt::Level OL) in NVPTXTargetMachine64() argument
122 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in NVPTXTargetMachine64()
HDNVPTXTargetMachine.h74 CodeGenOpt::Level OL);
83 CodeGenOpt::Level OL);
/NextBSD/contrib/llvm/lib/Target/Mips/
HDMipsTargetMachine.cpp89 CodeGenOpt::Level OL, bool isLittle) in MipsTargetMachine() argument
91 CPU, FS, Options, RM, CM, OL), in MipsTargetMachine()
111 CodeGenOpt::Level OL) in MipsebTargetMachine() argument
112 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in MipsebTargetMachine()
120 CodeGenOpt::Level OL) in MipselTargetMachine() argument
121 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in MipselTargetMachine()
HDMipsTargetMachine.h44 CodeModel::Model CM, CodeGenOpt::Level OL, bool isLittle);
79 CodeGenOpt::Level OL);
90 CodeGenOpt::Level OL);
/NextBSD/contrib/llvm/lib/Target/
HDTargetMachineC.cpp127 CodeGenOpt::Level OL; in LLVMCreateTargetMachine() local
130 OL = CodeGenOpt::None; in LLVMCreateTargetMachine()
133 OL = CodeGenOpt::Less; in LLVMCreateTargetMachine()
136 OL = CodeGenOpt::Aggressive; in LLVMCreateTargetMachine()
139 OL = CodeGenOpt::Default; in LLVMCreateTargetMachine()
145 CM, OL)); in LLVMCreateTargetMachine()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUTargetMachine.h42 CodeModel::Model CM, CodeGenOpt::Level OL);
68 CodeModel::Model CM, CodeGenOpt::Level OL);
82 CodeModel::Model CM, CodeGenOpt::Level OL);
HDAMDGPUTargetMachine.cpp92 CodeModel::Model CM, CodeGenOpt::Level OL) in R600TargetMachine() argument
93 : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {} in R600TargetMachine()
102 CodeModel::Model CM, CodeGenOpt::Level OL) in GCNTargetMachine() argument
103 : AMDGPUTargetMachine(T, TT, FS, CPU, Options, RM, CM, OL) {} in GCNTargetMachine()
/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64TargetMachine.h33 CodeGenOpt::Level OL, bool IsLittleEndian);
60 CodeGenOpt::Level OL);
71 CodeGenOpt::Level OL);
HDAArch64TargetMachine.cpp127 CodeGenOpt::Level OL, in AArch64TargetMachine() argument
132 Options, RM, CM, OL), in AArch64TargetMachine()
169 CodeGenOpt::Level OL) in AArch64leTargetMachine() argument
170 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} in AArch64leTargetMachine()
177 CodeGenOpt::Level OL) in AArch64beTargetMachine() argument
178 : AArch64TargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} in AArch64beTargetMachine()
/NextBSD/contrib/llvm/lib/Target/Sparc/MCTargetDesc/
HDSparcMCTargetDesc.cpp87 CodeGenOpt::Level OL) { in createSparcMCCodeGenInfo() argument
98 X->initMCCodeGenInfo(RM, CM, OL); in createSparcMCCodeGenInfo()
105 CodeGenOpt::Level OL) { in createSparcV9MCCodeGenInfo() argument
120 X->initMCCodeGenInfo(RM, CM, OL); in createSparcV9MCCodeGenInfo()
/NextBSD/contrib/llvm/lib/MC/
HDMCCodeGenInfo.cpp19 CodeGenOpt::Level OL) { in initMCCodeGenInfo() argument
22 OptLevel = OL; in initMCCodeGenInfo()
/NextBSD/contrib/ntp/sntp/m4/
HDhms_search_lib.m48 dnl HMS_SEARCH_LIBS([LIB_MATH], [sqrt], [m], [AIF], [AINF], [OL])
19 dnl [OL])
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430TargetMachine.cpp32 CodeGenOpt::Level OL) in MSP430TargetMachine() argument
34 Options, RM, CM, OL), in MSP430TargetMachine()
/NextBSD/contrib/llvm/lib/Target/BPF/
HDBPFTargetMachine.cpp43 CodeGenOpt::Level OL) in BPFTargetMachine() argument
45 OL), in BPFTargetMachine()
/NextBSD/contrib/llvm/lib/Target/MSP430/MCTargetDesc/
HDMSP430MCTargetDesc.cpp54 CodeGenOpt::Level OL) { in createMSP430MCCodeGenInfo() argument
56 X->initMCCodeGenInfo(RM, CM, OL); in createMSP430MCCodeGenInfo()
/NextBSD/contrib/llvm/lib/Target/NVPTX/MCTargetDesc/
HDNVPTXMCTargetDesc.cpp55 CodeGenOpt::Level OL) { in createNVPTXMCCodeGenInfo() argument
60 X->initMCCodeGenInfo(Reloc::Default, CM, OL); in createNVPTXMCCodeGenInfo()
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreTargetMachine.cpp29 CodeGenOpt::Level OL) in XCoreTargetMachine() argument
32 TT, CPU, FS, Options, RM, CM, OL), in XCoreTargetMachine()
/NextBSD/contrib/llvm/include/llvm/Support/
HDTargetRegistry.h98 CodeGenOpt::Level OL);
108 CodeGenOpt::Level OL);
306 CodeGenOpt::Level OL) const { in createMCCodeGenInfo() argument
309 return MCCodeGenInfoCtorFn(Triple(TT), RM, CM, OL); in createMCCodeGenInfo()
364 CodeGenOpt::Level OL = CodeGenOpt::Default) const {
368 CM, OL);
1098 CodeModel::Model CM, CodeGenOpt::Level OL) { in Allocator()
1099 return new TargetMachineImpl(T, TT, CPU, FS, Options, RM, CM, OL); in Allocator()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/MCTargetDesc/
HDAMDGPUMCTargetDesc.cpp61 CodeGenOpt::Level OL) { in createAMDGPUMCCodeGenInfo() argument
63 X->initMCCodeGenInfo(RM, CM, OL); in createAMDGPUMCCodeGenInfo()

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