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Searched refs:NewMIs (Results 1 – 12 of 12) sorted by relevance

/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCInstrInfo.cpp875 SmallVectorImpl<MachineInstr*> &NewMIs, in StoreRegToStackSlot() argument
883 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STW)) in StoreRegToStackSlot()
889 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STD)) in StoreRegToStackSlot()
894 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFD)) in StoreRegToStackSlot()
899 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STFS)) in StoreRegToStackSlot()
904 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CR)) in StoreRegToStackSlot()
910 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::SPILL_CRBIT)) in StoreRegToStackSlot()
916 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STVX)) in StoreRegToStackSlot()
922 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXVD2X)) in StoreRegToStackSlot()
928 NewMIs.push_back(addFrameReference(BuildMI(MF, DL, get(PPC::STXSDX)) in StoreRegToStackSlot()
[all …]
HDPPCInstrInfo.h74 SmallVectorImpl<MachineInstr*> &NewMIs,
79 SmallVectorImpl<MachineInstr*> &NewMIs,
/NextBSD/contrib/llvm/lib/CodeGen/
HDTwoAddressInstructionPass.cpp1288 SmallVector<MachineInstr *, 2> NewMIs; in tryInstructionTransform() local
1291 NewMIs)) { in tryInstructionTransform()
1295 assert(NewMIs.size() == 2 && in tryInstructionTransform()
1298 NewMIs[1]->addRegisterKilled(Reg, TRI); in tryInstructionTransform()
1302 MBB->insert(mi, NewMIs[0]); in tryInstructionTransform()
1303 MBB->insert(mi, NewMIs[1]); in tryInstructionTransform()
1305 DEBUG(dbgs() << "2addr: NEW LOAD: " << *NewMIs[0] in tryInstructionTransform()
1306 << "2addr: NEW INST: " << *NewMIs[1]); in tryInstructionTransform()
1309 unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); in tryInstructionTransform()
1310 unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); in tryInstructionTransform()
[all …]
HDMachineLICM.cpp1259 SmallVector<MachineInstr *, 2> NewMIs; in ExtractHoistableLoad() local
1263 NewMIs); in ExtractHoistableLoad()
1268 assert(NewMIs.size() == 2 && in ExtractHoistableLoad()
1272 MBB->insert(Pos, NewMIs[0]); in ExtractHoistableLoad()
1273 MBB->insert(Pos, NewMIs[1]); in ExtractHoistableLoad()
1276 if (!IsLoopInvariantInst(*NewMIs[0]) || !IsProfitableToHoist(*NewMIs[0])) { in ExtractHoistableLoad()
1277 NewMIs[0]->eraseFromParent(); in ExtractHoistableLoad()
1278 NewMIs[1]->eraseFromParent(); in ExtractHoistableLoad()
1283 UpdateRegPressure(NewMIs[1]); in ExtractHoistableLoad()
1287 return NewMIs[0]; in ExtractHoistableLoad()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrInfo.h309 SmallVectorImpl<MachineInstr*> &NewMIs) const;
322 SmallVectorImpl<MachineInstr*> &NewMIs) const;
355 SmallVectorImpl<MachineInstr*> &NewMIs) const override;
HDX86InstrInfo.cpp4094 SmallVectorImpl<MachineInstr*> &NewMIs) const { in storeRegToAddr()
4105 NewMIs.push_back(MIB); in storeRegToAddr()
4129 SmallVectorImpl<MachineInstr*> &NewMIs) const { in loadRegFromAddr()
4139 NewMIs.push_back(MIB); in loadRegFromAddr()
5521 SmallVectorImpl<MachineInstr*> &NewMIs) const { in unfoldMemoryOperand()
5568 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs); in unfoldMemoryOperand()
5572 MachineOperand &MO = NewMIs[0]->getOperand(i); in unfoldMemoryOperand()
5629 NewMIs.push_back(DataMI); in unfoldMemoryOperand()
5638 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs); in unfoldMemoryOperand()
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonInstrInfo.h93 SmallVectorImpl<MachineInstr*> &NewMIs) const;
104 SmallVectorImpl<MachineInstr*> &NewMIs) const;
HDHexagonInstrInfo.cpp648 SmallVectorImpl<MachineInstr*> &NewMIs) const in storeRegToAddr()
688 SmallVectorImpl<MachineInstr*> &NewMIs) const { in loadRegFromAddr()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUInstrInfo.h110 SmallVectorImpl<MachineInstr *> &NewMIs) const override;
HDAMDGPUInstrInfo.cpp176 SmallVectorImpl<MachineInstr*> &NewMIs) const { in unfoldMemoryOperand()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetInstrInfo.h650 SmallPtrSetImpl<MachineInstr *> &NewMIs,
831 SmallVectorImpl<MachineInstr*> &NewMIs) const{ in unfoldMemoryOperand() argument
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMBaseInstrInfo.cpp215 std::vector<MachineInstr*> NewMIs; in convertToThreeAddress() local
225 NewMIs.push_back(MemMI); in convertToThreeAddress()
226 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
238 NewMIs.push_back(UpdateMI); in convertToThreeAddress()
239 NewMIs.push_back(MemMI); in convertToThreeAddress()
258 MachineInstr *NewMI = NewMIs[j]; in convertToThreeAddress()
271 MFI->insert(MBBI, NewMIs[1]); in convertToThreeAddress()
272 MFI->insert(MBBI, NewMIs[0]); in convertToThreeAddress()
273 return NewMIs[0]; in convertToThreeAddress()