1 /*- 2 * Copyright (C) 2009-2012 Semihalf 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #ifndef _DEV_NAND_H_ 30 #define _DEV_NAND_H_ 31 32 #include <sys/bus.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/lock.h> 36 #include <sys/sx.h> 37 #include <sys/taskqueue.h> 38 #include <sys/queue.h> 39 #include <sys/bio.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 #include <sys/malloc.h> 43 44 #include <dev/nand/nand_dev.h> 45 46 MALLOC_DECLARE(M_NAND); 47 48 /* Read commands */ 49 #define NAND_CMD_READ 0x00 50 #define NAND_CMD_CHNG_READ_COL 0x05 51 #define NAND_CMD_READ_END 0x30 52 #define NAND_CMD_READ_CACHE 0x31 53 #define NAND_CMD_READ_CPBK 0x35 54 #define NAND_CMD_READ_CACHE_END 0x3F 55 #define NAND_CMD_CHNG_READ_COL_END 0xE0 56 57 /* Erase commands */ 58 #define NAND_CMD_ERASE 0x60 59 #define NAND_CMD_ERASE_END 0xD0 60 #define NAND_CMD_ERASE_INTLV 0xD1 61 62 /* Program commands */ 63 #define NAND_CMD_PROG 0x80 64 #define NAND_CMD_CHNG_WRITE_COL 0x85 65 #define NAND_CMD_PROG_END 0x10 66 #define NAND_CMD_PROG_INTLV 0x11 67 #define NAND_CMD_PROG_CACHE 0x15 68 69 /* Misc commands */ 70 #define NAND_CMD_STATUS 0x70 71 #define NAND_CMD_STATUS_ENH 0x78 72 #define NAND_CMD_READ_ID 0x90 73 #define NAND_CMD_READ_PARAMETER 0xec 74 #define NAND_CMD_READ_UNIQUE_ID 0xed 75 #define NAND_CMD_GET_FEATURE 0xee 76 #define NAND_CMD_SET_FEATURE 0xef 77 78 /* Reset commands */ 79 #define NAND_CMD_SYNCH_RESET 0xfc 80 #define NAND_CMD_RESET 0xff 81 82 /* Small page flash commands */ 83 #define NAND_CMD_SMALLA 0x00 84 #define NAND_CMD_SMALLB 0x01 85 #define NAND_CMD_SMALLOOB 0x50 86 87 #define NAND_STATUS_FAIL 0x1 88 #define NAND_STATUS_FAILC 0x2 89 #define NAND_STATUS_ARDY 0x20 90 #define NAND_STATUS_RDY 0x40 91 #define NAND_STATUS_WP 0x80 92 93 #define NAND_LP_OOB_COLUMN_START 0x800 94 #define NAND_LP_OOBSZ 0x40 95 #define NAND_SP_OOB_COLUMN_START 0x200 96 #define NAND_SP_OOBSZ 0x10 97 98 #define PAGE_PARAM_LENGTH 0x100 99 #define PAGE_PARAMETER_DEF 0x0 100 #define PAGE_PARAMETER_RED_1 0x100 101 #define PAGE_PARAMETER_RED_2 0x200 102 103 #define ONFI_SIG_ADDR 0x20 104 105 #define NAND_MAX_CHIPS 0x4 106 #define NAND_MAX_OOBSZ 512 107 #define NAND_MAX_PAGESZ 16384 108 109 #define NAND_SMALL_PAGE_SIZE 0x200 110 111 #define NAND_16_BIT 0x00000001 112 113 #define NAND_ECC_NONE 0x0 114 #define NAND_ECC_SOFT 0x1 115 #define NAND_ECC_FULLHW 0x2 116 #define NAND_ECC_PARTHW 0x4 117 #define NAND_ECC_MODE_MASK 0x7 118 119 #define ECC_OK 0 120 #define ECC_CORRECTABLE 1 121 #define ECC_ERROR_ECC (-1) 122 #define ECC_UNCORRECTABLE (-2) 123 124 #define NAND_MAN_SAMSUNG 0xec 125 #define NAND_MAN_HYNIX 0xad 126 #define NAND_MAN_STMICRO 0x20 127 #define NAND_MAN_MICRON 0x2c 128 129 struct nand_id { 130 uint8_t man_id; 131 uint8_t dev_id; 132 }; 133 134 struct nand_params { 135 struct nand_id id; 136 char *name; 137 uint32_t chip_size; 138 uint32_t page_size; 139 uint32_t oob_size; 140 uint32_t pages_per_block; 141 uint32_t flags; 142 }; 143 144 /* nand debug levels */ 145 #define NDBG_NAND 0x01 146 #define NDBG_CDEV 0x02 147 #define NDBG_GEN 0x04 148 #define NDBG_GEOM 0x08 149 #define NDBG_BUS 0x10 150 #define NDBG_SIM 0x20 151 #define NDBG_CTRL 0x40 152 #define NDBG_DRV 0x80 153 #define NDBG_ECC 0x100 154 155 /* nand_debug_function */ 156 void nand_debug(int level, const char *fmt, ...); 157 extern int nand_debug_flag; 158 159 /* ONFI features bit*/ 160 #define ONFI_FEAT_16BIT 0x01 161 #define ONFI_FEAT_MULT_LUN 0x02 162 #define ONFI_FEAT_INTLV_OPS 0x04 163 #define ONFI_FEAT_CPBK_RESTRICT 0x08 164 #define ONFI_FEAT_SRC_SYNCH 0x10 165 166 /* ONFI optional commands bits */ 167 #define ONFI_OPTCOM_PROG_CACHE 0x01 168 #define ONFI_OPTCOM_READ_CACHE 0x02 169 #define ONFI_OPTCOM_GETSET_FEAT 0x04 170 #define ONFI_OPTCOM_STATUS_ENH 0x08 171 #define ONFI_OPTCOM_COPYBACK 0x10 172 #define ONFI_OPTCOM_UNIQUE_ID 0x20 173 174 175 /* Layout of parameter page is defined in ONFI */ 176 struct onfi_params { 177 char signature[4]; 178 uint16_t rev; 179 uint16_t features; 180 uint16_t optional_commands; 181 uint8_t primary_advanced_command; 182 uint8_t res1; 183 uint16_t extended_parameter_page_length; 184 uint8_t parameter_page_count; 185 uint8_t res2[17]; 186 char manufacturer_name[12]; 187 char device_model[20]; 188 uint8_t manufacturer_id; 189 uint8_t manufacture_date_yy; 190 uint8_t manufacture_date_ww; 191 uint8_t res3[13]; 192 uint32_t bytes_per_page; 193 uint16_t spare_bytes_per_page; 194 uint32_t bytes_per_partial_page; 195 uint16_t spare_bytes_per_partial_page; 196 uint32_t pages_per_block; 197 uint32_t blocks_per_lun; 198 uint8_t luns; 199 uint8_t address_cycles; 200 uint8_t bits_per_cell; 201 uint16_t max_bad_block_per_lun; 202 uint16_t block_endurance; 203 uint8_t guaranteed_valid_blocks; 204 uint16_t valid_block_endurance; 205 uint8_t programs_per_page; 206 uint8_t partial_prog_attr; 207 uint8_t bits_of_ecc; 208 uint8_t interleaved_addr_bits; 209 uint8_t interleaved_oper_attr; 210 uint8_t eznand_support; 211 uint8_t res4[12]; 212 uint8_t pin_capacitance; 213 uint16_t asynch_timing_mode_support; 214 uint16_t asynch_prog_cache_timing_mode_support; 215 uint16_t t_prog; /* us, max page program time */ 216 uint16_t t_bers; /* us, max block erase time */ 217 uint16_t t_r; /* us, max page read time */ 218 uint16_t t_ccs; /* ns, min change column setup time */ 219 uint16_t source_synch_timing_mode_support; 220 uint8_t source_synch_feat; 221 uint16_t clk_input_capacitance; 222 uint16_t io_capacitance; 223 uint16_t input_capacitance; 224 uint8_t input_capacitance_max; 225 uint8_t driver_strength_support; 226 uint16_t t_r_interleaved; 227 uint16_t t_adl; 228 uint16_t t_r_eznand; 229 uint8_t nv_ddr2_features; 230 uint8_t nv_ddr2_warmup_cycles; 231 uint8_t res5[4]; 232 uint16_t vendor_rev; 233 uint8_t vendor_spec[88]; 234 uint16_t crc; 235 }__attribute__((packed)); 236 CTASSERT(sizeof(struct onfi_params) == 256); 237 238 struct onfi_chip_params { 239 uint32_t blocks_per_lun; 240 uint32_t pages_per_block; 241 uint32_t bytes_per_page; 242 uint32_t spare_bytes_per_page; 243 uint16_t t_bers; 244 uint16_t t_prog; 245 uint16_t t_r; 246 uint16_t t_ccs; 247 uint16_t features; 248 uint8_t address_cycles; 249 uint8_t luns; 250 }; 251 252 struct nand_ecc_data { 253 int eccsize; /* Number of data bytes per ECC step */ 254 int eccmode; 255 int eccbytes; /* Number of ECC bytes per step */ 256 257 uint16_t *eccpositions; /* Positions of ecc bytes */ 258 uint8_t ecccalculated[NAND_MAX_OOBSZ]; 259 uint8_t eccread[NAND_MAX_OOBSZ]; 260 }; 261 262 struct ecc_stat { 263 uint32_t ecc_succeded; 264 uint32_t ecc_corrected; 265 uint32_t ecc_failed; 266 }; 267 268 struct page_stat { 269 struct ecc_stat ecc_stat; 270 uint32_t page_read; 271 uint32_t page_raw_read; 272 uint32_t page_written; 273 uint32_t page_raw_written; 274 }; 275 276 struct block_stat { 277 uint32_t block_erased; 278 }; 279 280 struct chip_geom { 281 uint32_t chip_size; 282 uint32_t block_size; 283 uint32_t page_size; 284 uint32_t oob_size; 285 286 uint32_t luns; 287 uint32_t blks_per_lun; 288 uint32_t blks_per_chip; 289 uint32_t pgs_per_blk; 290 291 uint32_t pg_mask; 292 uint32_t blk_mask; 293 uint32_t lun_mask; 294 uint8_t blk_shift; 295 uint8_t lun_shift; 296 }; 297 298 struct nand_chip { 299 device_t dev; 300 struct nand_id id; 301 struct chip_geom chip_geom; 302 303 uint16_t t_prog; /* us, max page program time */ 304 uint16_t t_bers; /* us, max block erase time */ 305 uint16_t t_r; /* us, max page read time */ 306 uint16_t t_ccs; /* ns, min change column setup time */ 307 uint8_t num; 308 uint8_t flags; 309 310 struct page_stat *pg_stat; 311 struct block_stat *blk_stat; 312 struct nand_softc *nand; 313 struct nand_bbt *bbt; 314 struct nand_ops *ops; 315 struct cdev *cdev; 316 317 struct disk *ndisk; 318 struct disk *rdisk; 319 struct bio_queue_head bioq; /* bio queue */ 320 struct mtx qlock; /* bioq lock */ 321 struct taskqueue *tq; /* private task queue for i/o request */ 322 struct task iotask; /* i/o processing */ 323 324 }; 325 326 struct nand_softc { 327 uint8_t flags; 328 329 char *chip_cdev_name; 330 struct nand_ecc_data ecc; 331 }; 332 333 /* NAND ops */ 334 int nand_erase_blocks(struct nand_chip *chip, off_t offset, size_t len); 335 int nand_prog_pages(struct nand_chip *chip, uint32_t offset, uint8_t *buf, 336 uint32_t len); 337 int nand_read_pages(struct nand_chip *chip, uint32_t offset, void *buf, 338 uint32_t len); 339 int nand_read_pages_raw(struct nand_chip *chip, uint32_t offset, void *buf, 340 uint32_t len); 341 int nand_prog_pages_raw(struct nand_chip *chip, uint32_t offset, void *buf, 342 uint32_t len); 343 int nand_read_oob(struct nand_chip *chip, uint32_t page, void *buf, 344 uint32_t len); 345 int nand_prog_oob(struct nand_chip *chip, uint32_t page, void *buf, 346 uint32_t len); 347 348 int nand_select_cs(device_t dev, uint8_t cs); 349 350 int nand_read_parameter(struct nand_softc *nand, struct onfi_params *param); 351 int nand_synch_reset(struct nand_softc *nand); 352 int nand_chng_read_col(device_t dev, uint32_t col, void *buf, size_t len); 353 int nand_chng_write_col(device_t dev, uint32_t col, void *buf, size_t len); 354 int nand_get_feature(device_t dev, uint8_t feat, void* buf); 355 int nand_set_feature(device_t dev, uint8_t feat, void* buf); 356 357 358 int nand_erase_block_intlv(device_t dev, uint32_t block); 359 int nand_copyback_read(device_t dev, uint32_t page, uint32_t col, 360 void *buf, size_t len); 361 int nand_copyback_prog(device_t dev, uint32_t page, uint32_t col, 362 void *buf, size_t len); 363 int nand_copyback_prog_intlv(device_t dev, uint32_t page); 364 int nand_prog_cache(device_t dev, uint32_t page, uint32_t col, 365 void *buf, size_t len, uint8_t end); 366 int nand_prog_intlv(device_t dev, uint32_t page, uint32_t col, 367 void *buf, size_t len); 368 int nand_read_cache(device_t dev, uint32_t page, uint32_t col, 369 void *buf, size_t len, uint8_t end); 370 371 int nand_write_ecc(struct nand_softc *nand, uint32_t page, uint8_t *data); 372 int nand_read_ecc(struct nand_softc *nand, uint32_t page, uint8_t *data); 373 374 int nand_softecc_get(device_t dev, uint8_t *buf, int pagesize, uint8_t *ecc); 375 int nand_softecc_correct(device_t dev, uint8_t *buf, int pagesize, 376 uint8_t *readecc, uint8_t *calcecc); 377 378 /* Chip initialization */ 379 void nand_init(struct nand_softc *nand, device_t dev, int ecc_mode, 380 int ecc_bytes, int ecc_size, uint16_t* eccposition, char* cdev_name); 381 void nand_detach(struct nand_softc *nand); 382 struct nand_params *nand_get_params(struct nand_id *id); 383 384 void nand_onfi_set_params(struct nand_chip *chip, struct onfi_chip_params *params); 385 void nand_set_params(struct nand_chip *chip, struct nand_params *params); 386 int nand_init_stat(struct nand_chip *chip); 387 void nand_destroy_stat(struct nand_chip *chip); 388 389 /* BBT */ 390 int nand_init_bbt(struct nand_chip *chip); 391 void nand_destroy_bbt(struct nand_chip *chip); 392 int nand_update_bbt(struct nand_chip *chip); 393 int nand_mark_bad_block(struct nand_chip* chip, uint32_t block_num); 394 int nand_check_bad_block(struct nand_chip* chip, uint32_t block_num); 395 396 /* cdev creation/removal */ 397 int nand_make_dev(struct nand_chip* chip); 398 void nand_destroy_dev(struct nand_chip *chip); 399 400 int create_geom_disk(struct nand_chip* chip); 401 int create_geom_raw_disk(struct nand_chip *chip); 402 void destroy_geom_disk(struct nand_chip *chip); 403 void destroy_geom_raw_disk(struct nand_chip *chip); 404 405 int init_chip_geom(struct chip_geom* cg, uint32_t luns, uint32_t blks_per_lun, 406 uint32_t pgs_per_blk, uint32_t pg_size, uint32_t oob_size); 407 int nand_row_to_blkpg(struct chip_geom *cg, uint32_t row, uint32_t *lun, 408 uint32_t *blk, uint32_t *pg); 409 int page_to_row(struct chip_geom *cg, uint32_t page, uint32_t *row); 410 int nand_check_page_boundary(struct nand_chip *chip, uint32_t page); 411 void nand_get_chip_param(struct nand_chip *chip, struct chip_param_io *param); 412 413 #endif /* _DEV_NAND_H_ */ 414