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Searched refs:N2 (Results 1 – 25 of 33) sorted by relevance

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/NextBSD/contrib/llvm/include/llvm/ADT/
HDStringSwitch.h90 template<unsigned N0, unsigned N1, unsigned N2>
92 const char (&S2)[N2], const T& Value) { in Cases() argument
96 template<unsigned N0, unsigned N1, unsigned N2, unsigned N3>
98 const char (&S2)[N2], const char (&S3)[N3], in Cases() argument
103 template<unsigned N0, unsigned N1, unsigned N2, unsigned N3, unsigned N4>
105 const char (&S2)[N2], const char (&S3)[N3], in Cases() argument
/NextBSD/crypto/openssl/crypto/bn/asm/
HDarmv4-mont.pl248 my ($N0,$N1,$N2,$N3)=map("d$_",(4..7));
309 vmlal.u32 $A4xB,$Ni,${N2}[0]
311 vmlal.u32 $A5xB,$Ni,${N2}[1]
357 vmlal.u32 $A4xB,$Ni,${N2}[0]
359 vmlal.u32 $A5xB,$Ni,${N2}[1]
396 vmlal.u32 $A4xB,$Ni,${N2}[0]
398 vmlal.u32 $A5xB,$Ni,${N2}[1]
405 vld1.32 {$N2-$N3}, [$nptr]!
428 vmlal.u32 $A4xB,$Ni,${N2}[0]
430 vmlal.u32 $A5xB,$Ni,${N2}[1]
[all …]
HDppc64-mont.pl165 $N0="f20"; $N1="f21"; $N2="f22"; $N3="f23";
389 lfd $N2,`$FRAME+112`($sp)
397 fcfid $N2,$N2
416 stfd $N2,56($nap_d) ; save n[j+1] in double format
430 fmadd $T2a,$N2,$na,$T2a
431 fmadd $T2b,$N2,$nb,$T2b
441 fmadd $T3a,$N2,$nc,$T3a
442 fmadd $T3b,$N2,$nd,$T3b
527 lfd $N2,`$FRAME+112`($sp)
535 fcfid $N2,$N2
[all …]
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDSelectionDAG.cpp958 SDValue N2, in GetBinarySDNode() argument
967 Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2, *Flags); in GetBinarySDNode()
973 BinarySDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs, N1, N2); in GetBinarySDNode()
1511 static void commuteShuffle(SDValue &N1, SDValue &N2, SmallVectorImpl<int> &M) { in commuteShuffle() argument
1512 std::swap(N1, N2); in commuteShuffle()
1517 SDValue N2, const int *Mask) { in getVectorShuffle() argument
1518 assert(VT == N1.getValueType() && VT == N2.getValueType() && in getVectorShuffle()
1522 if (N1.getOpcode() == ISD::UNDEF && N2.getOpcode() == ISD::UNDEF) in getVectorShuffle()
1535 if (N1 == N2) { in getVectorShuffle()
1536 N2 = getUNDEF(VT); in getVectorShuffle()
[all …]
HDDAGCombiner.cpp326 SDValue SimplifySelect(SDLoc DL, SDValue N0, SDValue N1, SDValue N2);
327 SDValue SimplifySelectCC(SDLoc DL, SDValue N0, SDValue N1, SDValue N2,
709 SDValue N0, N1, N2; in isOneUseSetCC() local
710 if (isSetCCEquivalent(N, N0, N1, N2) && N.getNode()->hasOneUse()) in isOneUseSetCC()
4903 SDValue N2 = N->getOperand(2); in visitSELECT() local
4908 if (N1 == N2) in visitSELECT()
4913 return !N0C->isNullValue() ? N1 : N2; in visitSELECT()
4917 return DAG.getNode(ISD::OR, SDLoc(N), VT, N0, N2); in visitSELECT()
4933 isNullConstant(N1) && isOneConstant(N2)) { in visitSELECT()
4952 return DAG.getNode(ISD::AND, SDLoc(N), VT, NOTNode, N2); in visitSELECT()
[all …]
HDInstrEmitter.cpp531 SDValue N2 = Node->getOperand(2); in EmitSubregNode() local
532 unsigned SubIdx = cast<ConstantSDNode>(N2)->getZExtValue(); in EmitSubregNode()
HDTargetLowering.cpp2091 SDValue N2 = N->getOperand(1); in isGAPlusOffset() local
2093 ConstantSDNode *V = dyn_cast<ConstantSDNode>(N2); in isGAPlusOffset()
2098 } else if (isGAPlusOffset(N2.getNode(), GA, Offset)) { in isGAPlusOffset()
HDLegalizeDAG.cpp103 SDValue N1, SDValue N2,
209 SDValue N1, SDValue N2, in ShuffleWithNarrowerEltType() argument
218 return DAG.getVectorShuffle(NVT, dl, N1, N2, &Mask[0]); in ShuffleWithNarrowerEltType()
232 return DAG.getVectorShuffle(NVT, dl, N1, N2, &NewMask[0]); in ShuffleWithNarrowerEltType()
/NextBSD/share/examples/netgraph/
HDvirtual.lan225 M4=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
227 M5=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
229 M6=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
HDvirtual.chain232 M4=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
234 M5=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
236 M6=`od -An -N2 -i /dev/random | sed -e 's/ //g' | \
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDSelectionDAG.h575 SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
577 SDValue getVectorShuffle(EVT VT, SDLoc dl, SDValue N1, SDValue N2,
581 return getVectorShuffle(VT, dl, N1, N2, MaskElts.data());
682 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
684 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
686 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
688 SDValue getNode(unsigned Opcode, SDLoc DL, EVT VT, SDValue N1, SDValue N2,
696 SDValue N2);
698 SDValue N2, SDValue N3);
700 SDValue N2, SDValue N3, SDValue N4);
[all …]
HDSelectionDAGNodes.h1376 SDValue N2, const int *M)
1378 InitOperands(Ops, N1, N2);
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonCommonGEP.cpp76 bool operator() (const GepNode* N1, const GepNode *N2) const { in operator ()()
77 const_iterator F1 = find(N1), F2 = find(N2); in operator ()()
477 NodePair node_pair(GepNode *N1, GepNode *N2) { in node_pair() argument
478 uintptr_t P1 = uintptr_t(N1), P2 = uintptr_t(N2); in node_pair()
480 return std::make_pair(N1, N2); in node_pair()
481 return std::make_pair(N2, N1); in node_pair()
492 bool node_eq(GepNode *N1, GepNode *N2, NodePairSet &Eq, NodePairSet &Ne) { in node_eq() argument
495 if (node_hash(N1) != node_hash(N2)) in node_eq()
498 NodePair NP = node_pair(N1, N2); in node_eq()
507 bool Root2 = N2->Flags & GepNode::Root; in node_eq()
[all …]
/NextBSD/contrib/gcc/config/arm/
HDfpa.md107 suf%?s\\t%0, %1, #%N2"
119 suf%?d\\t%0, %1, #%N2"
132 suf%?d\\t%0, %1, #%N2"
718 mnf%D3s\\t%0, #%N2
722 mvf%d3s\\t%0, %1\;mnf%D3s\\t%0, #%N2
724 mnf%d3s\\t%0, #%N1\;mnf%D3s\\t%0, #%N2"
740 mnf%D3d\\t%0, #%N2
744 mvf%d3d\\t%0, %1\;mnf%D3d\\t%0, #%N2
746 mnf%d3d\\t%0, #%N1\;mnf%D3d\\t%0, #%N2"
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp1672 SDValue N2 = N->getOperand(2); in PerformDAGCombine() local
1679 return DAG.getNode(XCoreISD::LADD, dl, DAG.getVTList(VT, VT), N1, N0, N2); in PerformDAGCombine()
1684 SDValue Result = DAG.getNode(ISD::AND, dl, VT, N2, in PerformDAGCombine()
1696 DAG.computeKnownBits(N2, KnownZero, KnownOne); in PerformDAGCombine()
1699 SDValue Result = DAG.getNode(ISD::ADD, dl, VT, N0, N2); in PerformDAGCombine()
1709 SDValue N2 = N->getOperand(2); in PerformDAGCombine() local
1719 DAG.computeKnownBits(N2, KnownZero, KnownOne); in PerformDAGCombine()
1721 SDValue Borrow = N2; in PerformDAGCombine()
1723 DAG.getConstant(0, dl, VT), N2); in PerformDAGCombine()
1735 DAG.computeKnownBits(N2, KnownZero, KnownOne); in PerformDAGCombine()
[all …]
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430ISelDAGToDAG.cpp116 SDNode *SelectIndexedBinOp(SDNode *Op, SDValue N1, SDValue N2,
352 SDValue N1, SDValue N2, in SelectIndexedBinOp() argument
365 SDValue Ops0[] = { N2, LD->getBasePtr(), LD->getChain() }; in SelectIndexedBinOp()
/NextBSD/contrib/llvm/lib/Target/NVPTX/
HDNVPTXISelDAGToDAG.cpp2046 SDValue N2 = N->getOperand(2); in SelectStore() local
2052 if (SelectDirectAddr(N2, Addr)) { in SelectStore()
2080 } else if (TM.is64Bit() ? SelectADDRsi64(N2.getNode(), N2, Base, Offset) in SelectStore()
2081 : SelectADDRsi(N2.getNode(), N2, Base, Offset)) { in SelectStore()
2109 } else if (TM.is64Bit() ? SelectADDRri64(N2.getNode(), N2, Base, Offset) in SelectStore()
2110 : SelectADDRri(N2.getNode(), N2, Base, Offset)) { in SelectStore()
2213 getI32Imm(toType, dl), getI32Imm(toTypeWidth, dl), N2, in SelectStore()
2266 SDValue N2; in SelectStoreVector() local
2274 N2 = N->getOperand(3); in SelectStoreVector()
2282 N2 = N->getOperand(5); in SelectStoreVector()
[all …]
/NextBSD/contrib/pam_modules/pam_passwdqc/
HDREADME21 min=N0,N1,N2,N3,N4 [min=disabled,24,12,8,7]
37 N2 is used for passphrases. A passphrase must consist of sufficient
/NextBSD/contrib/ntp/ntpd/
HDrefclock_wwv.c439 #define N2 (N15 / 2) /* space (-1) */ macro
442 {N2, N2, 0, 0}, /* 0 */
443 {P2, N2, 0, 0}, /* 1 */
444 {N2, P2, 0, 0}, /* 2 */
/NextBSD/contrib/llvm/lib/Analysis/
HDDependenceAnalysis.cpp2004 const SCEV *N2 = collectUpperBound(Loop2, A1->getType()); in symbolicRDIVtest() local
2006 DEBUG(if (N2) dbgs() << "\t N2 = " << *N2 << "\n"); in symbolicRDIVtest()
2023 if (N2) { in symbolicRDIVtest()
2025 const SCEV *A2N2 = SE->getMulExpr(A2, N2); in symbolicRDIVtest()
2035 if (N1 && N2) { in symbolicRDIVtest()
2038 const SCEV *A2N2 = SE->getMulExpr(A2, N2); in symbolicRDIVtest()
2056 if (N1 && N2) { in symbolicRDIVtest()
2059 const SCEV *A2N2 = SE->getMulExpr(A2, N2); in symbolicRDIVtest()
2084 if (N2) { in symbolicRDIVtest()
2086 const SCEV *A2N2 = SE->getMulExpr(A2, N2); in symbolicRDIVtest()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp4410 SDValue N2 = DAG.getNode(ARMISD::VREV16, DL, VT8Bit, N1); in getCTPOP16BitCounts() local
4411 SDValue N3 = DAG.getNode(ISD::ADD, DL, VT8Bit, N1, N2); in getCTPOP16BitCounts()
4470 SDValue N2 = DAG.getNode(ARMISD::VUZP, DL, VT16Bit, N1, N1); in lowerCTPOP32BitElements() local
4473 SDValue Extended = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::v4i32, N2); in lowerCTPOP32BitElements()
4477 SDValue Extracted = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, MVT::v4i16, N2, in lowerCTPOP32BitElements()
6268 SDValue N2; in LowerSDIV_v4i16() local
6280 N2 = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::v4f32, in LowerSDIV_v4i16()
6285 N1, N2); in LowerSDIV_v4i16()
6286 N2 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N1, N2); in LowerSDIV_v4i16()
6291 N0 = DAG.getNode(ISD::FMUL, dl, MVT::v4f32, N0, N2); in LowerSDIV_v4i16()
[all …]
HDARMScheduleA8.td821 // Result written in N2, but that is relative to the last cycle of multicycle,
855 // Result written in N2, but that is relative to the last cycle of multicycle,
861 // Result written in N2, but that is relative to the last cycle of multicycle,
HDARMISelDAGToDAG.cpp2650 SDValue N2 = N0.getOperand(1); in Select() local
2651 ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2); in Select()
2764 SDValue N2 = N->getOperand(2); in Select() local
2768 assert(N2.getOpcode() == ISD::Constant); in Select()
2772 cast<ConstantSDNode>(N2)->getZExtValue()), dl, in Select()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDAMDGPUISelDAGToDAG.cpp983 SDValue N2 = N0.getOperand(0); in SelectMUBUF() local
986 Ptr = N2; in SelectMUBUF()
/NextBSD/contrib/llvm/utils/TableGen/
HDCodeGenDAGPatterns.cpp2302 TreePatternNode *N1 = Nodes[i], *N2 = Nodes[i+1]; in InferAllTypes() local
2303 assert(N1->getNumTypes() == 1 && N2->getNumTypes() == 1 && in InferAllTypes()
2306 MadeChange |= N1->UpdateNodeType(0, N2->getExtType(0), *this); in InferAllTypes()
2307 MadeChange |= N2->UpdateNodeType(0, N1->getExtType(0), *this); in InferAllTypes()

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