Searched refs:LogicOp (Results 1 – 3 of 3) sorted by relevance
| /NextBSD/contrib/llvm/lib/Target/SystemZ/ |
| HD | SystemZInstrInfo.cpp | 636 struct LogicOp { struct
637 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {} in LogicOp() argument
638 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize) in LogicOp() argument
647 static LogicOp interpretAndImmediate(unsigned Opcode) { in interpretAndImmediate()
649 case SystemZ::NILMux: return LogicOp(32, 0, 16); in interpretAndImmediate()
650 case SystemZ::NIHMux: return LogicOp(32, 16, 16); in interpretAndImmediate()
651 case SystemZ::NILL64: return LogicOp(64, 0, 16); in interpretAndImmediate()
652 case SystemZ::NILH64: return LogicOp(64, 16, 16); in interpretAndImmediate()
653 case SystemZ::NIHL64: return LogicOp(64, 32, 16); in interpretAndImmediate()
654 case SystemZ::NIHH64: return LogicOp(64, 48, 16); in interpretAndImmediate()
[all …]
|
| /NextBSD/contrib/llvm/lib/CodeGen/ |
| HD | CodeGenPrepare.cpp | 4669 BinaryOperator *LogicOp; in splitBranchCondition() local
4671 if (!match(BB.getTerminator(), m_Br(m_OneUse(m_BinOp(LogicOp)), TBB, FBB))) in splitBranchCondition()
4676 if (match(LogicOp, m_And(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
4679 else if (match(LogicOp, m_Or(m_OneUse(m_Value(Cond1)), in splitBranchCondition()
4702 LogicOp->eraseFromParent(); in splitBranchCondition()
|
| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86ISelLowering.cpp | 12684 unsigned LogicOp = in LowerFABSorFNEG() local
12689 return DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
12694 SDValue LogicNode = DAG.getNode(LogicOp, dl, LogicVT, Operand, Mask); in LowerFABSorFNEG()
|