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Searched refs:Lo (Results 1 – 25 of 83) sorted by relevance

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/NextBSD/crypto/heimdal/lib/wind/
HDUnicodeData.txt444 01BB;LATIN LETTER TWO WITH STROKE;Lo;0;L;;;;;N;LATIN LETTER TWO BAR;;;;
449 01C0;LATIN LETTER DENTAL CLICK;Lo;0;L;;;;;N;LATIN LETTER PIPE;;;;
450 01C1;LATIN LETTER LATERAL CLICK;Lo;0;L;;;;;N;LATIN LETTER DOUBLE PIPE;;;;
451 01C2;LATIN LETTER ALVEOLAR CLICK;Lo;0;L;;;;;N;LATIN LETTER PIPE DOUBLE BAR;;;;
452 01C3;LATIN LETTER RETROFLEX CLICK;Lo;0;L;;;;;N;LATIN LETTER EXCLAMATION MARK;;;;
1369 05D0;HEBREW LETTER ALEF;Lo;0;R;;;;;N;;;;;
1370 05D1;HEBREW LETTER BET;Lo;0;R;;;;;N;;;;;
1371 05D2;HEBREW LETTER GIMEL;Lo;0;R;;;;;N;;;;;
1372 05D3;HEBREW LETTER DALET;Lo;0;R;;;;;N;;;;;
1373 05D4;HEBREW LETTER HE;Lo;0;R;;;;;N;;;;;
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HDDerivedNormalizationProps.txt594 0958..095F ; Full_Composition_Exclusion # Lo [8] DEVANAGARI LETTER QA..DEVANAGARI LETTER YYA
595 09DC..09DD ; Full_Composition_Exclusion # Lo [2] BENGALI LETTER RRA..BENGALI LETTER RHA
596 09DF ; Full_Composition_Exclusion # Lo BENGALI LETTER YYA
597 0A33 ; Full_Composition_Exclusion # Lo GURMUKHI LETTER LLA
598 0A36 ; Full_Composition_Exclusion # Lo GURMUKHI LETTER SHA
599 0A59..0A5B ; Full_Composition_Exclusion # Lo [3] GURMUKHI LETTER KHHA..GURMUKHI LETTER ZA
600 0A5E ; Full_Composition_Exclusion # Lo GURMUKHI LETTER FA
601 0B5C..0B5D ; Full_Composition_Exclusion # Lo [2] ORIYA LETTER RRA..ORIYA LETTER RHA
602 0F43 ; Full_Composition_Exclusion # Lo TIBETAN LETTER GHA
603 0F4D ; Full_Composition_Exclusion # Lo TIBETAN LETTER DDHA
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/NextBSD/sys/contrib/dev/acpica/components/utilities/
HDutmath.c65 UINT32 Lo; member
126 ACPI_DIV_64_BY_32 (Remainder32, DividendOvl.Part.Lo, Divisor, in AcpiUtShortDivide()
127 Quotient.Part.Lo, Remainder32); in AcpiUtShortDivide()
202 ACPI_DIV_64_BY_32 (0, Dividend.Part.Hi, Divisor.Part.Lo, in AcpiUtDivide()
204 ACPI_DIV_64_BY_32 (Partial1, Dividend.Part.Lo, Divisor.Part.Lo, in AcpiUtDivide()
205 Quotient.Part.Lo, Remainder.Part.Lo); in AcpiUtDivide()
223 NormalizedDivisor.Part.Lo); in AcpiUtDivide()
225 NormalizedDividend.Part.Lo); in AcpiUtDivide()
232 NormalizedDividend.Part.Lo, in AcpiUtDivide()
233 NormalizedDivisor.Part.Lo, in AcpiUtDivide()
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/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDLegalizeTypes.h168 SDValue JoinIntegers(SDValue Lo, SDValue Hi);
177 void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
179 SDValue &Lo, SDValue &Hi);
310 void GetExpandedInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
311 void SetExpandedInteger(SDValue Op, SDValue Lo, SDValue Hi);
316 SDValue &Lo, SDValue &Hi);
317 void ExpandIntRes_ANY_EXTEND (SDNode *N, SDValue &Lo, SDValue &Hi);
318 void ExpandIntRes_AssertSext (SDNode *N, SDValue &Lo, SDValue &Hi);
319 void ExpandIntRes_AssertZext (SDNode *N, SDValue &Lo, SDValue &Hi);
320 void ExpandIntRes_Constant (SDNode *N, SDValue &Lo, SDValue &Hi);
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HDLegalizeTypesGeneric.cpp36 SDValue &Lo, SDValue &Hi) { in ExpandRes_MERGE_VALUES() argument
38 GetExpandedOp(Op, Lo, Hi); in ExpandRes_MERGE_VALUES()
41 void DAGTypeLegalizer::ExpandRes_BITCAST(SDNode *N, SDValue &Lo, SDValue &Hi) { in ExpandRes_BITCAST() argument
58 SplitInteger(GetSoftenedFloat(InOp), Lo, Hi); in ExpandRes_BITCAST()
59 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
66 GetExpandedOp(InOp, Lo, Hi); in ExpandRes_BITCAST()
69 std::swap(Lo, Hi); in ExpandRes_BITCAST()
70 Lo = DAG.getNode(ISD::BITCAST, dl, NOutVT, Lo); in ExpandRes_BITCAST()
75 GetSplitVector(InOp, Lo, Hi); in ExpandRes_BITCAST()
77 std::swap(Lo, Hi); in ExpandRes_BITCAST()
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HDLegalizeIntegerTypes.cpp280 SDValue Lo, Hi; in PromoteIntRes_BITCAST() local
281 GetSplitVector(N->getOperand(0), Lo, Hi); in PromoteIntRes_BITCAST()
282 Lo = BitConvertToInteger(Lo); in PromoteIntRes_BITCAST()
286 std::swap(Lo, Hi); in PromoteIntRes_BITCAST()
291 JoinIntegers(Lo, Hi)); in PromoteIntRes_BITCAST()
1002 SDValue Lo = ZExtPromotedInteger(N->getOperand(0)); in PromoteIntOp_BUILD_PAIR() local
1004 assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?"); in PromoteIntOp_BUILD_PAIR()
1010 return DAG.getNode(ISD::OR, dl, N->getValueType(0), Lo, Hi); in PromoteIntOp_BUILD_PAIR()
1233 SDValue Lo, Hi; in ExpandIntegerResult() local
1234 Lo = Hi = SDValue(); in ExpandIntegerResult()
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HDLegalizeFloatTypes.cpp866 SDValue Lo, Hi; in ExpandFloatResult() local
867 Lo = Hi = SDValue(); in ExpandFloatResult()
881 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; in ExpandFloatResult()
882 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; in ExpandFloatResult()
883 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in ExpandFloatResult()
885 case ISD::MERGE_VALUES: ExpandRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in ExpandFloatResult()
886 case ISD::BITCAST: ExpandRes_BITCAST(N, Lo, Hi); break; in ExpandFloatResult()
887 case ISD::BUILD_PAIR: ExpandRes_BUILD_PAIR(N, Lo, Hi); break; in ExpandFloatResult()
888 case ISD::EXTRACT_ELEMENT: ExpandRes_EXTRACT_ELEMENT(N, Lo, Hi); break; in ExpandFloatResult()
889 case ISD::EXTRACT_VECTOR_ELT: ExpandRes_EXTRACT_VECTOR_ELT(N, Lo, Hi); break; in ExpandFloatResult()
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HDLegalizeVectorTypes.cpp569 SDValue Lo, Hi; in SplitVectorResult() local
585 case ISD::MERGE_VALUES: SplitRes_MERGE_VALUES(N, ResNo, Lo, Hi); break; in SplitVectorResult()
587 case ISD::SELECT: SplitRes_SELECT(N, Lo, Hi); break; in SplitVectorResult()
588 case ISD::SELECT_CC: SplitRes_SELECT_CC(N, Lo, Hi); break; in SplitVectorResult()
589 case ISD::UNDEF: SplitRes_UNDEF(N, Lo, Hi); break; in SplitVectorResult()
590 case ISD::BITCAST: SplitVecRes_BITCAST(N, Lo, Hi); break; in SplitVectorResult()
591 case ISD::BUILD_VECTOR: SplitVecRes_BUILD_VECTOR(N, Lo, Hi); break; in SplitVectorResult()
592 case ISD::CONCAT_VECTORS: SplitVecRes_CONCAT_VECTORS(N, Lo, Hi); break; in SplitVectorResult()
593 case ISD::EXTRACT_SUBVECTOR: SplitVecRes_EXTRACT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
594 case ISD::INSERT_SUBVECTOR: SplitVecRes_INSERT_SUBVECTOR(N, Lo, Hi); break; in SplitVectorResult()
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HDLegalizeTypes.cpp789 void DAGTypeLegalizer::GetExpandedInteger(SDValue Op, SDValue &Lo, in GetExpandedInteger() argument
795 Lo = Entry.first; in GetExpandedInteger()
799 void DAGTypeLegalizer::SetExpandedInteger(SDValue Op, SDValue Lo, in SetExpandedInteger() argument
801 assert(Lo.getValueType() == in SetExpandedInteger()
803 Hi.getValueType() == Lo.getValueType() && in SetExpandedInteger()
806 AnalyzeNewValue(Lo); in SetExpandedInteger()
812 Entry.first = Lo; in SetExpandedInteger()
816 void DAGTypeLegalizer::GetExpandedFloat(SDValue Op, SDValue &Lo, in GetExpandedFloat() argument
822 Lo = Entry.first; in GetExpandedFloat()
826 void DAGTypeLegalizer::SetExpandedFloat(SDValue Op, SDValue Lo, in SetExpandedFloat() argument
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HDLegalizeVectorOps.cpp563 SDValue Lo, Hi, ShAmt; in ExpandLoad() local
568 Lo = DAG.getNode(ISD::SRL, dl, WideVT, LoadVals[WideIdx], ShAmt); in ExpandLoad()
569 Lo = DAG.getNode(ISD::AND, dl, WideVT, Lo, SrcEltBitMask); in ExpandLoad()
586 Lo = DAG.getNode(ISD::OR, dl, WideVT, Lo, Hi); in ExpandLoad()
591 Lo = DAG.getAnyExtOrTrunc(Lo, dl, DstEltVT); in ExpandLoad()
594 Lo = DAG.getZExtOrTrunc(Lo, dl, DstEltVT); in ExpandLoad()
600 Lo = DAG.getNode(ISD::SHL, dl, WideVT, Lo, ShAmt); in ExpandLoad()
601 Lo = DAG.getNode(ISD::SRA, dl, WideVT, Lo, ShAmt); in ExpandLoad()
602 Lo = DAG.getSExtOrTrunc(Lo, dl, DstEltVT); in ExpandLoad()
605 Vals.push_back(Lo); in ExpandLoad()
HDLegalizeDAG.cpp393 SDValue Lo = Val; in ExpandUnalignedStore() local
399 DAG.getDataLayout().isLittleEndian() ? Lo : Hi, in ExpandUnalignedStore()
408 Chain, dl, DAG.getDataLayout().isLittleEndian() ? Hi : Lo, Ptr, in ExpandUnalignedStore()
530 SDValue Lo, Hi; in ExpandUnalignedLoad() local
532 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, LD->getPointerInfo(), in ExpandUnalignedLoad()
550 Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, VT, Chain, Ptr, in ExpandUnalignedLoad()
562 Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo); in ExpandUnalignedLoad()
564 SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1), in ExpandUnalignedLoad()
685 SDValue Lo = DAG.getConstant(IntVal.trunc(32), dl, MVT::i32); in OptimizeFloatStore() local
688 std::swap(Lo, Hi); in OptimizeFloatStore()
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/NextBSD/contrib/llvm/lib/IR/
HDMDBuilder.cpp66 MDNode *MDBuilder::createRange(const APInt &Lo, const APInt &Hi) { in createRange() argument
67 assert(Lo.getBitWidth() == Hi.getBitWidth() && "Mismatched bitwidths!"); in createRange()
69 Type *Ty = IntegerType::get(Context, Lo.getBitWidth()); in createRange()
70 return createRange(ConstantInt::get(Ty, Lo), ConstantInt::get(Ty, Hi)); in createRange()
73 MDNode *MDBuilder::createRange(Constant *Lo, Constant *Hi) { in createRange() argument
75 if (Hi == Lo) in createRange()
79 Metadata *Range[2] = {createConstant(Lo), createConstant(Hi)}; in createRange()
/NextBSD/contrib/llvm/include/llvm/Support/
HDSwapByteOrder.h35 uint16_t Lo = value >> 8; in SwapByteOrder_16()
36 return Hi | Lo; in SwapByteOrder_16()
65 uint32_t Lo = SwapByteOrder_32(uint32_t(value >> 32)); in SwapByteOrder_64()
66 return (Hi << 32) | Lo; in SwapByteOrder_64()
HDGCOV.h193 uint32_t Lo, Hi; in readInt64() local
194 if (!readInt(Lo) || !readInt(Hi)) in readInt64()
196 Val = ((uint64_t)Hi << 32) | Lo; in readInt64()
/NextBSD/contrib/llvm/lib/Target/Sparc/
HDSparcISelDAGToDAG.cpp104 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
109 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
131 if (Addr.getOperand(0).getOpcode() == SPISD::Lo || in SelectADDRrr()
132 Addr.getOperand(1).getOpcode() == SPISD::Lo) in SelectADDRrr()
HDSparcISelLowering.cpp818 SDValue Lo = DAG.getLoad(MVT::i32, dl, Store, StackPtr, in LowerCall_32() local
826 RegsToPass.push_back(std::make_pair(NextVA.getLocReg(), Lo)); in LowerCall_32()
833 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, in LowerCall_32()
849 MemOpChains.push_back(DAG.getStore(Chain, dl, Lo, PtrOff, in LowerCall_32()
1693 case SPISD::Lo: return "SPISD::Lo"; in getTargetNodeName()
1802 SDValue Lo = DAG.getNode(SPISD::Lo, DL, VT, withTargetFlags(Op, LoTF, DAG)); in makeHiLoPair() local
1803 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeHiLoPair()
1841 L44 = DAG.getNode(SPISD::Lo, DL, VT, L44); in makeAddress()
1849 SDValue Lo = makeHiLoPair(Op, SparcMCExpr::VK_Sparc_HI, in makeAddress() local
1851 return DAG.getNode(ISD::ADD, DL, VT, Hi, Lo); in makeAddress()
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/NextBSD/contrib/llvm/tools/clang/lib/CodeGen/
HDTargetInfo.cpp1452 void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const;
1478 void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi,
1767 void X86_64ABIInfo::postMerge(unsigned AggregateSize, Class &Lo, in postMerge() argument
1791 Lo = Memory; in postMerge()
1792 if (Hi == X87Up && Lo != X87 && honorsRevision0_98()) in postMerge()
1793 Lo = Memory; in postMerge()
1794 if (AggregateSize > 128 && (Lo != SSE || Hi != SSEUp)) in postMerge()
1795 Lo = Memory; in postMerge()
1796 if (Hi == SSEUp && Lo != SSE) in postMerge()
1841 Class &Lo, Class &Hi, bool isNamedArg) const { in classify() argument
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/NextBSD/contrib/llvm/lib/Target/Mips/
HDMips16ISelDAGToDAG.cpp49 SDNode *Lo = nullptr, *Hi = nullptr; in selectMULT() local
56 Lo = CurDAG->getMachineNode(Opcode, DL, Ty, MVT::Glue, InFlag); in selectMULT()
57 InFlag = SDValue(Lo, 1); in selectMULT()
63 return std::make_pair(Lo, Hi); in selectMULT()
217 if (Addr.getOperand(1).getOpcode() == MipsISD::Lo || in selectAddr16()
HDMipsISelLowering.h46 Lo, enumerator
297 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, Ty, in getAddrLocal() local
299 return DAG.getNode(ISD::ADD, DL, Ty, Load, Lo); in getAddrLocal()
341 SDValue Lo = getTargetNode(N, Ty, DAG, MipsII::MO_ABS_LO); in getAddrNonPIC() local
344 DAG.getNode(MipsISD::Lo, DL, Ty, Lo)); in getAddrNonPIC()
HDMipsISelLowering.cpp116 case MipsISD::Lo: return "MipsISD::Lo"; in getTargetNodeName()
799 SDValue Lo = Add.getOperand(1); in performADDCombine() local
801 if ((Lo.getOpcode() != MipsISD::Lo) || in performADDCombine()
802 (Lo.getOperand(0).getOpcode() != ISD::TargetJumpTable)) in performADDCombine()
810 return DAG.getNode(ISD::ADD, DL, ValTy, Add1, Lo); in performADDCombine()
1762 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); in lowerGlobalTLSAddress() local
1764 return DAG.getNode(ISD::ADD, DL, PtrVT, Add, Lo); in lowerGlobalTLSAddress()
1785 SDValue Lo = DAG.getNode(MipsISD::Lo, DL, PtrVT, TGALo); in lowerGlobalTLSAddress() local
1786 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Hi, Lo); in lowerGlobalTLSAddress()
2084 SDValue Lo = Op.getOperand(0), Hi = Op.getOperand(1); in lowerShiftLeftParts() local
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/NextBSD/contrib/llvm/lib/MC/
HDMCObjectStreamer.cpp58 const MCSymbol *Lo, in emitAbsoluteSymbolDiff() argument
61 if (!Hi->getFragment() || Hi->getFragment() != Lo->getFragment()) { in emitAbsoluteSymbolDiff()
62 MCStreamer::emitAbsoluteSymbolDiff(Hi, Lo, Size); in emitAbsoluteSymbolDiff()
66 assert(Hi->getOffset() >= Lo->getOffset() && in emitAbsoluteSymbolDiff()
68 EmitIntValue(Hi->getOffset() - Lo->getOffset(), Size); in emitAbsoluteSymbolDiff()
/NextBSD/contrib/llvm/include/llvm/IR/
HDMDBuilder.h71 MDNode *createRange(const APInt &Lo, const APInt &Hi);
74 MDNode *createRange(Constant *Lo, Constant *Hi);
/NextBSD/contrib/llvm/lib/Target/XCore/
HDXCoreISelLowering.cpp585 SDValue Lo(Hi.getNode(), 1); in LowerSMUL_LOHI() local
586 SDValue Ops[] = { Lo, Hi }; in LowerSMUL_LOHI()
602 SDValue Lo(Hi.getNode(), 1); in LowerUMUL_LOHI() local
603 SDValue Ops[] = { Lo, Hi }; in LowerUMUL_LOHI()
699 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul() local
700 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
707 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul() local
708 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
718 SDValue Lo(Hi.getNode(), 1); in TryExpandADDWithMul() local
723 return DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, Lo, Hi); in TryExpandADDWithMul()
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/NextBSD/contrib/llvm/lib/Target/Mips/MCTargetDesc/
HDMipsELFObjectWriter.cpp284 static void setMatch(MipsRelocationEntry &Hi, MipsRelocationEntry &Lo) { in setMatch() argument
285 Lo.HasMatchingHi = true; in setMatch()
286 Hi.SortOffset = Lo.R.Offset - 1; in setMatch()
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDR600ISelLowering.cpp979 SDValue Lo = Op.getOperand(0); in LowerSHLParts() local
995 SDValue Overflow = DAG.getNode(ISD::SRL, DL, VT, Lo, CompShift); in LowerSHLParts()
1000 SDValue LoSmall = DAG.getNode(ISD::SHL, DL, VT, Lo, Shift); in LowerSHLParts()
1002 SDValue HiBig = DAG.getNode(ISD::SHL, DL, VT, Lo, BigShift); in LowerSHLParts()
1006 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSHLParts()
1008 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSHLParts()
1015 SDValue Lo = Op.getOperand(0); in LowerSRXParts() local
1037 SDValue LoSmall = DAG.getNode(ISD::SRL, DL, VT, Lo, Shift); in LowerSRXParts()
1044 Lo = DAG.getSelectCC(DL, Shift, Width, LoSmall, LoBig, ISD::SETULT); in LowerSRXParts()
1046 return DAG.getNode(ISD::MERGE_VALUES, DL, DAG.getVTList(VT,VT), Lo, Hi); in LowerSRXParts()
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