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Searched refs:Lane (Results 1 – 25 of 42) sorted by relevance

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/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSIMachineFunctionInfo.h38 int Lane; member
39 SpilledReg(unsigned R, int L) : VGPR (R), Lane (L) { } in SpilledReg()
40 SpilledReg() : VGPR(0), Lane(-1) { } in SpilledReg()
41 bool hasLane() { return Lane != -1;} in hasLane()
HDSIMachineFunctionInfo.cpp49 unsigned Lane = (Offset / 4) % 64; in getSpilledReg() local
67 Spill.Lane = Lane; in getSpilledReg()
HDSIRegisterInfo.cpp229 .addImm(Spill.Lane); in eliminateFrameIndex()
259 .addImm(Spill.Lane) in eliminateFrameIndex()
HDSIISelLowering.cpp1998 unsigned Lane = 0; in adjustWritemask() local
2015 Lane = SubIdx2Lane(I->getConstantOperandVal(1)); in adjustWritemask()
2019 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) { in adjustWritemask()
2026 if (Users[Lane]) in adjustWritemask()
2029 Users[Lane] = *I; in adjustWritemask()
2049 SDLoc(), Users[Lane]->getValueType(0), in adjustWritemask()
2051 DAG.ReplaceAllUsesWith(Users[Lane], Copy); in adjustWritemask()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDA15SDOptimizer.cpp72 unsigned Reg, unsigned Lane,
78 unsigned DReg, unsigned Lane,
93 DebugLoc DL, unsigned DReg, unsigned Lane,
433 unsigned Reg, unsigned Lane, bool QPR) { in createDupLane() argument
442 .addImm(Lane)); in createDupLane()
452 unsigned DReg, unsigned Lane, in createExtractSubreg() argument
459 .addReg(DReg, 0, Lane); in createExtractSubreg()
503 DebugLoc DL, unsigned DReg, unsigned Lane, in createInsertSubreg() argument
512 .addImm(Lane); in createInsertSubreg()
569 unsigned Lane; in optimizeAllLanesPattern() local
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HDARMBaseInstrInfo.cpp4139 unsigned SReg, unsigned &Lane) { in getCorrespondingDRegAndLane() argument
4141 Lane = 0; in getCorrespondingDRegAndLane()
4146 Lane = 1; in getCorrespondingDRegAndLane()
4170 unsigned DReg, unsigned Lane, in getImplicitSPRUseForDPRUse() argument
4181 (Lane & 1) ? ARM::ssub_0 : ARM::ssub_1); in getImplicitSPRUseForDPRUse()
4199 unsigned Lane; in setExecutionDomain() local
4241 DReg = getCorrespondingDRegAndLane(TRI, SrcReg, Lane); in setExecutionDomain()
4249 .addImm(Lane)); in setExecutionDomain()
4264 DReg = getCorrespondingDRegAndLane(TRI, DstReg, Lane); in setExecutionDomain()
4267 if (!getImplicitSPRUseForDPRUse(TRI, MI, DReg, Lane, ImplicitSReg)) in setExecutionDomain()
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/NextBSD/sys/gnu/dts/arm/
HDarmada-xp-db.dts116 /* Port 0, Lane 0 */
120 /* Port 0, Lane 1 */
124 /* Port 0, Lane 2 */
128 /* Port 0, Lane 3 */
132 /* Port 2, Lane 0 */
136 /* Port 3, Lane 0 */
HDarmada-385-db-ap.dts163 /* Port 0, Lane 0 */
168 /* Port 1, Lane 0 */
173 /* Port 2, Lane 0 */
HDarmada-xp-axpwifiap.dts79 /* Port 0, Lane 0 */
85 /* Port 0, Lane 1 */
91 /* Port 0, Lane 3 */
HDarmada-xp-gp.dts135 /* Port 0, Lane 0 */
139 /* Port 2, Lane 0 */
143 /* Port 3, Lane 0 */
HDarmada-388-db.dts177 /* Port 0, Lane 0 */
181 /* Port 1, Lane 0 */
HDarmada-xp-netgear-rn2120.dts73 /* Port 0, Lane 0 */
79 /* Port 0, Lane 1 */
85 /* Port 1, Lane 0 */
HDarmada-370-mirabox.dts71 /* Port 0, Lane 0 */
77 /* Port 1, Lane 0 */
HDarmada-375-db.dts195 /* Port 0, Lane 0 */
199 /* Port 1, Lane 0 */
HDarmada-388-gp.dts236 /* Port 0, Lane 0 */
245 /* Port 1, Lane 0 */
249 /* Port 2, Lane 0 */
HDarmada-370-db.dts171 /* Port 0, Lane 0 */
176 /* Port 1, Lane 0 */
HDarmada-370-rd.dts84 /* Port 0, Lane 0 */
90 /* Port 1, Lane 0 */
HDarmada-370-netgear-rn104.dts73 /* Port 0, Lane 0 */
79 /* Port 1, Lane 0 */
HDarmada-370-netgear-rn102.dts73 /* Port 0, Lane 0 */
79 /* Port 1, Lane 0 */
HDarmada-xp-lenovo-ix4-300d.dts75 /* Port 0, Lane 0 */
81 /* Port 1, Lane 0 */
HDarmada-xp-synology-ds414.dts91 /* Port 0, Lane 0 */
100 /* Port 1, Lane 0 */
HDarmada-388-rd.dts127 /* Port 0, Lane 0 */
HDarmada-xp-matrix.dts104 /* Port 0, Lane 0 */
Dkirkwood-netgear_readynas_nv+_v2.dts37 /* Port 0, Lane 0 */
/NextBSD/contrib/llvm/lib/Transforms/Vectorize/
HDSLPVectorizer.cpp509 Scalar(S), User(U), Lane(L){}; in ExternalUser()
515 int Lane; member
914 for (int Lane = 0, LE = Entry->Scalars.size(); Lane != LE; ++Lane) { in buildTree() local
915 Value *Scalar = Entry->Scalars[Lane]; in buildTree()
951 Lane << " from " << *Scalar << ".\n"); in buildTree()
952 ExternalUses.push_back(ExternalUser(Scalar, U, Lane)); in buildTree()
1756 I->Lane); in getTreeCost()
2054 for (unsigned Lane = 0, LE = VL.size(); Lane != LE; ++Lane) { in Gather() local
2056 if (E->Scalars[Lane] == VL[i]) { in Gather()
2057 FoundLane = Lane; in Gather()
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