| /NextBSD/contrib/llvm/utils/TableGen/ |
| HD | CodeGenSchedule.h | 50 bool IsRead; member
59 : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false), in CodeGenSchedRW()
64 IsRead = Def->isSubClassOf("SchedRead"); in CodeGenSchedRW()
77 : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), in CodeGenSchedRW()
321 const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const { in getSchedRW() argument
322 return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx); in getSchedRW()
325 bool IsRead = Def->isSubClassOf("SchedRead"); in getSchedRW() local
326 unsigned Idx = getSchedRWIdx(Def, IsRead); in getSchedRW()
328 IsRead ? getSchedRead(Idx) : getSchedWrite(Idx)); in getSchedRW()
334 unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const;
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| HD | CodeGenSchedule.cpp | 329 std::string CodeGenSchedModels::genRWName(const IdxVec& Seq, bool IsRead) { in genRWName() argument
334 Name += getSchedRW(*I, IsRead).Name; in genRWName()
340 unsigned CodeGenSchedModels::getSchedRWIdx(Record *Def, bool IsRead, in getSchedRWIdx() argument
342 const std::vector<CodeGenSchedRW> &RWVec = IsRead ? SchedReads : SchedWrites; in getSchedRWIdx()
393 bool IsRead) const { in findRWs()
395 unsigned Idx = getSchedRWIdx(*RI, IsRead); in findRWs()
402 bool IsRead) const { in expandRWSequence()
403 const CodeGenSchedRW &SchedRW = getSchedRW(RWIdx, IsRead); in expandRWSequence()
413 expandRWSequence(*I, RWSeq, IsRead); in expandRWSequence()
421 unsigned RWIdx, IdxVec &RWSeq, bool IsRead, in expandRWSeqForProc() argument
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| /NextBSD/contrib/llvm/tools/clang/include/clang/Sema/ |
| HD | ScopeInfo.h | 265 WeakUseTy(const Expr *Use, bool IsRead) : Rep(Use, IsRead) {} in WeakUseTy() argument
299 inline void recordUseOfWeak(const ExprT *E, bool IsRead = true);
826 void FunctionScopeInfo::recordUseOfWeak(const ExprT *E, bool IsRead) { in recordUseOfWeak() argument
829 Uses.push_back(WeakUseTy(E, IsRead)); in recordUseOfWeak()
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| HD | Sema.h | 1154 void recordUseOfEvaluatedWeak(const ExprT *E, bool IsRead=true) {
1156 getCurFunction()->recordUseOfWeak(E, IsRead);
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| /NextBSD/contrib/llvm/lib/Transforms/IPO/ |
| HD | FunctionAttrs.cpp | 424 bool IsRead = false; in determinePointerReadAttrs() local
475 IsRead = true; in determinePointerReadAttrs()
497 IsRead = true; in determinePointerReadAttrs()
505 IsRead = true; in determinePointerReadAttrs()
517 return IsRead ? Attribute::ReadOnly : Attribute::ReadNone; in determinePointerReadAttrs()
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| /NextBSD/contrib/compiler-rt/lib/tsan/rtl/ |
| HD | tsan_rtl.h | 249 bool ALWAYS_INLINE IsWrite() const { return !IsRead(); } in IsWrite()
250 bool ALWAYS_INLINE IsRead() const { return x_ & kReadBit; } in IsRead() function
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| HD | tsan_rtl.cc | 652 old.IsRead() <= cur.IsRead()) in ContainsSameAccessSlow()
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| /NextBSD/contrib/llvm/tools/clang/lib/CodeGen/ |
| HD | CGBuiltin.cpp | 3290 llvm::Type *ValueType, bool IsRead) { in EmitSpecialRegisterBuiltin() argument
3312 if (IsRead) { in EmitSpecialRegisterBuiltin()
3599 bool IsRead = BuiltinID == ARM::BI__builtin_arm_rsr || in EmitARMBuiltinExpr() local
3620 return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead); in EmitARMBuiltinExpr()
4384 bool IsRead = BuiltinID == AArch64::BI__builtin_arm_rsr || in EmitAArch64BuiltinExpr() local
4404 return EmitSpecialRegisterBuiltin(*this, E, RegisterType, ValueType, IsRead); in EmitAArch64BuiltinExpr()
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMISelDAGToDAG.cpp | 3475 static int getMClassRegisterMask(StringRef Reg, StringRef Flags, bool IsRead, in getMClassRegisterMask() argument
3489 if (IsRead) { in getMClassRegisterMask()
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