| /NextBSD/contrib/llvm/lib/Target/Mips/AsmParser/ |
| HD | MipsAsmParser.cpp | 181 SmallVectorImpl<MCInst> &Instructions);
184 SmallVectorImpl<MCInst> &Instructions);
188 SmallVectorImpl<MCInst> &Instructions);
192 SmallVectorImpl<MCInst> &Instructions);
195 SmallVectorImpl<MCInst> &Instructions);
198 SmallVectorImpl<MCInst> &Instructions);
201 SmallVectorImpl<MCInst> &Instructions);
203 SmallVectorImpl<MCInst> &Instructions);
206 SmallVectorImpl<MCInst> &Instructions, bool isLoad,
210 SmallVectorImpl<MCInst> &Instructions);
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| /NextBSD/contrib/llvm/lib/MC/ |
| HD | MCStreamer.cpp | 74 (MAB ? MAB->generateCompactUnwindEncoding(FI.Instructions) : 0); in generateCompactUnwindEncodings()
266 CurFrame->Instructions.push_back(Instruction); in EmitCFIDefCfa()
275 CurFrame->Instructions.push_back(Instruction); in EmitCFIDefCfaOffset()
283 CurFrame->Instructions.push_back(Instruction); in EmitCFIAdjustCfaOffset()
291 CurFrame->Instructions.push_back(Instruction); in EmitCFIDefCfaRegister()
300 CurFrame->Instructions.push_back(Instruction); in EmitCFIOffset()
308 CurFrame->Instructions.push_back(Instruction); in EmitCFIRelOffset()
330 CurFrame->Instructions.push_back(Instruction); in EmitCFIRememberState()
338 CurFrame->Instructions.push_back(Instruction); in EmitCFIRestoreState()
346 CurFrame->Instructions.push_back(Instruction); in EmitCFISameValue()
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| HD | MCWin64EH.cpp | 179 uint8_t numCodes = CountOfUnwindCodes(info->Instructions); in EmitUnwindInfo()
184 WinEH::Instruction &frameInst = info->Instructions[info->LastFrameInst]; in EmitUnwindInfo()
191 uint8_t numInst = info->Instructions.size(); in EmitUnwindInfo()
193 WinEH::Instruction inst = info->Instructions.back(); in EmitUnwindInfo()
194 info->Instructions.pop_back(); in EmitUnwindInfo()
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| /NextBSD/contrib/llvm/utils/TableGen/ |
| HD | CodeGenTarget.h | 69 std::unique_ptr<CodeGenInstruction>> Instructions; variable
152 if (Instructions.empty()) ReadInstructions(); in getInstructions()
153 return Instructions; in getInstructions()
158 if (Instructions.empty()) ReadInstructions(); in getInstruction()
159 auto I = Instructions.find(InstRec); in getInstruction()
160 assert(I != Instructions.end() && "Not an instruction"); in getInstruction()
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| HD | AsmWriterEmitter.cpp | 41 std::vector<AsmWriterInst> Instructions; member in __anon103a0dc20111::AsmWriterEmitter
487 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) { in EmitPrintInstruction()
489 AsmWriterInst &Inst = Instructions[i]; in EmitPrintInstruction()
491 Instructions.erase(Instructions.begin()+i); in EmitPrintInstruction()
499 std::reverse(Instructions.begin(), Instructions.end()); in EmitPrintInstruction()
506 if (!Instructions.empty()) { in EmitPrintInstruction()
509 while (!Instructions.empty()) in EmitPrintInstruction()
510 EmitInstructions(Instructions, O); in EmitPrintInstruction()
1108 Instructions.emplace_back(*I, AsmWriter->getValueAsInt("Variant"), in AsmWriterEmitter()
1117 for (unsigned i = 0, e = Instructions.size(); i != e; ++i) in AsmWriterEmitter()
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| /NextBSD/contrib/llvm/lib/Target/AArch64/ |
| HD | AArch64AddressTypePromotion.cpp | 102 typedef SmallVector<Instruction *, 16> Instructions; typedef in __anon9550f8050111::AArch64AddressTypePromotion
103 typedef DenseMap<Value *, Instructions> ValueToInsts;
121 bool propagateSignExtension(Instructions &SExtInsts);
135 void analyzeSExtension(Instructions &SExtInsts);
252 AArch64AddressTypePromotion::propagateSignExtension(Instructions &SExtInsts) { in propagateSignExtension()
382 Instructions &Insts = Entry.second; in mergeSExts()
383 Instructions CurPts; in mergeSExts()
416 void AArch64AddressTypePromotion::analyzeSExtension(Instructions &SExtInsts) { in analyzeSExtension()
489 Instructions SExtInsts; in runOnFunction()
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| /NextBSD/contrib/llvm/include/llvm/MC/ |
| HD | MCWinEH.h | 46 std::vector<Instruction> Instructions; member
52 ChainedParent(nullptr), Instructions() {} in FrameInfo()
57 ChainedParent(nullptr), Instructions() {} in FrameInfo()
63 ChainedParent(ChainedParent), Instructions() {} in FrameInfo()
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| /NextBSD/contrib/llvm/lib/Transforms/Scalar/ |
| HD | LoopRerollPass.cpp | 174 : Valid(false), Instructions(1, P) { in SimpleLoopReduction()
185 return Instructions.front(); in getPHI()
190 return Instructions.back(); in getReducedValue()
195 return Instructions[i+1]; in get()
203 return Instructions.size()-1; in size()
211 return std::next(Instructions.begin()); in begin()
216 return std::next(Instructions.begin()); in begin()
219 iterator end() { return Instructions.end(); } in end()
220 const_iterator end() const { return Instructions.end(); } in end()
224 SmallInstructionVector Instructions; member
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| HD | LoopDistribute.cpp | 441 auto Instructions = in computePartitionSetForPointers() local
447 for (Instruction *Inst : Instructions) { in computePartitionSetForPointers()
549 const SmallVectorImpl<Instruction *> &Instructions, in MemoryInstructionDependences() argument
551 Accesses.append(Instructions.begin(), Instructions.end()); in MemoryInstructionDependences()
562 DEBUG(Dep.print(dbgs(), 2, Instructions)); in MemoryInstructionDependences()
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| /NextBSD/contrib/llvm/lib/DebugInfo/DWARF/ |
| HD | DWARFDebugFrame.cpp | 75 std::vector<Instruction> Instructions; member in llvm::FrameEntry
80 Instructions.push_back(Instruction(Opcode)); in addInstruction()
84 Instructions.push_back(Instruction(Opcode)); in addInstruction()
85 Instructions.back().Ops.push_back(Operand1); in addInstruction()
89 Instructions.push_back(Instruction(Opcode)); in addInstruction()
90 Instructions.back().Ops.push_back(Operand1); in addInstruction()
91 Instructions.back().Ops.push_back(Operand2); in addInstruction()
414 for (const auto &Instr : Instructions) { in dumpInstructions()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/ |
| HD | SparcInstrVIS.td | 30 // For VIS Instructions with no operand.
35 // For VIS Instructions with only rs1, rd operands.
42 // For VIS Instructions with only rs2, rd operands.
49 // For VIS Instructions with only rd operand.
56 // VIS 1 Instructions
148 // VIS 2 Instructions.
165 // VIS 3 Instructions.
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| HD | SparcInstrInfo.td | 321 // Instructions
402 // Section B.1 - Load Integer Instructions, p. 90
411 // Section B.2 - Load Floating-point Instructions, p. 92
420 // Section B.4 - Store Integer Instructions, p. 95
427 // Section B.5 - Store Floating-point Instructions, p. 97
465 // Section B.11 - Logical Instructions, p. 106
504 // Section B.12 - Shift Instructions, p. 107
509 // Section B.13 - Add Instructions, p. 108
528 // Section B.15 - Subtract Instructions, p. 110
551 // Section B.18 - Multiply Instructions, p. 113
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| /NextBSD/contrib/llvm/lib/Target/Mips/ |
| HD | MicroMipsInstrInfo.td | 618 /// Compact Branch Instructions
624 /// Arithmetic Instructions (ALU Immediate)
644 /// Arithmetic Instructions (3-Operand, R-Type)
671 /// Arithmetic Instructions with PC and Immediate
674 /// Shift Instructions
692 /// Load and Store Instructions - aligned
708 /// Load and Store Instructions - unaligned
718 /// Load and Store Instructions - multiple
724 /// Load and Store Pair Instructions
728 /// Load and Store multiple pseudo Instructions
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| HD | Mips64InstrInfo.td | 79 // Instructions specific format
102 /// Arithmetic Instructions (ALU Immediate)
123 /// Arithmetic Instructions (3-Operand, R-Type)
142 /// Shift Instructions
162 // Rotate Instructions
171 /// Load and Store Instructions
209 /// Jump and Branch Instructions
226 /// Multiply and Divide Instructions.
259 /// Sign Ext In Register Instructions.
621 // Assembler Pseudo Instructions
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| /NextBSD/contrib/llvm/lib/Target/X86/ |
| HD | X86InstrArithmetic.td | 42 // Fixed-Register Multiplication and Division Instructions.
370 // Two address Instructions.
653 // BinOpRR - Instructions like "add reg, reg, reg".
662 // BinOpRR_F - Instructions like "cmp reg, Reg", where the pattern has
671 // BinOpRR_RF - Instructions like "add reg, reg, reg", where the pattern has
680 // BinOpRR_RFF - Instructions like "adc reg, reg, reg", where the pattern has
689 // BinOpRR_Rev - Instructions like "add reg, reg, reg" (reversed encoding).
703 // BinOpRR_RDD_Rev - Instructions like "adc reg, reg, reg" (reversed encoding).
707 // BinOpRR_F_Rev - Instructions like "cmp reg, reg" (reversed encoding).
719 // BinOpRM - Instructions like "add reg, reg, [mem]".
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| HD | X86InstrMMX.td | 217 // MMX Scalar Instructions
220 // Data Transfer Instructions
344 // Arithmetic Instructions
452 // Logical Instructions
462 // Shift Instructions
509 // Comparison Instructions
524 // -- Unpack Instructions
544 // -- Pack Instructions
552 // -- Shuffle Instructions
573 // -- Conversion Instructions
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| /NextBSD/contrib/gcc/config/arm/ |
| HD | arm926ejs.md | 49 ;; ALU Instructions
75 ;; Multiplication Instructions
114 ;; Load/Store Instructions
166 ;; Branch and Call Instructions
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| HD | arm1026ejs.md | 57 ;; ALU Instructions
89 ;; Multiplication Instructions
151 ;; Load/Store Instructions
219 ;; Branch and Call Instructions
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| /NextBSD/contrib/llvm/tools/bugpoint/ |
| HD | CrashDebugger.cpp | 456 SmallPtrSet<Instruction*, 64> Instructions; in TestInsts() local
459 Instructions.insert(cast<Instruction>(VMap[Insts[i]])); in TestInsts()
462 outs() << "Checking for crash with only " << Instructions.size(); in TestInsts()
463 if (Instructions.size() == 1) in TestInsts()
472 if (!Instructions.count(Inst) && !isa<TerminatorInst>(Inst) && in TestInsts()
492 for (Instruction *Inst : Instructions) in TestInsts()
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| /NextBSD/contrib/llvm/lib/Target/Sparc/AsmParser/ |
| HD | SparcAsmParser.cpp | 84 SmallVectorImpl<MCInst> &Instructions);
402 SmallVectorImpl<MCInst> &Instructions) { in expandSET() argument
427 Instructions.push_back(TmpInst); in expandSET()
440 Instructions.push_back(TmpInst); in expandSET()
450 SmallVector<MCInst, 8> Instructions; in MatchAndEmitInstruction() local
458 Instructions.push_back(Inst); in MatchAndEmitInstruction()
461 expandSET(Inst, IDLoc, Instructions); in MatchAndEmitInstruction()
465 for (const MCInst &I : Instructions) { in MatchAndEmitInstruction()
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| /NextBSD/contrib/llvm/lib/Target/PowerPC/ |
| HD | PPC.td | 201 // Instructions with the same BaseName and Interpretation64Bit values
204 // Instructions with the same RC value form a column.
214 // Instructions with the same BaseName and Interpretation64Bit values
217 // Instructions with the same RC value form a column.
227 // Instructions with the same BaseName and Interpretation64Bit values
230 // Instructions with the same RC value form a column.
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| /NextBSD/contrib/llvm/include/llvm/IR/ |
| HD | Instruction.def | 1 //===-- llvm/Instruction.def - File that describes Instructions -*- C++ -*-===//
92 // Terminator Instructions - These instructions are used to terminate a basic
143 // NOTE: (see Instructions.cpp) encodes a table based on this ordering.
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| /NextBSD/contrib/llvm/include/llvm/CodeGen/ |
| HD | MachineBasicBlock.h | 63 typedef ilist<MachineInstr> Instructions;
64 Instructions Insts;
205 typedef Instructions::iterator instr_iterator;
206 typedef Instructions::const_iterator const_instr_iterator;
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| /NextBSD/contrib/llvm/lib/Target/ARM/ |
| HD | ARMScheduleV6.td | 27 // Binary Instructions that produce a result
33 // Bitwise Instructions that produce a result
39 // Unary Instructions that produce a result
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| /NextBSD/contrib/llvm/lib/Target/MSP430/ |
| HD | MSP430InstrFormats.td | 76 // MSP430 Double Operand (Format I) Instructions
149 // MSP430 Single Operand (Format II) Instructions
196 // MSP430 Conditional Jumps Instructions
|