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Searched refs:IMPLICIT_DEF (Results 1 – 25 of 52) sorted by relevance

123

/NextBSD/contrib/llvm/lib/Target/AArch64/
HDAArch64InstrInfo.td1281 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1287 (INSERT_SUBREG (VecTy (IMPLICIT_DEF)),
1445 (INSERT_SUBREG (v8i8 (IMPLICIT_DEF)),
1449 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
1453 (INSERT_SUBREG (v4i16 (IMPLICIT_DEF)),
1457 (INSERT_SUBREG (v8i16 (IMPLICIT_DEF)),
1461 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)),
1465 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)),
1472 (INSERT_SUBREG (v2i64 (IMPLICIT_DEF)),
2657 (FCVTNv8i16 (INSERT_SUBREG (IMPLICIT_DEF), V64:$Rd, dsub), V128:$Rn)>;
[all …]
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetOpcodes.h52 IMPLICIT_DEF = 8, enumerator
HDTargetInstrInfo.h78 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
/NextBSD/contrib/llvm/lib/CodeGen/
HDMachineSSAUpdater.cpp151 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetValueInMiddleOfBlock()
288 MachineInstr *NewDef = InsertNewDef(TargetOpcode::IMPLICIT_DEF, in GetUndefVal()
HDProcessImplicitDefs.cpp90 UserMI->setDesc(TII->get(TargetOpcode::IMPLICIT_DEF)); in processImplicitDef()
HDPHIElimination.cpp251 TII->get(TargetOpcode::IMPLICIT_DEF), DestReg); in LowerPHINode()
391 TII->get(TargetOpcode::IMPLICIT_DEF), in LowerPHINode()
/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDResourcePriorityQueue.cpp267 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
307 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
553 if (N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in initNumRegDefsLeft()
HDInstrEmitter.cpp211 assert(Node->getMachineOpcode() != TargetOpcode::IMPLICIT_DEF && in CreateVirtualRegisters()
286 Op.getMachineOpcode() == TargetOpcode::IMPLICIT_DEF) { in getVR()
297 TII->get(TargetOpcode::IMPLICIT_DEF), VReg); in getVR()
745 if (Opc == TargetOpcode::IMPLICIT_DEF) in EmitMachineNode()
HDScheduleDAGSDNodes.cpp82 N->getMachineOpcode() == TargetOpcode::IMPLICIT_DEF)) in newSUnit()
537 if (POpc == TargetOpcode::IMPLICIT_DEF) { in InitNodeNumDefs()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86InstrAVX512.td656 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)),
657 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
660 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)),
661 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
664 (INSERT_SUBREG (v16i32 (IMPLICIT_DEF)),
665 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
668 (INSERT_SUBREG (v16f32 (IMPLICIT_DEF)),
669 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128X:$src, sub_xmm),
673 (INSERT_SUBREG (v8i64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
675 (INSERT_SUBREG (v8f64 (IMPLICIT_DEF)), VR256X:$src, sub_ymm)>;
[all …]
HDX86InstrSSE.td359 (INSERT_SUBREG (v4i64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
361 (INSERT_SUBREG (v4f64 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
363 (INSERT_SUBREG (v8i32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
365 (INSERT_SUBREG (v8f32 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
367 (INSERT_SUBREG (v16i16 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
369 (INSERT_SUBREG (v32i8 (IMPLICIT_DEF)), VR128:$src, sub_xmm)>;
1570 (VCVTSI2SSrm (f32 (IMPLICIT_DEF)), addr:$src)>;
1572 (VCVTSI2SS64rm (f32 (IMPLICIT_DEF)), addr:$src)>;
1574 (VCVTSI2SDrm (f64 (IMPLICIT_DEF)), addr:$src)>;
1576 (VCVTSI2SD64rm (f64 (IMPLICIT_DEF)), addr:$src)>;
[all …]
HDX86InstrShiftRotate.td932 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
936 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
941 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
945 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
950 (i32 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
954 (i64 (IMPLICIT_DEF)), GR8:$src2, sub_8bit))>;
/NextBSD/contrib/llvm/lib/Target/AMDGPU/
HDSILowerI1Copies.cpp88 if (MI.getOpcode() == AMDGPU::IMPLICIT_DEF) { in runOnMachineFunction()
HDR600EmitClauseMarkers.cpp96 case AMDGPU::IMPLICIT_DEF: in IsTrivialInst()
HDR600Packetizer.cpp355 if (MI->isKill() || MI->getOpcode() == AMDGPU::IMPLICIT_DEF || in runOnMachineFunction()
HDR600Instructions.td479 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
485 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), $reg, sub0),
491 (v4f32 (IMPLICIT_DEF)), imm:$type, 0, 7, 7, 7, 7, cf_inst, 0)
496 (v4f32 (IMPLICIT_DEF)), 1, 60, 7, 7, 7, 7, cf_inst, 0)
/NextBSD/contrib/llvm/lib/Target/Hexagon/
HDHexagonAsmPrinter.cpp192 MII->getOpcode() == TargetOpcode::IMPLICIT_DEF) in EmitInstruction()
HDHexagonMachineScheduler.cpp57 case TargetOpcode::IMPLICIT_DEF: in isResourceAvailable()
109 case TargetOpcode::IMPLICIT_DEF: in reserveResources()
/NextBSD/contrib/llvm/lib/Target/SystemZ/
HDSystemZInstrFP.td355 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
362 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_r32),
368 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
375 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
HDSystemZInstrVector.td998 (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar, subreg)>;
1000 (vrep (INSERT_SUBREG (vt (IMPLICIT_DEF)), cls:$scalar,
1011 (VPDI (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
1014 (VPDI VR128:$vec, (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), FP64:$elt,
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMInstrNEON.td4195 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
4199 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$Rm, ssub_0),
5705 (INSERT_SUBREG (v2f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5707 (INSERT_SUBREG (v2f64 (IMPLICIT_DEF)), DPR:$src, dsub_0)>;
5709 (INSERT_SUBREG (v4f32 (IMPLICIT_DEF)), SPR:$src, ssub_0)>;
5712 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5714 (VSETLNi16 (v4i16 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5716 (VSETLNi32 (v2i32 (IMPLICIT_DEF)), GPR:$src, (i32 0))>;
5719 (INSERT_SUBREG (v16i8 (IMPLICIT_DEF)),
5720 (VSETLNi8 (v8i8 (IMPLICIT_DEF)), GPR:$src, (i32 0)),
[all …]
HDA15SDOptimizer.cpp525 TII->get(TargetOpcode::IMPLICIT_DEF), Out); in createImplicitDef()
HDARMISelDAGToDAG.cpp1891 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0); in SelectVLD()
2002 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0) in SelectVST()
2050 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVST()
2168 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVLDSTLane()
2303 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, VT), 0) in SelectVTBL()
/NextBSD/contrib/llvm/include/llvm/CodeGen/
HDMachineInstr.h759 bool isImplicitDef() const { return getOpcode()==TargetOpcode::IMPLICIT_DEF; }
814 case TargetOpcode::IMPLICIT_DEF:
/NextBSD/contrib/llvm/lib/Target/MSP430/
HDMSP430InstrInfo.cpp304 case TargetOpcode::IMPLICIT_DEF: in GetInstSizeInBytes()

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