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Searched refs:ILP (Results 1 – 9 of 9) sorted by relevance

/NextBSD/contrib/llvm/lib/CodeGen/SelectionDAG/
HDScheduleDAGRRList.cpp2360 bool LStall = (!checkPref || left->SchedulingPref == Sched::ILP) && in BUCompareLatency()
2362 bool RStall = (!checkPref || right->SchedulingPref == Sched::ILP) && in BUCompareLatency()
2378 if (!checkPref || (left->SchedulingPref == Sched::ILP || in BUCompareLatency()
2379 right->SchedulingPref == Sched::ILP)) { in BUCompareLatency()
HDSelectionDAGISel.cpp306 assert(TLI->getSchedulingPreference() == Sched::ILP && in createDefaultScheduler()
/NextBSD/contrib/llvm/include/llvm/Target/
HDTargetLowering.h72 ILP, // Scheduling for ILP in low register pressure mode. enumerator
/NextBSD/contrib/llvm/lib/CodeGen/
HDTargetLoweringBase.cpp775 SchedPreferenceInfo = Sched::ILP; in TargetLoweringBase()
/NextBSD/contrib/llvm/lib/Target/ARM/
HDARMISelLowering.cpp1221 return Sched::ILP; in getSchedulingPreference()
1236 return Sched::ILP; in getSchedulingPreference()
/NextBSD/contrib/llvm/lib/Target/PowerPC/
HDPPCISelLowering.cpp11498 return Sched::ILP; in getSchedulingPreference()
/NextBSD/contrib/llvm/lib/Target/X86/
HDX86ISelLowering.cpp93 setSchedulingPreference(Sched::ILP); in X86TargetLowering()
95 setSchedulingPreference(Sched::ILP); in X86TargetLowering()
/NextBSD/contrib/gcc/doc/
HDinvoke.texi12378 your code has enough easily exploitable ILP to allow the compiler to
/NextBSD/crypto/heimdal/lib/wind/
HDNormalizationTest.txt9363 C782;C782;110B 1175 11B5;C782;110B 1175 11B5; # (잂; 잂; 잂; 잂; 잂; ) HANGUL SYLLABLE ILP