1 /*- 2 * Copyright (c) 2006 Olivier Houchard 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 16 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* $FreeBSD$ */ 28 29 #ifndef I83142_REG_H_ 30 #define I83142_REG_H_ 31 /* Physical Memory Map */ 32 /* 33 * 0x000000000 - 0x07FFFFFFF SDRAM 34 * 0x090100000 - 0x0901FFFFF ATUe Outbound IO Window 35 * 0x0F0000000 - 0x0F1FFFFFF Flash 36 * 0x0F2000000 - 0x0F20FFFFF PCE1 37 * 0x0F3000000 - 0x0FFCFFFFF Compact Flash 38 * 0x0FFD00000 - 0x0FFDFFFFF MMR 39 * 0x0FFFB0000 - 0x0FFFBFFFF ATU-X Outbound I/O Window 40 * 0x0FFFD0000 - 0x0FFFDFFFF ATUe Outbound I/O Window 41 * 0x100000000 - 0x1FFFFFFFF ATU-X outbound Memory Translation Window 42 * 0x2FF000000 - 0x2FFFFFFFF ATUe Outbound Memory Translation Window 43 */ 44 45 #define IOP34X_VADDR 0xf0000000 46 #define IOP34X_HWADDR 0xffd00000 47 #define IOP34X_SIZE 0x100000 48 49 #define IOP34X_ADMA0_OFFSET 0x00080000 50 #define IOP34X_ADMA1_OFFSET 0x00080200 51 #define IOP34X_ADMA2_OFFSET 0x00080400 52 #define IOP34X_ADMA_SIZE 0x200 53 54 55 /* ADMA Registers */ 56 #define IOP34X_ADMA_CCR 0x0000 /* Channel Control Register */ 57 #define IOP34X_ADMA_CSR 0x0004 /* Channel Status Register */ 58 #define IOP34X_ADMA_DAR 0x0008 /* Descriptor Address Register */ 59 #define IOP34X_ADMA_IPCR 0x0018 /* Internal Interface Parity Ctrl Reg */ 60 #define IOP34X_ADMA_NDAR 0x0024 /* Next Descriptor Register */ 61 #define IOP34X_ADMA_DCR 0x0028 /* Descriptor Control Register */ 62 63 #define IOP34X_ADMA_IE (1 << 0) /* Interrupt enable */ 64 #define IOP34X_ADMA_TR (1 << 1) /* Transfert Direction */ 65 /* 66 * Source Destination 67 * 00 Host I/O Interface Local Memory 68 * 01 Local Memory Host I/O Interface 69 * 10 Internal Bus Local Memory 70 * 11 Local Memory Internal Bus 71 */ 72 #define IOP34X_ADMA_SS (1 << 3) /* Source selection */ 73 /* 0000: Data Transfer / CRC / Memory Block Fill */ 74 #define IOP34X_ADMA_ZRBCE (1 << 7) /* Zero Result Buffer Check Enable */ 75 #define IOP34X_ADMA_MBFE (1 << 8) /* Memory Block Fill Enable */ 76 #define IOP34X_ADMA_CGE (1 << 9) /* CRC Generation enable */ 77 #define IOP34X_ADMA_CTD (1 << 10) /* CRC Transfer disable */ 78 #define IOP34X_ADMA_CSFD (1 << 11) /* CRC Seed fetch disable */ 79 #define IOP34X_ADMA_SWBE (1 << 12) /* Status write back enable */ 80 #define IOP34X_ADMA_ESE (1 << 13) /* Endian swap enable */ 81 #define IOP34X_ADMA_PQUTE (1 << 16) /* P+Q Update Transfer Enable */ 82 #define IOP34X_ADMA_DXE (1 << 17) /* Dual XOR Enable */ 83 #define IOP34X_ADMA_PQTE (1 << 18) /* P+Q Transfer Enable */ 84 #define IOP34X_ADMA_PTD (1 << 19) /* P Transfer Disable */ 85 #define IOP34X_ADMA_ROE (1 << 30) /* Relaxed Ordering Enable */ 86 #define IOP34X_ADMA_NSE (1U << 31) /* No Snoop Enable */ 87 88 #define IOP34X_PBBAR0 0x81588 /* PBI Base Address Register 0 */ 89 #define IOP34X_PBBAR0_ADDRMASK 0xfffff000 90 #define IOP34X_PBBAR1 0x81590 91 #define IOP34X_PCE1 0xF2000000 92 #define IOP34X_PCE1_SIZE 0x00100000 93 #define IOP34X_PCE1_VADDR 0xF1000000 94 #define IOP34X_ESSTSR0 0x82188 95 #define IOP34X_CONTROLLER_ONLY (1 << 14) 96 #define IOP34X_INT_SEL_PCIX (1 << 15) 97 #define IOP34X_PFR 0x82180 /* Processor Frequency Register */ 98 #define IOP34X_FREQ_MASK ((1 << 16) | (1 << 17) | (1 << 18)) 99 #define IOP34X_FREQ_600 (0) 100 #define IOP34X_FREQ_667 (1 << 16) 101 #define IOP34X_FREQ_800 (1 << 17) 102 #define IOP34X_FREQ_833 ((1 << 17) | (1 << 16)) 103 #define IOP34X_FREQ_1000 (1 << 18) 104 #define IOP34X_FREQ_1200 ((1 << 16) | (1 << 18)) 105 106 #define IOP34X_UART0_VADDR IOP34X_VADDR + 0x82300 107 #define IOP34X_UART0_HWADDR IOP34X_HWADDR + 0x82300 108 #define IOP34X_UART1_VADDR IOP34X_VADDR + 0x82340 109 #define IOP34X_UART1_HWADDR IOP34X_HWADDR + 0x82340 110 #define IOP34X_PBI_HWADDR 0xffd81580 111 112 /* SDRAM Memory Controller */ 113 #define SMC_SDBR 0x8180c /* Base Register */ 114 #define SMC_SDBR_BASEADDR (1 << 27) 115 #define SMC_SDBR_BASEADDR_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \ 116 | (1U << 31)) 117 #define SMC_SDUBR 0x81810 /* Upper Base Register */ 118 #define SMC_SBSR 0x81814 /* SDRAM Bank Size Register */ 119 #define SMC_SBSR_BANK_NB (1 << 2) /* Number of DDR Banks 120 0 => 2 Banks 121 1 => 1 Bank 122 */ 123 #define SMC_SBSR_BANK_SZ (1 << 27) /* SDRAM Bank Size : 124 0x00000 Empty 125 0x00001 128MB 126 0x00010 256MB 127 0x00100 512MB 128 0x01000 1GB 129 */ 130 #define SMC_SBSR_BANK_SZ_MASK ((1 << 27) | (1 << 28) | (1 << 29) | (1 << 30) \ 131 | (1U << 31)) 132 133 134 /* Two possible addresses for ATUe depending on configuration. */ 135 #define IOP34X_ATUE_ADDR(esstrsr) ((((esstrsr) & (IOP34X_CONTROLLER_ONLY | \ 136 IOP34X_INT_SEL_PCIX)) == (IOP34X_CONTROLLER_ONLY | IOP34X_INT_SEL_PCIX)) ? \ 137 0xffdc8000 : 0xffdcd000) 138 139 /* Three possible addresses for ATU-X depending on configuration. */ 140 #define IOP34X_ATUX_ADDR(esstrsr) (!((esstrsr) & IOP34X_CONTROLLER_ONLY) ? \ 141 0xffdcc000 : !((esstrsr) & IOP34X_INT_SEL_PCIX) ? 0xffdc8000 : 0xffdcd000) 142 143 #define IOP34X_OIOBAR_SIZE 0x10000 144 #define IOP34X_PCIX_OIOBAR 0xfffb0000 145 #define IOP34X_PCIX_OIOBAR_VADDR 0xf01b0000 146 #define IOP34X_PCIX_OMBAR 0x100000000 147 #define IOP34X_PCIE_OIOBAR 0xfffd0000 148 #define IOP34X_PCIE_OIOBAR_VADDR 0xf01d0000 149 #define IOP34X_PCIE_OMBAR 0x200000000 150 151 /* ATU Registers */ 152 /* Common for ATU-X and ATUe */ 153 #define ATU_VID 0x0000 /* ATU Vendor ID */ 154 #define ATU_DID 0x0002 /* ATU Device ID */ 155 #define ATU_CMD 0x0004 /* ATU Command Register */ 156 #define ATU_SR 0x0006 /* ATU Status Register */ 157 #define ATU_RID 0x0008 /* ATU Revision ID */ 158 #define ATU_CCR 0x0009 /* ATU Class Code */ 159 #define ATU_CLSR 0x000c /* ATU Cacheline Size */ 160 #define ATU_LT 0x000d /* ATU Latency Timer */ 161 #define ATU_HTR 0x000e /* ATU Header Type */ 162 #define ATU_BISTR 0x000f /* ATU BIST Register */ 163 #define ATU_IABAR0 0x0010 /* Inbound ATU Base Address register 0 */ 164 #define ATU_IAUBAR0 0x0014 /* Inbound ATU Upper Base Address Register 0 */ 165 #define ATU_IABAR1 0x0018 /* Inbound ATU Base Address Register 1 */ 166 #define ATU_IAUBAR1 0x001c /* Inbound ATU Upper Base Address Register 1 */ 167 #define ATU_IABAR2 0x0020 /* Inbound ATU Base Address Register 2 */ 168 #define ATU_IAUBAR2 0x0024 /* Inbound ATU Upper Base Address Register 2 */ 169 #define ATU_VSIR 0x002c /* ATU Subsystem Vendor ID Register */ 170 #define ATU_SIR 0x002e /* ATU Subsystem ID Register */ 171 #define ATU_ERBAR 0x0030 /* Expansion ROM Base Address Register */ 172 #define ATU_CAPPTR 0x0034 /* ATU Capabilities Pointer Register */ 173 #define ATU_ILR 0x003c /* ATU Interrupt Line Register */ 174 #define ATU_IPR 0x003d /* ATU Interrupt Pin Register */ 175 #define ATU_MGNT 0x003e /* ATU Minimum Grand Register */ 176 #define ATU_MLAT 0x003f /* ATU Maximum Latency Register */ 177 #define ATU_IALR0 0x0040 /* Inbound ATU Limit Register 0 */ 178 #define ATU_IATVR0 0x0044 /* Inbound ATU Translate Value Register 0 */ 179 #define ATU_IAUTVR0 0x0048 /* Inbound ATU Upper Translate Value Register 0*/ 180 #define ATU_IALR1 0x004c /* Inbound ATU Limit Register 1 */ 181 #define ATU_IATVR1 0x0050 /* Inbound ATU Translate Value Register 1 */ 182 #define ATU_IAUTVR1 0x0054 /* Inbound ATU Upper Translate Value Register 1*/ 183 #define ATU_IALR2 0x0058 /* Inbound ATU Limit Register 2 */ 184 #define ATU_IATVR2 0x005c /* Inbound ATU Translate Value Register 2 */ 185 #define ATU_IAUTVR2 0x0060 /* Inbound ATU Upper Translate Value Register 2*/ 186 #define ATU_ERLR 0x0064 /* Expansion ROM Limit Register */ 187 #define ATU_ERTVR 0x0068 /* Expansion ROM Translater Value Register */ 188 #define ATU_ERUTVR 0x006c /* Expansion ROM Upper Translate Value Register*/ 189 #define ATU_CR 0x0070 /* ATU Configuration Register */ 190 #define ATU_CR_OUT_EN (1 << 1) 191 #define ATU_PCSR 0x0074 /* PCI Configuration and Status Register */ 192 #define PCIE_BUSNO(x) ((x & 0xff000000) >> 24) 193 #define ATUX_CORE_RST ((1 << 30) | (1U << 31)) /* Core Processor Reset */ 194 #define ATUX_P_RSTOUT (1 << 21) /* Central Resource PCI Bus Reset */ 195 #define ATUE_CORE_RST ((1 << 9) | (1 << 8)) /* Core Processor Reset */ 196 #define ATU_ISR 0x0078 /* ATU Interrupt Status Register */ 197 #define ATUX_ISR_PIE (1 << 18) /* PCI Interface error */ 198 #define ATUX_ISR_IBPR (1 << 16) /* Internal Bus Parity Error */ 199 #define ATUX_ISR_DCE (1 << 14) /* Detected Correctable error */ 200 #define ATUX_ISR_ISCE (1 << 13) /* Initiated Split Completion Error Msg */ 201 #define ATUX_ISR_RSCE (1 << 12) /* Received Split Completion Error Msg */ 202 #define ATUX_ISR_DPE (1 << 9) /* Detected Parity Error */ 203 #define ATUX_ISR_IBMA (1 << 7) /* Internal Bus Master Abort */ 204 #define ATUX_ISR_PMA (1 << 3) /* PCI Master Abort */ 205 #define ATUX_ISR_PTAM (1 << 2) /* PCI Target Abort (Master) */ 206 #define ATUX_ISR_PTAT (1 << 1) /* PCI Target Abort (Target) */ 207 #define ATUX_ISR_PMPE (1 << 0) /* PCI Master Parity Error */ 208 #define ATUX_ISR_ERRMSK (ATUX_ISR_PIE | ATUX_ISR_IBPR | ATUX_ISR_DCE | \ 209 ATUX_ISR_ISCE | ATUX_ISR_RSCE | ATUX_ISR_DPE | ATUX_ISR_IBMA | ATUX_ISR_PMA\ 210 | ATUX_ISR_PTAM | ATUX_ISR_PTAT | ATUX_ISR_PMPE) 211 #define ATUE_ISR_HON (1 << 13) /* Halt on Error Interrupt */ 212 #define ATUE_ISR_RSE (1 << 12) /* Root System Error Message */ 213 #define ATUE_ISR_REM (1 << 11) /* Root Error Message */ 214 #define ATUE_ISR_PIE (1 << 10) /* PCI Interface error */ 215 #define ATUE_ISR_CEM (1 << 9) /* Correctable Error Message */ 216 #define ATUE_ISR_UEM (1 << 8) /* Uncorrectable error message */ 217 #define ATUE_ISR_CRS (1 << 7) /* Received Configuration Retry Status */ 218 #define ATUE_ISR_IBMA (1 << 5) /* Internal Bus Master Abort */ 219 #define ATUE_ISR_DPE (1 << 4) /* Detected Parity Error Interrupt */ 220 #define ATUE_ISR_MAI (1 << 3) /* Received Master Abort Interrupt */ 221 #define ATUE_ISR_STAI (1 << 2) /* Signaled Target Abort Interrupt */ 222 #define ATUE_ISR_TAI (1 << 1) /* Received Target Abort Interrupt */ 223 #define ATUE_ISR_MDPE (1 << 0) /* Master Data Parity Error Interrupt */ 224 #define ATUE_ISR_ERRMSK (ATUE_ISR_HON | ATUE_ISR_RSE | ATUE_ISR_REM | \ 225 ATUE_ISR_PIE | ATUE_ISR_CEM | ATUE_ISR_UEM | ATUE_ISR_CRS | ATUE_ISR_IBMA |\ 226 ATUE_ISR_DPE | ATUE_ISR_MAI | ATUE_ISR_STAI | ATUE_ISR_TAI | ATUE_ISR_MDPE) 227 #define ATU_IMR 0x007c /* ATU Interrupt Mask Register */ 228 /* 0x0080 - 0x008f reserved */ 229 #define ATU_VPDCID 0x0090 /* VPD Capability Identifier Register */ 230 #define ATU_VPDNIP 0x0091 /* VPD Next Item Pointer Register */ 231 #define ATU_VPDAR 0x0092 /* VPD Address Register */ 232 #define ATU_VPDDR 0x0094 /* VPD Data Register */ 233 #define ATU_PMCID 0x0098 /* PM Capability Identifier Register */ 234 #define ATU_PMNIPR 0x0099 /* PM Next Item Pointer Register */ 235 #define ATU_PMCR 0x009a /* ATU Power Management Capabilities Register */ 236 #define ATU_PMCSR 0x009c /* ATU Power Management Control/Status Register*/ 237 #define ATU_MSICIR 0x00a0 /* MSI Capability Identifier Register */ 238 #define ATU_MSINIPR 0x00a1 /* MSI Next Item Pointer Register */ 239 #define ATU_MCR 0x00a2 /* Message Control Register */ 240 #define ATU_MAR 0x00a4 /* Message Address Register */ 241 #define ATU_MUAR 0x00a8 /* Message Upper Address Register */ 242 #define ATU_MDR 0x00ac /* Message Data Register */ 243 #define ATU_PCIXSR 0x00d4 /* PCI-X Status Register */ 244 #define PCIXSR_BUSNO(x) (((x) & 0xff00) >> 8) 245 #define ATU_IABAR3 0x0200 /* Inbound ATU Base Address Register 3 */ 246 #define ATU_IAUBAR3 0x0204 /* Inbound ATU Upper Base Address Register 3 */ 247 #define ATU_IALR3 0x0208 /* Inbound ATU Limit Register 3 */ 248 #define ATU_ITVR3 0x020c /* Inbound ATU Upper Translate Value Reg 3 */ 249 #define ATU_OIOBAR 0x0300 /* Outbound I/O Base Address Register */ 250 #define ATU_OIOWTVR 0x0304 /* Outbound I/O Window Translate Value Reg */ 251 #define ATU_OUMBAR0 0x0308 /* Outbound Upper Memory Window base addr reg 0*/ 252 #define ATU_OUMBAR_FUNC (28) 253 #define ATU_OUMBAR_EN (1U << 31) 254 #define ATU_OUMWTVR0 0x030c /* Outbound Upper 32bit Memory Window Translate Value Register 0 */ 255 #define ATU_OUMBAR1 0x0310 /* Outbound Upper Memory Window base addr reg1*/ 256 #define ATU_OUMWTVR1 0x0314 /* Outbound Upper 32bit Memory Window Translate Value Register 1 */ 257 #define ATU_OUMBAR2 0x0318 /* Outbound Upper Memory Window base addr reg2*/ 258 #define ATU_OUMWTVR2 0x031c /* Outbount Upper 32bit Memory Window Translate Value Register 2 */ 259 #define ATU_OUMBAR3 0x0320 /* Outbound Upper Memory Window base addr reg3*/ 260 #define ATU_OUMWTVR3 0x0324 /* Outbound Upper 32bit Memory Window Translate Value Register 3 */ 261 262 /* ATU-X specific */ 263 #define ATUX_OCCAR 0x0330 /* Outbound Configuration Cycle Address Reg */ 264 #define ATUX_OCCDR 0x0334 /* Outbound Configuration Cycle Data Reg */ 265 #define ATUX_OCCFN 0x0338 /* Outbound Configuration Cycle Function Number*/ 266 /* ATUe specific */ 267 #define ATUE_OCCAR 0x032c /* Outbound Configuration Cycle Address Reg */ 268 #define ATUE_OCCDR 0x0330 /* Outbound Configuration Cycle Data Reg */ 269 #define ATUE_OCCFN 0x0334 /* Outbound Configuration Cycle Function Number*/ 270 /* Interrupts */ 271 272 /* IINTRSRC0 */ 273 #define ICU_INT_ADMA0_EOT (0) /* ADMA 0 End of transfer */ 274 #define ICU_INT_ADMA0_EOC (1) /* ADMA 0 End of Chain */ 275 #define ICU_INT_ADMA1_EOT (2) /* ADMA 1 End of transfer */ 276 #define ICU_INT_ADMA1_EOC (3) /* ADMA 1 End of chain */ 277 #define ICU_INT_ADMA2_EOT (4) /* ADMA 2 End of transfer */ 278 #define ICU_INT_ADMA2_EOC (5) /* ADMA 2 end of chain */ 279 #define ICU_INT_WDOG (6) /* Watchdog timer */ 280 /* 7 Reserved */ 281 #define ICU_INT_TIMER0 (8) /* Timer 0 */ 282 #define ICU_INT_TIMER1 (9) /* Timer 1 */ 283 #define ICU_INT_I2C0 (10) /* I2C bus interface 0 */ 284 #define ICU_INT_I2C1 (11) /* I2C bus interface 1 */ 285 #define ICU_INT_MU (12) /* Message Unit */ 286 #define ICU_INT_MU_IPQ (13) /* Message unit inbound post queue */ 287 #define ICU_INT_ATUE_IM (14) /* ATU-E inbound message */ 288 #define ICU_INT_ATU_BIST (15) /* ATU/Start BIST */ 289 #define ICU_INT_PMC (16) /* PMC */ 290 #define ICU_INT_PMU (17) /* PMU */ 291 #define ICU_INT_PC (18) /* Processor cache */ 292 /* 19-23 Reserved */ 293 #define ICU_INT_XINT0 (24) 294 #define ICU_INT_XINT1 (25) 295 #define ICU_INT_XINT2 (26) 296 #define ICU_INT_XINT3 (27) 297 #define ICU_INT_XINT4 (28) 298 #define ICU_INT_XINT5 (29) 299 #define ICU_INT_XINT6 (30) 300 #define ICU_INT_XINT7 (31) 301 /* IINTSRC1 */ 302 #define ICU_INT_XINT8 (32) 303 #define ICU_INT_XINT9 (33) 304 #define ICU_INT_XINT10 (34) 305 #define ICU_INT_XINT11 (35) 306 #define ICU_INT_XINT12 (36) 307 #define ICU_INT_XINT13 (37) 308 #define ICU_INT_XINT14 (38) 309 #define ICU_INT_XINT15 (39) 310 /* 40-50 reserved */ 311 #define ICU_INT_UART0 (51) /* UART 0 */ 312 #define ICU_INT_UART1 (52) /* UART 1 */ 313 #define ICU_INT_PBIUE (53) /* Peripheral bus interface unit error */ 314 #define ICU_INT_ATUCRW (54) /* ATU Configuration register write */ 315 #define ICU_INT_ATUE (55) /* ATU error */ 316 #define ICU_INT_MCUE (56) /* Memory controller unit error */ 317 #define ICU_INT_ADMA0E (57) /* ADMA Channel 0 error */ 318 #define ICU_INT_ADMA1E (58) /* ADMA Channel 1 error */ 319 #define ICU_INT_ADMA2E (59) /* ADMA Channel 2 error */ 320 /* 60-61 reserved */ 321 #define ICU_INT_MUE (62) /* Messaging Unit Error */ 322 /* 63 reserved */ 323 324 /* IINTSRC2 */ 325 #define ICU_INT_IP (64) /* Inter-processor */ 326 /* 65-93 reserved */ 327 #define ICU_INT_SIBBE (94) /* South internal bus bridge error */ 328 /* 95 reserved */ 329 330 /* IINTSRC3 */ 331 #define ICU_INT_I2C2 (96) /* I2C bus interface 2 */ 332 #define ICU_INT_ATUE_BIST (97) /* ATU-E/Start BIST */ 333 #define ICU_INT_ATUE_CRW (98) /* ATU-E Configuration register write */ 334 #define ICU_INT_ATUEE (99) /* ATU-E Error */ 335 #define ICU_INT_IMU (100) /* IMU */ 336 /* 101-106 reserved */ 337 #define ICU_INT_ATUE_MA (107) /* ATUE Interrupt message A */ 338 #define ICU_INT_ATUE_MB (108) /* ATUE Interrupt message B */ 339 #define ICU_INT_ATUE_MC (109) /* ATUE Interrupt message C */ 340 #define ICU_INT_ATUE_MD (110) /* ATUE Interrupt message D */ 341 #define ICU_INT_MU_MSIX_TW (111) /* MU MSI-X Table write */ 342 /* 112 reserved */ 343 #define ICU_INT_IMSI (113) /* Inbound MSI */ 344 /* 114-126 reserved */ 345 #define ICU_INT_HPI (127) /* HPI */ 346 347 348 #endif /* I81342_REG_H_ */ 349