1 /* 2 * Copyright 2009 Advanced Micro Devices, Inc. 3 * Copyright 2009 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice shall be included in 13 * all copies or substantial portions of the Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 21 * OTHER DEALINGS IN THE SOFTWARE. 22 * 23 * Authors: Dave Airlie 24 * Alex Deucher 25 * Jerome Glisse 26 */ 27 #ifndef R600D_H 28 #define R600D_H 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #define CP_PACKET2 0x80000000 34 #define PACKET2_PAD_SHIFT 0 35 #define PACKET2_PAD_MASK (0x3fffffff << 0) 36 37 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 38 39 #define R6XX_MAX_SH_GPRS 256 40 #define R6XX_MAX_TEMP_GPRS 16 41 #define R6XX_MAX_SH_THREADS 256 42 #define R6XX_MAX_SH_STACK_ENTRIES 4096 43 #define R6XX_MAX_BACKENDS 8 44 #define R6XX_MAX_BACKENDS_MASK 0xff 45 #define R6XX_MAX_SIMDS 8 46 #define R6XX_MAX_SIMDS_MASK 0xff 47 #define R6XX_MAX_PIPES 8 48 #define R6XX_MAX_PIPES_MASK 0xff 49 50 /* PTE flags */ 51 /* 52 * FIXME Linux<->FreeBSD: PTE_VALID is already defined on PowerPC on FreeBSD. 53 * Fortunately, it's never used in the Radeon driver. 54 */ 55 /* 56 #define PTE_VALID (1 << 0) 57 #define PTE_SYSTEM (1 << 1) 58 #define PTE_SNOOPED (1 << 2) 59 #define PTE_READABLE (1 << 5) 60 #define PTE_WRITEABLE (1 << 6) 61 */ 62 63 /* tiling bits */ 64 #define ARRAY_LINEAR_GENERAL 0x00000000 65 #define ARRAY_LINEAR_ALIGNED 0x00000001 66 #define ARRAY_1D_TILED_THIN1 0x00000002 67 #define ARRAY_2D_TILED_THIN1 0x00000004 68 69 /* Registers */ 70 #define ARB_POP 0x2418 71 #define ENABLE_TC128 (1 << 30) 72 #define ARB_GDEC_RD_CNTL 0x246C 73 74 #define CC_GC_SHADER_PIPE_CONFIG 0x8950 75 #define CC_RB_BACKEND_DISABLE 0x98F4 76 #define BACKEND_DISABLE(x) ((x) << 16) 77 78 #define R_028808_CB_COLOR_CONTROL 0x28808 79 #define S_028808_SPECIAL_OP(x) (((x) & 0x7) << 4) 80 #define G_028808_SPECIAL_OP(x) (((x) >> 4) & 0x7) 81 #define C_028808_SPECIAL_OP 0xFFFFFF8F 82 #define V_028808_SPECIAL_NORMAL 0x00 83 #define V_028808_SPECIAL_DISABLE 0x01 84 #define V_028808_SPECIAL_RESOLVE_BOX 0x07 85 86 #define CB_COLOR0_BASE 0x28040 87 #define CB_COLOR1_BASE 0x28044 88 #define CB_COLOR2_BASE 0x28048 89 #define CB_COLOR3_BASE 0x2804C 90 #define CB_COLOR4_BASE 0x28050 91 #define CB_COLOR5_BASE 0x28054 92 #define CB_COLOR6_BASE 0x28058 93 #define CB_COLOR7_BASE 0x2805C 94 #define CB_COLOR7_FRAG 0x280FC 95 96 #define CB_COLOR0_SIZE 0x28060 97 #define CB_COLOR0_VIEW 0x28080 98 #define R_028080_CB_COLOR0_VIEW 0x028080 99 #define S_028080_SLICE_START(x) (((x) & 0x7FF) << 0) 100 #define G_028080_SLICE_START(x) (((x) >> 0) & 0x7FF) 101 #define C_028080_SLICE_START 0xFFFFF800 102 #define S_028080_SLICE_MAX(x) (((x) & 0x7FF) << 13) 103 #define G_028080_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 104 #define C_028080_SLICE_MAX 0xFF001FFF 105 #define R_028084_CB_COLOR1_VIEW 0x028084 106 #define R_028088_CB_COLOR2_VIEW 0x028088 107 #define R_02808C_CB_COLOR3_VIEW 0x02808C 108 #define R_028090_CB_COLOR4_VIEW 0x028090 109 #define R_028094_CB_COLOR5_VIEW 0x028094 110 #define R_028098_CB_COLOR6_VIEW 0x028098 111 #define R_02809C_CB_COLOR7_VIEW 0x02809C 112 #define R_028100_CB_COLOR0_MASK 0x028100 113 #define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0) 114 #define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF) 115 #define C_028100_CMASK_BLOCK_MAX 0xFFFFF000 116 #define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12) 117 #define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF) 118 #define C_028100_FMASK_TILE_MAX 0x00000FFF 119 #define R_028104_CB_COLOR1_MASK 0x028104 120 #define R_028108_CB_COLOR2_MASK 0x028108 121 #define R_02810C_CB_COLOR3_MASK 0x02810C 122 #define R_028110_CB_COLOR4_MASK 0x028110 123 #define R_028114_CB_COLOR5_MASK 0x028114 124 #define R_028118_CB_COLOR6_MASK 0x028118 125 #define R_02811C_CB_COLOR7_MASK 0x02811C 126 #define CB_COLOR0_INFO 0x280a0 127 # define CB_FORMAT(x) ((x) << 2) 128 # define CB_ARRAY_MODE(x) ((x) << 8) 129 # define CB_SOURCE_FORMAT(x) ((x) << 27) 130 # define CB_SF_EXPORT_FULL 0 131 # define CB_SF_EXPORT_NORM 1 132 #define CB_COLOR0_TILE 0x280c0 133 #define CB_COLOR0_FRAG 0x280e0 134 #define CB_COLOR0_MASK 0x28100 135 136 #define SQ_ALU_CONST_CACHE_PS_0 0x28940 137 #define SQ_ALU_CONST_CACHE_PS_1 0x28944 138 #define SQ_ALU_CONST_CACHE_PS_2 0x28948 139 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c 140 #define SQ_ALU_CONST_CACHE_PS_4 0x28950 141 #define SQ_ALU_CONST_CACHE_PS_5 0x28954 142 #define SQ_ALU_CONST_CACHE_PS_6 0x28958 143 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c 144 #define SQ_ALU_CONST_CACHE_PS_8 0x28960 145 #define SQ_ALU_CONST_CACHE_PS_9 0x28964 146 #define SQ_ALU_CONST_CACHE_PS_10 0x28968 147 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c 148 #define SQ_ALU_CONST_CACHE_PS_12 0x28970 149 #define SQ_ALU_CONST_CACHE_PS_13 0x28974 150 #define SQ_ALU_CONST_CACHE_PS_14 0x28978 151 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c 152 #define SQ_ALU_CONST_CACHE_VS_0 0x28980 153 #define SQ_ALU_CONST_CACHE_VS_1 0x28984 154 #define SQ_ALU_CONST_CACHE_VS_2 0x28988 155 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c 156 #define SQ_ALU_CONST_CACHE_VS_4 0x28990 157 #define SQ_ALU_CONST_CACHE_VS_5 0x28994 158 #define SQ_ALU_CONST_CACHE_VS_6 0x28998 159 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c 160 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0 161 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4 162 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8 163 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac 164 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0 165 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4 166 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8 167 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc 168 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0 169 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4 170 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8 171 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc 172 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0 173 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4 174 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8 175 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc 176 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0 177 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4 178 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8 179 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec 180 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0 181 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4 182 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8 183 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc 184 185 #define CONFIG_MEMSIZE 0x5428 186 #define CONFIG_CNTL 0x5424 187 #define CP_STALLED_STAT1 0x8674 188 #define CP_STALLED_STAT2 0x8678 189 #define CP_BUSY_STAT 0x867C 190 #define CP_STAT 0x8680 191 #define CP_COHER_BASE 0x85F8 192 #define CP_DEBUG 0xC1FC 193 #define R_0086D8_CP_ME_CNTL 0x86D8 194 #define S_0086D8_CP_ME_HALT(x) (((x) & 1)<<28) 195 #define C_0086D8_CP_ME_HALT(x) ((x) & 0xEFFFFFFF) 196 #define CP_ME_RAM_DATA 0xC160 197 #define CP_ME_RAM_RADDR 0xC158 198 #define CP_ME_RAM_WADDR 0xC15C 199 #define CP_MEQ_THRESHOLDS 0x8764 200 #define MEQ_END(x) ((x) << 16) 201 #define ROQ_END(x) ((x) << 24) 202 #define CP_PERFMON_CNTL 0x87FC 203 #define CP_PFP_UCODE_ADDR 0xC150 204 #define CP_PFP_UCODE_DATA 0xC154 205 #define CP_QUEUE_THRESHOLDS 0x8760 206 #define ROQ_IB1_START(x) ((x) << 0) 207 #define ROQ_IB2_START(x) ((x) << 8) 208 #define CP_RB_BASE 0xC100 209 #define CP_RB_CNTL 0xC104 210 #define RB_BUFSZ(x) ((x) << 0) 211 #define RB_BLKSZ(x) ((x) << 8) 212 #define RB_NO_UPDATE (1 << 27) 213 #define RB_RPTR_WR_ENA (1U << 31) 214 #define BUF_SWAP_32BIT (2 << 16) 215 #define CP_RB_RPTR 0x8700 216 #define CP_RB_RPTR_ADDR 0xC10C 217 #define RB_RPTR_SWAP(x) ((x) << 0) 218 #define CP_RB_RPTR_ADDR_HI 0xC110 219 #define CP_RB_RPTR_WR 0xC108 220 #define CP_RB_WPTR 0xC114 221 #define CP_RB_WPTR_ADDR 0xC118 222 #define CP_RB_WPTR_ADDR_HI 0xC11C 223 #define CP_RB_WPTR_DELAY 0x8704 224 #define CP_ROQ_IB1_STAT 0x8784 225 #define CP_ROQ_IB2_STAT 0x8788 226 #define CP_SEM_WAIT_TIMER 0x85BC 227 228 #define DB_DEBUG 0x9830 229 #define PREZ_MUST_WAIT_FOR_POSTZ_DONE (1U << 31) 230 #define DB_DEPTH_BASE 0x2800C 231 #define DB_HTILE_DATA_BASE 0x28014 232 #define DB_HTILE_SURFACE 0x28D24 233 #define S_028D24_HTILE_WIDTH(x) (((x) & 0x1) << 0) 234 #define G_028D24_HTILE_WIDTH(x) (((x) >> 0) & 0x1) 235 #define C_028D24_HTILE_WIDTH 0xFFFFFFFE 236 #define S_028D24_HTILE_HEIGHT(x) (((x) & 0x1) << 1) 237 #define G_028D24_HTILE_HEIGHT(x) (((x) >> 1) & 0x1) 238 #define C_028D24_HTILE_HEIGHT 0xFFFFFFFD 239 #define G_028D24_LINEAR(x) (((x) >> 2) & 0x1) 240 #define DB_WATERMARKS 0x9838 241 #define DEPTH_FREE(x) ((x) << 0) 242 #define DEPTH_FLUSH(x) ((x) << 5) 243 #define DEPTH_PENDING_FREE(x) ((x) << 15) 244 #define DEPTH_CACHELINE_FREE(x) ((x) << 20) 245 246 #define DCP_TILING_CONFIG 0x6CA0 247 #define PIPE_TILING(x) ((x) << 1) 248 #define BANK_TILING(x) ((x) << 4) 249 #define GROUP_SIZE(x) ((x) << 6) 250 #define ROW_TILING(x) ((x) << 8) 251 #define BANK_SWAPS(x) ((x) << 11) 252 #define SAMPLE_SPLIT(x) ((x) << 14) 253 #define BACKEND_MAP(x) ((x) << 16) 254 255 #define GB_TILING_CONFIG 0x98F0 256 #define PIPE_TILING__SHIFT 1 257 #define PIPE_TILING__MASK 0x0000000e 258 259 #define GC_USER_SHADER_PIPE_CONFIG 0x8954 260 #define INACTIVE_QD_PIPES(x) ((x) << 8) 261 #define INACTIVE_QD_PIPES_MASK 0x0000FF00 262 #define INACTIVE_SIMDS(x) ((x) << 16) 263 #define INACTIVE_SIMDS_MASK 0x00FF0000 264 265 #define SQ_CONFIG 0x8c00 266 # define VC_ENABLE (1 << 0) 267 # define EXPORT_SRC_C (1 << 1) 268 # define DX9_CONSTS (1 << 2) 269 # define ALU_INST_PREFER_VECTOR (1 << 3) 270 # define DX10_CLAMP (1 << 4) 271 # define CLAUSE_SEQ_PRIO(x) ((x) << 8) 272 # define PS_PRIO(x) ((x) << 24) 273 # define VS_PRIO(x) ((x) << 26) 274 # define GS_PRIO(x) ((x) << 28) 275 # define ES_PRIO(x) ((x) << 30) 276 #define SQ_GPR_RESOURCE_MGMT_1 0x8c04 277 # define NUM_PS_GPRS(x) ((x) << 0) 278 # define NUM_VS_GPRS(x) ((x) << 16) 279 # define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28) 280 #define SQ_GPR_RESOURCE_MGMT_2 0x8c08 281 # define NUM_GS_GPRS(x) ((x) << 0) 282 # define NUM_ES_GPRS(x) ((x) << 16) 283 #define SQ_THREAD_RESOURCE_MGMT 0x8c0c 284 # define NUM_PS_THREADS(x) ((x) << 0) 285 # define NUM_VS_THREADS(x) ((x) << 8) 286 # define NUM_GS_THREADS(x) ((x) << 16) 287 # define NUM_ES_THREADS(x) ((x) << 24) 288 #define SQ_STACK_RESOURCE_MGMT_1 0x8c10 289 # define NUM_PS_STACK_ENTRIES(x) ((x) << 0) 290 # define NUM_VS_STACK_ENTRIES(x) ((x) << 16) 291 #define SQ_STACK_RESOURCE_MGMT_2 0x8c14 292 # define NUM_GS_STACK_ENTRIES(x) ((x) << 0) 293 # define NUM_ES_STACK_ENTRIES(x) ((x) << 16) 294 #define SQ_ESGS_RING_BASE 0x8c40 295 #define SQ_GSVS_RING_BASE 0x8c48 296 #define SQ_ESTMP_RING_BASE 0x8c50 297 #define SQ_GSTMP_RING_BASE 0x8c58 298 #define SQ_VSTMP_RING_BASE 0x8c60 299 #define SQ_PSTMP_RING_BASE 0x8c68 300 #define SQ_FBUF_RING_BASE 0x8c70 301 #define SQ_REDUC_RING_BASE 0x8c78 302 303 #define GRBM_CNTL 0x8000 304 # define GRBM_READ_TIMEOUT(x) ((x) << 0) 305 #define GRBM_STATUS 0x8010 306 #define CMDFIFO_AVAIL_MASK 0x0000001F 307 #define GUI_ACTIVE (1<<31) 308 #define GRBM_STATUS2 0x8014 309 #define GRBM_SOFT_RESET 0x8020 310 #define SOFT_RESET_CP (1<<0) 311 312 #define CG_THERMAL_STATUS 0x7F4 313 #define ASIC_T(x) ((x) << 0) 314 #define ASIC_T_MASK 0x1FF 315 #define ASIC_T_SHIFT 0 316 317 #define HDP_HOST_PATH_CNTL 0x2C00 318 #define HDP_NONSURFACE_BASE 0x2C04 319 #define HDP_NONSURFACE_INFO 0x2C08 320 #define HDP_NONSURFACE_SIZE 0x2C0C 321 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 322 #define HDP_TILING_CONFIG 0x2F3C 323 #define HDP_DEBUG1 0x2F34 324 325 #define MC_VM_AGP_TOP 0x2184 326 #define MC_VM_AGP_BOT 0x2188 327 #define MC_VM_AGP_BASE 0x218C 328 #define MC_VM_FB_LOCATION 0x2180 329 #define MC_VM_L1_TLB_MCD_RD_A_CNTL 0x219C 330 #define ENABLE_L1_TLB (1 << 0) 331 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 332 #define ENABLE_L1_STRICT_ORDERING (1 << 2) 333 #define SYSTEM_ACCESS_MODE_MASK 0x000000C0 334 #define SYSTEM_ACCESS_MODE_SHIFT 6 335 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 6) 336 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 6) 337 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 6) 338 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 6) 339 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 8) 340 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE (1 << 8) 341 #define ENABLE_SEMAPHORE_MODE (1 << 10) 342 #define ENABLE_WAIT_L2_QUERY (1 << 11) 343 #define EFFECTIVE_L1_TLB_SIZE(x) (((x) & 7) << 12) 344 #define EFFECTIVE_L1_TLB_SIZE_MASK 0x00007000 345 #define EFFECTIVE_L1_TLB_SIZE_SHIFT 12 346 #define EFFECTIVE_L1_QUEUE_SIZE(x) (((x) & 7) << 15) 347 #define EFFECTIVE_L1_QUEUE_SIZE_MASK 0x00038000 348 #define EFFECTIVE_L1_QUEUE_SIZE_SHIFT 15 349 #define MC_VM_L1_TLB_MCD_RD_B_CNTL 0x21A0 350 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL 0x21FC 351 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL 0x2204 352 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL 0x2208 353 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL 0x220C 354 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL 0x2200 355 #define MC_VM_L1_TLB_MCD_WR_A_CNTL 0x21A4 356 #define MC_VM_L1_TLB_MCD_WR_B_CNTL 0x21A8 357 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL 0x2210 358 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL 0x2218 359 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL 0x221C 360 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL 0x2220 361 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL 0x2214 362 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2190 363 #define LOGICAL_PAGE_NUMBER_MASK 0x000FFFFF 364 #define LOGICAL_PAGE_NUMBER_SHIFT 0 365 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2194 366 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x2198 367 368 #define PA_CL_ENHANCE 0x8A14 369 #define CLIP_VTX_REORDER_ENA (1 << 0) 370 #define NUM_CLIP_SEQ(x) ((x) << 1) 371 #define PA_SC_AA_CONFIG 0x28C04 372 #define PA_SC_AA_SAMPLE_LOCS_2S 0x8B40 373 #define PA_SC_AA_SAMPLE_LOCS_4S 0x8B44 374 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0 0x8B48 375 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1 0x8B4C 376 #define S0_X(x) ((x) << 0) 377 #define S0_Y(x) ((x) << 4) 378 #define S1_X(x) ((x) << 8) 379 #define S1_Y(x) ((x) << 12) 380 #define S2_X(x) ((x) << 16) 381 #define S2_Y(x) ((x) << 20) 382 #define S3_X(x) ((x) << 24) 383 #define S3_Y(x) ((x) << 28) 384 #define S4_X(x) ((x) << 0) 385 #define S4_Y(x) ((x) << 4) 386 #define S5_X(x) ((x) << 8) 387 #define S5_Y(x) ((x) << 12) 388 #define S6_X(x) ((x) << 16) 389 #define S6_Y(x) ((x) << 20) 390 #define S7_X(x) ((x) << 24) 391 #define S7_Y(x) ((x) << 28) 392 #define PA_SC_CLIPRECT_RULE 0x2820c 393 #define PA_SC_ENHANCE 0x8BF0 394 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 395 #define FORCE_EOV_MAX_TILE_CNT(x) ((x) << 12) 396 #define PA_SC_LINE_STIPPLE 0x28A0C 397 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 398 #define PA_SC_MODE_CNTL 0x28A4C 399 #define PA_SC_MULTI_CHIP_CNTL 0x8B20 400 401 #define PA_SC_SCREEN_SCISSOR_TL 0x28030 402 #define PA_SC_GENERIC_SCISSOR_TL 0x28240 403 #define PA_SC_WINDOW_SCISSOR_TL 0x28204 404 405 #define PCIE_PORT_INDEX 0x0038 406 #define PCIE_PORT_DATA 0x003C 407 408 #define CHMAP 0x2004 409 #define NOOFCHAN_SHIFT 12 410 #define NOOFCHAN_MASK 0x00003000 411 412 #define RAMCFG 0x2408 413 #define NOOFBANK_SHIFT 0 414 #define NOOFBANK_MASK 0x00000001 415 #define NOOFRANK_SHIFT 1 416 #define NOOFRANK_MASK 0x00000002 417 #define NOOFROWS_SHIFT 2 418 #define NOOFROWS_MASK 0x0000001C 419 #define NOOFCOLS_SHIFT 5 420 #define NOOFCOLS_MASK 0x00000060 421 #define CHANSIZE_SHIFT 7 422 #define CHANSIZE_MASK 0x00000080 423 #define BURSTLENGTH_SHIFT 8 424 #define BURSTLENGTH_MASK 0x00000100 425 #define CHANSIZE_OVERRIDE (1 << 10) 426 427 #define SCRATCH_REG0 0x8500 428 #define SCRATCH_REG1 0x8504 429 #define SCRATCH_REG2 0x8508 430 #define SCRATCH_REG3 0x850C 431 #define SCRATCH_REG4 0x8510 432 #define SCRATCH_REG5 0x8514 433 #define SCRATCH_REG6 0x8518 434 #define SCRATCH_REG7 0x851C 435 #define SCRATCH_UMSK 0x8540 436 #define SCRATCH_ADDR 0x8544 437 438 #define SPI_CONFIG_CNTL 0x9100 439 #define GPR_WRITE_PRIORITY(x) ((x) << 0) 440 #define DISABLE_INTERP_1 (1 << 5) 441 #define SPI_CONFIG_CNTL_1 0x913C 442 #define VTX_DONE_DELAY(x) ((x) << 0) 443 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 444 #define SPI_INPUT_Z 0x286D8 445 #define SPI_PS_IN_CONTROL_0 0x286CC 446 #define NUM_INTERP(x) ((x)<<0) 447 #define POSITION_ENA (1<<8) 448 #define POSITION_CENTROID (1<<9) 449 #define POSITION_ADDR(x) ((x)<<10) 450 #define PARAM_GEN(x) ((x)<<15) 451 #define PARAM_GEN_ADDR(x) ((x)<<19) 452 #define BARYC_SAMPLE_CNTL(x) ((x)<<26) 453 #define PERSP_GRADIENT_ENA (1<<28) 454 #define LINEAR_GRADIENT_ENA (1<<29) 455 #define POSITION_SAMPLE (1<<30) 456 #define BARYC_AT_SAMPLE_ENA (1<<31) 457 #define SPI_PS_IN_CONTROL_1 0x286D0 458 #define GEN_INDEX_PIX (1<<0) 459 #define GEN_INDEX_PIX_ADDR(x) ((x)<<1) 460 #define FRONT_FACE_ENA (1<<8) 461 #define FRONT_FACE_CHAN(x) ((x)<<9) 462 #define FRONT_FACE_ALL_BITS (1<<11) 463 #define FRONT_FACE_ADDR(x) ((x)<<12) 464 #define FOG_ADDR(x) ((x)<<17) 465 #define FIXED_PT_POSITION_ENA (1<<24) 466 #define FIXED_PT_POSITION_ADDR(x) ((x)<<25) 467 468 #define SQ_MS_FIFO_SIZES 0x8CF0 469 #define CACHE_FIFO_SIZE(x) ((x) << 0) 470 #define FETCH_FIFO_HIWATER(x) ((x) << 8) 471 #define DONE_FIFO_HIWATER(x) ((x) << 16) 472 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24) 473 #define SQ_PGM_START_ES 0x28880 474 #define SQ_PGM_START_FS 0x28894 475 #define SQ_PGM_START_GS 0x2886C 476 #define SQ_PGM_START_PS 0x28840 477 #define SQ_PGM_RESOURCES_PS 0x28850 478 #define SQ_PGM_EXPORTS_PS 0x28854 479 #define SQ_PGM_CF_OFFSET_PS 0x288cc 480 #define SQ_PGM_START_VS 0x28858 481 #define SQ_PGM_RESOURCES_VS 0x28868 482 #define SQ_PGM_CF_OFFSET_VS 0x288d0 483 484 #define SQ_VTX_CONSTANT_WORD0_0 0x30000 485 #define SQ_VTX_CONSTANT_WORD1_0 0x30004 486 #define SQ_VTX_CONSTANT_WORD2_0 0x30008 487 # define SQ_VTXC_BASE_ADDR_HI(x) ((x) << 0) 488 # define SQ_VTXC_STRIDE(x) ((x) << 8) 489 # define SQ_VTXC_ENDIAN_SWAP(x) ((x) << 30) 490 # define SQ_ENDIAN_NONE 0 491 # define SQ_ENDIAN_8IN16 1 492 # define SQ_ENDIAN_8IN32 2 493 #define SQ_VTX_CONSTANT_WORD3_0 0x3000c 494 #define SQ_VTX_CONSTANT_WORD6_0 0x38018 495 #define S__SQ_VTX_CONSTANT_TYPE(x) (((x) & 3) << 30) 496 #define G__SQ_VTX_CONSTANT_TYPE(x) (((x) >> 30) & 3) 497 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0 498 #define SQ_TEX_VTX_INVALID_BUFFER 0x1 499 #define SQ_TEX_VTX_VALID_TEXTURE 0x2 500 #define SQ_TEX_VTX_VALID_BUFFER 0x3 501 502 503 #define SX_MISC 0x28350 504 #define SX_MEMORY_EXPORT_BASE 0x9010 505 #define SX_DEBUG_1 0x9054 506 #define SMX_EVENT_RELEASE (1 << 0) 507 #define ENABLE_NEW_SMX_ADDRESS (1 << 16) 508 509 #define TA_CNTL_AUX 0x9508 510 #define DISABLE_CUBE_WRAP (1 << 0) 511 #define DISABLE_CUBE_ANISO (1 << 1) 512 #define SYNC_GRADIENT (1 << 24) 513 #define SYNC_WALKER (1 << 25) 514 #define SYNC_ALIGNER (1 << 26) 515 #define BILINEAR_PRECISION_6_BIT (0 << 31) 516 #define BILINEAR_PRECISION_8_BIT (1U << 31) 517 518 #define TC_CNTL 0x9608 519 #define TC_L2_SIZE(x) ((x)<<5) 520 #define L2_DISABLE_LATE_HIT (1<<9) 521 522 #define VC_ENHANCE 0x9714 523 524 #define VGT_CACHE_INVALIDATION 0x88C4 525 #define CACHE_INVALIDATION(x) ((x)<<0) 526 #define VC_ONLY 0 527 #define TC_ONLY 1 528 #define VC_AND_TC 2 529 #define VGT_DMA_BASE 0x287E8 530 #define VGT_DMA_BASE_HI 0x287E4 531 #define VGT_ES_PER_GS 0x88CC 532 #define VGT_GS_PER_ES 0x88C8 533 #define VGT_GS_PER_VS 0x88E8 534 #define VGT_GS_VERTEX_REUSE 0x88D4 535 #define VGT_PRIMITIVE_TYPE 0x8958 536 #define VGT_NUM_INSTANCES 0x8974 537 #define VGT_OUT_DEALLOC_CNTL 0x28C5C 538 #define DEALLOC_DIST_MASK 0x0000007F 539 #define VGT_STRMOUT_BASE_OFFSET_0 0x28B10 540 #define VGT_STRMOUT_BASE_OFFSET_1 0x28B14 541 #define VGT_STRMOUT_BASE_OFFSET_2 0x28B18 542 #define VGT_STRMOUT_BASE_OFFSET_3 0x28B1c 543 #define VGT_STRMOUT_BASE_OFFSET_HI_0 0x28B44 544 #define VGT_STRMOUT_BASE_OFFSET_HI_1 0x28B48 545 #define VGT_STRMOUT_BASE_OFFSET_HI_2 0x28B4c 546 #define VGT_STRMOUT_BASE_OFFSET_HI_3 0x28B50 547 #define VGT_STRMOUT_BUFFER_BASE_0 0x28AD8 548 #define VGT_STRMOUT_BUFFER_BASE_1 0x28AE8 549 #define VGT_STRMOUT_BUFFER_BASE_2 0x28AF8 550 #define VGT_STRMOUT_BUFFER_BASE_3 0x28B08 551 #define VGT_STRMOUT_BUFFER_OFFSET_0 0x28ADC 552 #define VGT_STRMOUT_BUFFER_OFFSET_1 0x28AEC 553 #define VGT_STRMOUT_BUFFER_OFFSET_2 0x28AFC 554 #define VGT_STRMOUT_BUFFER_OFFSET_3 0x28B0C 555 #define VGT_STRMOUT_BUFFER_SIZE_0 0x28AD0 556 #define VGT_STRMOUT_BUFFER_SIZE_1 0x28AE0 557 #define VGT_STRMOUT_BUFFER_SIZE_2 0x28AF0 558 #define VGT_STRMOUT_BUFFER_SIZE_3 0x28B00 559 560 #define VGT_STRMOUT_EN 0x28AB0 561 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58 562 #define VTX_REUSE_DEPTH_MASK 0x000000FF 563 #define VGT_EVENT_INITIATOR 0x28a90 564 # define CACHE_FLUSH_AND_INV_EVENT_TS (0x14 << 0) 565 # define CACHE_FLUSH_AND_INV_EVENT (0x16 << 0) 566 567 #define VM_CONTEXT0_CNTL 0x1410 568 #define ENABLE_CONTEXT (1 << 0) 569 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 570 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 571 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR 0x1490 572 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR 0x14B0 573 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x1574 574 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x1594 575 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x15B4 576 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1554 577 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470 578 #define REQUEST_TYPE(x) (((x) & 0xf) << 0) 579 #define RESPONSE_TYPE_MASK 0x000000F0 580 #define RESPONSE_TYPE_SHIFT 4 581 #define VM_L2_CNTL 0x1400 582 #define ENABLE_L2_CACHE (1 << 0) 583 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 584 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 585 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 13) 586 #define VM_L2_CNTL2 0x1404 587 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 588 #define INVALIDATE_L2_CACHE (1 << 1) 589 #define VM_L2_CNTL3 0x1408 590 #define BANK_SELECT_0(x) (((x) & 0x1f) << 0) 591 #define BANK_SELECT_1(x) (((x) & 0x1f) << 5) 592 #define L2_CACHE_UPDATE_MODE(x) (((x) & 3) << 10) 593 #define VM_L2_STATUS 0x140C 594 #define L2_BUSY (1 << 0) 595 596 #define WAIT_UNTIL 0x8040 597 #define WAIT_2D_IDLE_bit (1 << 14) 598 #define WAIT_3D_IDLE_bit (1 << 15) 599 #define WAIT_2D_IDLECLEAN_bit (1 << 16) 600 #define WAIT_3D_IDLECLEAN_bit (1 << 17) 601 602 /* async DMA */ 603 #define DMA_TILING_CONFIG 0x3ec4 604 #define DMA_CONFIG 0x3e4c 605 606 #define DMA_RB_CNTL 0xd000 607 # define DMA_RB_ENABLE (1 << 0) 608 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 609 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 610 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 611 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 612 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 613 #define DMA_RB_BASE 0xd004 614 #define DMA_RB_RPTR 0xd008 615 #define DMA_RB_WPTR 0xd00c 616 617 #define DMA_RB_RPTR_ADDR_HI 0xd01c 618 #define DMA_RB_RPTR_ADDR_LO 0xd020 619 620 #define DMA_IB_CNTL 0xd024 621 # define DMA_IB_ENABLE (1 << 0) 622 # define DMA_IB_SWAP_ENABLE (1 << 4) 623 #define DMA_IB_RPTR 0xd028 624 #define DMA_CNTL 0xd02c 625 # define TRAP_ENABLE (1 << 0) 626 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 627 # define SEM_WAIT_INT_ENABLE (1 << 2) 628 # define DATA_SWAP_ENABLE (1 << 3) 629 # define FENCE_SWAP_ENABLE (1 << 4) 630 # define CTXEMPTY_INT_ENABLE (1 << 28) 631 #define DMA_STATUS_REG 0xd034 632 # define DMA_IDLE (1 << 0) 633 #define DMA_SEM_INCOMPLETE_TIMER_CNTL 0xd044 634 #define DMA_SEM_WAIT_FAIL_TIMER_CNTL 0xd048 635 #define DMA_MODE 0xd0bc 636 637 /* async DMA packets */ 638 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \ 639 (((t) & 0x1) << 23) | \ 640 (((s) & 0x1) << 22) | \ 641 (((n) & 0xFFFF) << 0)) 642 /* async DMA Packet types */ 643 #define DMA_PACKET_WRITE 0x2 644 #define DMA_PACKET_COPY 0x3 645 #define DMA_PACKET_INDIRECT_BUFFER 0x4 646 #define DMA_PACKET_SEMAPHORE 0x5 647 #define DMA_PACKET_FENCE 0x6 648 #define DMA_PACKET_TRAP 0x7 649 #define DMA_PACKET_CONSTANT_FILL 0xd /* 7xx only */ 650 #define DMA_PACKET_NOP 0xf 651 652 #define IH_RB_CNTL 0x3e00 653 # define IH_RB_ENABLE (1 << 0) 654 # define IH_RB_SIZE(x) ((x) << 1) /* log2 */ 655 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 656 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 657 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 658 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 659 # define IH_WPTR_OVERFLOW_CLEAR (1U << 31) 660 #define IH_RB_BASE 0x3e04 661 #define IH_RB_RPTR 0x3e08 662 #define IH_RB_WPTR 0x3e0c 663 # define RB_OVERFLOW (1 << 0) 664 # define WPTR_OFFSET_MASK 0x3fffc 665 #define IH_RB_WPTR_ADDR_HI 0x3e10 666 #define IH_RB_WPTR_ADDR_LO 0x3e14 667 #define IH_CNTL 0x3e18 668 # define ENABLE_INTR (1 << 0) 669 # define IH_MC_SWAP(x) ((x) << 1) 670 # define IH_MC_SWAP_NONE 0 671 # define IH_MC_SWAP_16BIT 1 672 # define IH_MC_SWAP_32BIT 2 673 # define IH_MC_SWAP_64BIT 3 674 # define RPTR_REARM (1 << 4) 675 # define MC_WRREQ_CREDIT(x) ((x) << 15) 676 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 677 678 #define RLC_CNTL 0x3f00 679 # define RLC_ENABLE (1 << 0) 680 #define RLC_HB_BASE 0x3f10 681 #define RLC_HB_CNTL 0x3f0c 682 #define RLC_HB_RPTR 0x3f20 683 #define RLC_HB_WPTR 0x3f1c 684 #define RLC_HB_WPTR_LSB_ADDR 0x3f14 685 #define RLC_HB_WPTR_MSB_ADDR 0x3f18 686 #define RLC_GPU_CLOCK_COUNT_LSB 0x3f38 687 #define RLC_GPU_CLOCK_COUNT_MSB 0x3f3c 688 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0x3f40 689 #define RLC_MC_CNTL 0x3f44 690 #define RLC_UCODE_CNTL 0x3f48 691 #define RLC_UCODE_ADDR 0x3f2c 692 #define RLC_UCODE_DATA 0x3f30 693 694 /* new for TN */ 695 #define TN_RLC_SAVE_AND_RESTORE_BASE 0x3f10 696 #define TN_RLC_CLEAR_STATE_RESTORE_BASE 0x3f20 697 698 #define SRBM_SOFT_RESET 0xe60 699 # define SOFT_RESET_DMA (1 << 12) 700 # define SOFT_RESET_RLC (1 << 13) 701 # define RV770_SOFT_RESET_DMA (1 << 20) 702 703 #define CP_INT_CNTL 0xc124 704 # define CNTX_BUSY_INT_ENABLE (1 << 19) 705 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 706 # define SCRATCH_INT_ENABLE (1 << 25) 707 # define TIME_STAMP_INT_ENABLE (1 << 26) 708 # define IB2_INT_ENABLE (1 << 29) 709 # define IB1_INT_ENABLE (1 << 30) 710 # define RB_INT_ENABLE (1U << 31) 711 #define CP_INT_STATUS 0xc128 712 # define SCRATCH_INT_STAT (1 << 25) 713 # define TIME_STAMP_INT_STAT (1 << 26) 714 # define IB2_INT_STAT (1 << 29) 715 # define IB1_INT_STAT (1 << 30) 716 # define RB_INT_STAT (1U << 31) 717 718 #define GRBM_INT_CNTL 0x8060 719 # define RDERR_INT_ENABLE (1 << 0) 720 # define WAIT_COUNT_TIMEOUT_INT_ENABLE (1 << 1) 721 # define GUI_IDLE_INT_ENABLE (1 << 19) 722 723 #define INTERRUPT_CNTL 0x5468 724 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 725 # define IH_DUMMY_RD_EN (1 << 1) 726 # define IH_REQ_NONSNOOP_EN (1 << 3) 727 # define GEN_IH_INT_EN (1 << 8) 728 #define INTERRUPT_CNTL2 0x546c 729 730 #define D1MODE_VBLANK_STATUS 0x6534 731 #define D2MODE_VBLANK_STATUS 0x6d34 732 # define DxMODE_VBLANK_OCCURRED (1 << 0) 733 # define DxMODE_VBLANK_ACK (1 << 4) 734 # define DxMODE_VBLANK_STAT (1 << 12) 735 # define DxMODE_VBLANK_INTERRUPT (1 << 16) 736 # define DxMODE_VBLANK_INTERRUPT_TYPE (1 << 17) 737 #define D1MODE_VLINE_STATUS 0x653c 738 #define D2MODE_VLINE_STATUS 0x6d3c 739 # define DxMODE_VLINE_OCCURRED (1 << 0) 740 # define DxMODE_VLINE_ACK (1 << 4) 741 # define DxMODE_VLINE_STAT (1 << 12) 742 # define DxMODE_VLINE_INTERRUPT (1 << 16) 743 # define DxMODE_VLINE_INTERRUPT_TYPE (1 << 17) 744 #define DxMODE_INT_MASK 0x6540 745 # define D1MODE_VBLANK_INT_MASK (1 << 0) 746 # define D1MODE_VLINE_INT_MASK (1 << 4) 747 # define D2MODE_VBLANK_INT_MASK (1 << 8) 748 # define D2MODE_VLINE_INT_MASK (1 << 12) 749 #define DCE3_DISP_INTERRUPT_STATUS 0x7ddc 750 # define DC_HPD1_INTERRUPT (1 << 18) 751 # define DC_HPD2_INTERRUPT (1 << 19) 752 #define DISP_INTERRUPT_STATUS 0x7edc 753 # define LB_D1_VLINE_INTERRUPT (1 << 2) 754 # define LB_D2_VLINE_INTERRUPT (1 << 3) 755 # define LB_D1_VBLANK_INTERRUPT (1 << 4) 756 # define LB_D2_VBLANK_INTERRUPT (1 << 5) 757 # define DACA_AUTODETECT_INTERRUPT (1 << 16) 758 # define DACB_AUTODETECT_INTERRUPT (1 << 17) 759 # define DC_HOT_PLUG_DETECT1_INTERRUPT (1 << 18) 760 # define DC_HOT_PLUG_DETECT2_INTERRUPT (1 << 19) 761 # define DC_I2C_SW_DONE_INTERRUPT (1 << 20) 762 # define DC_I2C_HW_DONE_INTERRUPT (1 << 21) 763 #define DISP_INTERRUPT_STATUS_CONTINUE 0x7ee8 764 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE 0x7de8 765 # define DC_HPD4_INTERRUPT (1 << 14) 766 # define DC_HPD4_RX_INTERRUPT (1 << 15) 767 # define DC_HPD3_INTERRUPT (1 << 28) 768 # define DC_HPD1_RX_INTERRUPT (1 << 29) 769 # define DC_HPD2_RX_INTERRUPT (1 << 30) 770 #define DCE3_DISP_INTERRUPT_STATUS_CONTINUE2 0x7dec 771 # define DC_HPD3_RX_INTERRUPT (1 << 0) 772 # define DIGA_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 1) 773 # define DIGA_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 2) 774 # define DIGB_DP_VID_STREAM_DISABLE_INTERRUPT (1 << 3) 775 # define DIGB_DP_STEER_FIFO_OVERFLOW_INTERRUPT (1 << 4) 776 # define AUX1_SW_DONE_INTERRUPT (1 << 5) 777 # define AUX1_LS_DONE_INTERRUPT (1 << 6) 778 # define AUX2_SW_DONE_INTERRUPT (1 << 7) 779 # define AUX2_LS_DONE_INTERRUPT (1 << 8) 780 # define AUX3_SW_DONE_INTERRUPT (1 << 9) 781 # define AUX3_LS_DONE_INTERRUPT (1 << 10) 782 # define AUX4_SW_DONE_INTERRUPT (1 << 11) 783 # define AUX4_LS_DONE_INTERRUPT (1 << 12) 784 # define DIGA_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 13) 785 # define DIGB_DP_FAST_TRAINING_COMPLETE_INTERRUPT (1 << 14) 786 /* DCE 3.2 */ 787 # define AUX5_SW_DONE_INTERRUPT (1 << 15) 788 # define AUX5_LS_DONE_INTERRUPT (1 << 16) 789 # define AUX6_SW_DONE_INTERRUPT (1 << 17) 790 # define AUX6_LS_DONE_INTERRUPT (1 << 18) 791 # define DC_HPD5_INTERRUPT (1 << 19) 792 # define DC_HPD5_RX_INTERRUPT (1 << 20) 793 # define DC_HPD6_INTERRUPT (1 << 21) 794 # define DC_HPD6_RX_INTERRUPT (1 << 22) 795 796 #define DACA_AUTO_DETECT_CONTROL 0x7828 797 #define DACB_AUTO_DETECT_CONTROL 0x7a28 798 #define DCE3_DACA_AUTO_DETECT_CONTROL 0x7028 799 #define DCE3_DACB_AUTO_DETECT_CONTROL 0x7128 800 # define DACx_AUTODETECT_MODE(x) ((x) << 0) 801 # define DACx_AUTODETECT_MODE_NONE 0 802 # define DACx_AUTODETECT_MODE_CONNECT 1 803 # define DACx_AUTODETECT_MODE_DISCONNECT 2 804 # define DACx_AUTODETECT_FRAME_TIME_COUNTER(x) ((x) << 8) 805 /* bit 18 = R/C, 17 = G/Y, 16 = B/Comp */ 806 # define DACx_AUTODETECT_CHECK_MASK(x) ((x) << 16) 807 808 #define DCE3_DACA_AUTODETECT_INT_CONTROL 0x7038 809 #define DCE3_DACB_AUTODETECT_INT_CONTROL 0x7138 810 #define DACA_AUTODETECT_INT_CONTROL 0x7838 811 #define DACB_AUTODETECT_INT_CONTROL 0x7a38 812 # define DACx_AUTODETECT_ACK (1 << 0) 813 # define DACx_AUTODETECT_INT_ENABLE (1 << 16) 814 815 #define DC_HOT_PLUG_DETECT1_CONTROL 0x7d00 816 #define DC_HOT_PLUG_DETECT2_CONTROL 0x7d10 817 #define DC_HOT_PLUG_DETECT3_CONTROL 0x7d24 818 # define DC_HOT_PLUG_DETECTx_EN (1 << 0) 819 820 #define DC_HOT_PLUG_DETECT1_INT_STATUS 0x7d04 821 #define DC_HOT_PLUG_DETECT2_INT_STATUS 0x7d14 822 #define DC_HOT_PLUG_DETECT3_INT_STATUS 0x7d28 823 # define DC_HOT_PLUG_DETECTx_INT_STATUS (1 << 0) 824 # define DC_HOT_PLUG_DETECTx_SENSE (1 << 1) 825 826 /* DCE 3.0 */ 827 #define DC_HPD1_INT_STATUS 0x7d00 828 #define DC_HPD2_INT_STATUS 0x7d0c 829 #define DC_HPD3_INT_STATUS 0x7d18 830 #define DC_HPD4_INT_STATUS 0x7d24 831 /* DCE 3.2 */ 832 #define DC_HPD5_INT_STATUS 0x7dc0 833 #define DC_HPD6_INT_STATUS 0x7df4 834 # define DC_HPDx_INT_STATUS (1 << 0) 835 # define DC_HPDx_SENSE (1 << 1) 836 # define DC_HPDx_RX_INT_STATUS (1 << 8) 837 838 #define DC_HOT_PLUG_DETECT1_INT_CONTROL 0x7d08 839 #define DC_HOT_PLUG_DETECT2_INT_CONTROL 0x7d18 840 #define DC_HOT_PLUG_DETECT3_INT_CONTROL 0x7d2c 841 # define DC_HOT_PLUG_DETECTx_INT_ACK (1 << 0) 842 # define DC_HOT_PLUG_DETECTx_INT_POLARITY (1 << 8) 843 # define DC_HOT_PLUG_DETECTx_INT_EN (1 << 16) 844 /* DCE 3.0 */ 845 #define DC_HPD1_INT_CONTROL 0x7d04 846 #define DC_HPD2_INT_CONTROL 0x7d10 847 #define DC_HPD3_INT_CONTROL 0x7d1c 848 #define DC_HPD4_INT_CONTROL 0x7d28 849 /* DCE 3.2 */ 850 #define DC_HPD5_INT_CONTROL 0x7dc4 851 #define DC_HPD6_INT_CONTROL 0x7df8 852 # define DC_HPDx_INT_ACK (1 << 0) 853 # define DC_HPDx_INT_POLARITY (1 << 8) 854 # define DC_HPDx_INT_EN (1 << 16) 855 # define DC_HPDx_RX_INT_ACK (1 << 20) 856 # define DC_HPDx_RX_INT_EN (1 << 24) 857 858 /* DCE 3.0 */ 859 #define DC_HPD1_CONTROL 0x7d08 860 #define DC_HPD2_CONTROL 0x7d14 861 #define DC_HPD3_CONTROL 0x7d20 862 #define DC_HPD4_CONTROL 0x7d2c 863 /* DCE 3.2 */ 864 #define DC_HPD5_CONTROL 0x7dc8 865 #define DC_HPD6_CONTROL 0x7dfc 866 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 867 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 868 /* DCE 3.2 */ 869 # define DC_HPDx_EN (1 << 28) 870 871 #define D1GRPH_INTERRUPT_STATUS 0x6158 872 #define D2GRPH_INTERRUPT_STATUS 0x6958 873 # define DxGRPH_PFLIP_INT_OCCURRED (1 << 0) 874 # define DxGRPH_PFLIP_INT_CLEAR (1 << 8) 875 #define D1GRPH_INTERRUPT_CONTROL 0x615c 876 #define D2GRPH_INTERRUPT_CONTROL 0x695c 877 # define DxGRPH_PFLIP_INT_MASK (1 << 0) 878 # define DxGRPH_PFLIP_INT_TYPE (1 << 8) 879 880 /* PCIE link stuff */ 881 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ 882 # define LC_POINT_7_PLUS_EN (1 << 6) 883 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 884 # define LC_LINK_WIDTH_SHIFT 0 885 # define LC_LINK_WIDTH_MASK 0x7 886 # define LC_LINK_WIDTH_X0 0 887 # define LC_LINK_WIDTH_X1 1 888 # define LC_LINK_WIDTH_X2 2 889 # define LC_LINK_WIDTH_X4 3 890 # define LC_LINK_WIDTH_X8 4 891 # define LC_LINK_WIDTH_X16 6 892 # define LC_LINK_WIDTH_RD_SHIFT 4 893 # define LC_LINK_WIDTH_RD_MASK 0x70 894 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 895 # define LC_RECONFIG_NOW (1 << 8) 896 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 897 # define LC_RENEGOTIATE_EN (1 << 10) 898 # define LC_SHORT_RECONFIG_EN (1 << 11) 899 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 900 # define LC_UPCONFIGURE_DIS (1 << 13) 901 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 902 # define LC_GEN2_EN_STRAP (1 << 0) 903 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) 904 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5) 905 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6) 906 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8) 907 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3 908 # define LC_CURRENT_DATA_RATE (1 << 11) 909 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14) 910 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21) 911 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23) 912 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24) 913 #define MM_CFGREGS_CNTL 0x544c 914 # define MM_WR_TO_CFG_EN (1 << 3) 915 #define LINK_CNTL2 0x88 /* F0 */ 916 # define TARGET_LINK_SPEED_MASK (0xf << 0) 917 # define SELECTABLE_DEEMPHASIS (1 << 6) 918 919 /* Audio clocks */ 920 #define DCCG_AUDIO_DTO0_PHASE 0x0514 921 #define DCCG_AUDIO_DTO0_MODULE 0x0518 922 #define DCCG_AUDIO_DTO0_LOAD 0x051c 923 # define DTO_LOAD (1U << 31) 924 #define DCCG_AUDIO_DTO0_CNTL 0x0520 925 926 #define DCCG_AUDIO_DTO1_PHASE 0x0524 927 #define DCCG_AUDIO_DTO1_MODULE 0x0528 928 #define DCCG_AUDIO_DTO1_LOAD 0x052c 929 #define DCCG_AUDIO_DTO1_CNTL 0x0530 930 931 #define DCCG_AUDIO_DTO_SELECT 0x0534 932 933 /* digital blocks */ 934 #define TMDSA_CNTL 0x7880 935 # define TMDSA_HDMI_EN (1 << 2) 936 #define LVTMA_CNTL 0x7a80 937 # define LVTMA_HDMI_EN (1 << 2) 938 #define DDIA_CNTL 0x7200 939 # define DDIA_HDMI_EN (1 << 2) 940 #define DIG0_CNTL 0x75a0 941 # define DIG_MODE(x) (((x) & 7) << 8) 942 # define DIG_MODE_DP 0 943 # define DIG_MODE_LVDS 1 944 # define DIG_MODE_TMDS_DVI 2 945 # define DIG_MODE_TMDS_HDMI 3 946 # define DIG_MODE_SDVO 4 947 #define DIG1_CNTL 0x79a0 948 949 /* rs6xx/rs740 and r6xx share the same HDMI blocks, however, rs6xx has only one 950 * instance of the blocks while r6xx has 2. DCE 3.0 cards are slightly 951 * different due to the new DIG blocks, but also have 2 instances. 952 * DCE 3.0 HDMI blocks are part of each DIG encoder. 953 */ 954 955 /* rs6xx/rs740/r6xx/dce3 */ 956 #define HDMI0_CONTROL 0x7400 957 /* rs6xx/rs740/r6xx */ 958 # define HDMI0_ENABLE (1 << 0) 959 # define HDMI0_STREAM(x) (((x) & 3) << 2) 960 # define HDMI0_STREAM_TMDSA 0 961 # define HDMI0_STREAM_LVTMA 1 962 # define HDMI0_STREAM_DVOA 2 963 # define HDMI0_STREAM_DDIA 3 964 /* rs6xx/r6xx/dce3 */ 965 # define HDMI0_ERROR_ACK (1 << 8) 966 # define HDMI0_ERROR_MASK (1 << 9) 967 #define HDMI0_STATUS 0x7404 968 # define HDMI0_ACTIVE_AVMUTE (1 << 0) 969 # define HDMI0_AUDIO_ENABLE (1 << 4) 970 # define HDMI0_AZ_FORMAT_WTRIG (1 << 28) 971 # define HDMI0_AZ_FORMAT_WTRIG_INT (1 << 29) 972 #define HDMI0_AUDIO_PACKET_CONTROL 0x7408 973 # define HDMI0_AUDIO_SAMPLE_SEND (1 << 0) 974 # define HDMI0_AUDIO_DELAY_EN(x) (((x) & 3) << 4) 975 # define HDMI0_AUDIO_SEND_MAX_PACKETS (1 << 8) 976 # define HDMI0_AUDIO_TEST_EN (1 << 12) 977 # define HDMI0_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16) 978 # define HDMI0_AUDIO_CHANNEL_SWAP (1 << 24) 979 # define HDMI0_60958_CS_UPDATE (1 << 26) 980 # define HDMI0_AZ_FORMAT_WTRIG_MASK (1 << 28) 981 # define HDMI0_AZ_FORMAT_WTRIG_ACK (1 << 29) 982 #define HDMI0_AUDIO_CRC_CONTROL 0x740c 983 # define HDMI0_AUDIO_CRC_EN (1 << 0) 984 #define HDMI0_VBI_PACKET_CONTROL 0x7410 985 # define HDMI0_NULL_SEND (1 << 0) 986 # define HDMI0_GC_SEND (1 << 4) 987 # define HDMI0_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */ 988 #define HDMI0_INFOFRAME_CONTROL0 0x7414 989 # define HDMI0_AVI_INFO_SEND (1 << 0) 990 # define HDMI0_AVI_INFO_CONT (1 << 1) 991 # define HDMI0_AUDIO_INFO_SEND (1 << 4) 992 # define HDMI0_AUDIO_INFO_CONT (1 << 5) 993 # define HDMI0_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */ 994 # define HDMI0_AUDIO_INFO_UPDATE (1 << 7) 995 # define HDMI0_MPEG_INFO_SEND (1 << 8) 996 # define HDMI0_MPEG_INFO_CONT (1 << 9) 997 # define HDMI0_MPEG_INFO_UPDATE (1 << 10) 998 #define HDMI0_INFOFRAME_CONTROL1 0x7418 999 # define HDMI0_AVI_INFO_LINE(x) (((x) & 0x3f) << 0) 1000 # define HDMI0_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8) 1001 # define HDMI0_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16) 1002 #define HDMI0_GENERIC_PACKET_CONTROL 0x741c 1003 # define HDMI0_GENERIC0_SEND (1 << 0) 1004 # define HDMI0_GENERIC0_CONT (1 << 1) 1005 # define HDMI0_GENERIC0_UPDATE (1 << 2) 1006 # define HDMI0_GENERIC1_SEND (1 << 4) 1007 # define HDMI0_GENERIC1_CONT (1 << 5) 1008 # define HDMI0_GENERIC0_LINE(x) (((x) & 0x3f) << 16) 1009 # define HDMI0_GENERIC1_LINE(x) (((x) & 0x3f) << 24) 1010 #define HDMI0_GC 0x7428 1011 # define HDMI0_GC_AVMUTE (1 << 0) 1012 #define HDMI0_AVI_INFO0 0x7454 1013 # define HDMI0_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1014 # define HDMI0_AVI_INFO_S(x) (((x) & 3) << 8) 1015 # define HDMI0_AVI_INFO_B(x) (((x) & 3) << 10) 1016 # define HDMI0_AVI_INFO_A(x) (((x) & 1) << 12) 1017 # define HDMI0_AVI_INFO_Y(x) (((x) & 3) << 13) 1018 # define HDMI0_AVI_INFO_Y_RGB 0 1019 # define HDMI0_AVI_INFO_Y_YCBCR422 1 1020 # define HDMI0_AVI_INFO_Y_YCBCR444 2 1021 # define HDMI0_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8) 1022 # define HDMI0_AVI_INFO_R(x) (((x) & 0xf) << 16) 1023 # define HDMI0_AVI_INFO_M(x) (((x) & 0x3) << 20) 1024 # define HDMI0_AVI_INFO_C(x) (((x) & 0x3) << 22) 1025 # define HDMI0_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16) 1026 # define HDMI0_AVI_INFO_SC(x) (((x) & 0x3) << 24) 1027 # define HDMI0_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24) 1028 #define HDMI0_AVI_INFO1 0x7458 1029 # define HDMI0_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */ 1030 # define HDMI0_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */ 1031 # define HDMI0_AVI_INFO_TOP(x) (((x) & 0xffff) << 16) 1032 #define HDMI0_AVI_INFO2 0x745c 1033 # define HDMI0_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0) 1034 # define HDMI0_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16) 1035 #define HDMI0_AVI_INFO3 0x7460 1036 # define HDMI0_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0) 1037 # define HDMI0_AVI_INFO_VERSION(x) (((x) & 3) << 24) 1038 #define HDMI0_MPEG_INFO0 0x7464 1039 # define HDMI0_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1040 # define HDMI0_MPEG_INFO_MB0(x) (((x) & 0xff) << 8) 1041 # define HDMI0_MPEG_INFO_MB1(x) (((x) & 0xff) << 16) 1042 # define HDMI0_MPEG_INFO_MB2(x) (((x) & 0xff) << 24) 1043 #define HDMI0_MPEG_INFO1 0x7468 1044 # define HDMI0_MPEG_INFO_MB3(x) (((x) & 0xff) << 0) 1045 # define HDMI0_MPEG_INFO_MF(x) (((x) & 3) << 8) 1046 # define HDMI0_MPEG_INFO_FR(x) (((x) & 1) << 12) 1047 #define HDMI0_GENERIC0_HDR 0x746c 1048 #define HDMI0_GENERIC0_0 0x7470 1049 #define HDMI0_GENERIC0_1 0x7474 1050 #define HDMI0_GENERIC0_2 0x7478 1051 #define HDMI0_GENERIC0_3 0x747c 1052 #define HDMI0_GENERIC0_4 0x7480 1053 #define HDMI0_GENERIC0_5 0x7484 1054 #define HDMI0_GENERIC0_6 0x7488 1055 #define HDMI0_GENERIC1_HDR 0x748c 1056 #define HDMI0_GENERIC1_0 0x7490 1057 #define HDMI0_GENERIC1_1 0x7494 1058 #define HDMI0_GENERIC1_2 0x7498 1059 #define HDMI0_GENERIC1_3 0x749c 1060 #define HDMI0_GENERIC1_4 0x74a0 1061 #define HDMI0_GENERIC1_5 0x74a4 1062 #define HDMI0_GENERIC1_6 0x74a8 1063 #define HDMI0_ACR_32_0 0x74ac 1064 # define HDMI0_ACR_CTS_32(x) (((x) & 0xfffff) << 12) 1065 #define HDMI0_ACR_32_1 0x74b0 1066 # define HDMI0_ACR_N_32(x) (((x) & 0xfffff) << 0) 1067 #define HDMI0_ACR_44_0 0x74b4 1068 # define HDMI0_ACR_CTS_44(x) (((x) & 0xfffff) << 12) 1069 #define HDMI0_ACR_44_1 0x74b8 1070 # define HDMI0_ACR_N_44(x) (((x) & 0xfffff) << 0) 1071 #define HDMI0_ACR_48_0 0x74bc 1072 # define HDMI0_ACR_CTS_48(x) (((x) & 0xfffff) << 12) 1073 #define HDMI0_ACR_48_1 0x74c0 1074 # define HDMI0_ACR_N_48(x) (((x) & 0xfffff) << 0) 1075 #define HDMI0_ACR_STATUS_0 0x74c4 1076 #define HDMI0_ACR_STATUS_1 0x74c8 1077 #define HDMI0_AUDIO_INFO0 0x74cc 1078 # define HDMI0_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0) 1079 # define HDMI0_AUDIO_INFO_CC(x) (((x) & 7) << 8) 1080 #define HDMI0_AUDIO_INFO1 0x74d0 1081 # define HDMI0_AUDIO_INFO_CA(x) (((x) & 0xff) << 0) 1082 # define HDMI0_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11) 1083 # define HDMI0_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15) 1084 # define HDMI0_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8) 1085 #define HDMI0_60958_0 0x74d4 1086 # define HDMI0_60958_CS_A(x) (((x) & 1) << 0) 1087 # define HDMI0_60958_CS_B(x) (((x) & 1) << 1) 1088 # define HDMI0_60958_CS_C(x) (((x) & 1) << 2) 1089 # define HDMI0_60958_CS_D(x) (((x) & 3) << 3) 1090 # define HDMI0_60958_CS_MODE(x) (((x) & 3) << 6) 1091 # define HDMI0_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8) 1092 # define HDMI0_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16) 1093 # define HDMI0_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20) 1094 # define HDMI0_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24) 1095 # define HDMI0_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28) 1096 #define HDMI0_60958_1 0x74d8 1097 # define HDMI0_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0) 1098 # define HDMI0_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4) 1099 # define HDMI0_60958_CS_VALID_L(x) (((x) & 1) << 16) 1100 # define HDMI0_60958_CS_VALID_R(x) (((x) & 1) << 18) 1101 # define HDMI0_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20) 1102 #define HDMI0_ACR_PACKET_CONTROL 0x74dc 1103 # define HDMI0_ACR_SEND (1 << 0) 1104 # define HDMI0_ACR_CONT (1 << 1) 1105 # define HDMI0_ACR_SELECT(x) (((x) & 3) << 4) 1106 # define HDMI0_ACR_HW 0 1107 # define HDMI0_ACR_32 1 1108 # define HDMI0_ACR_44 2 1109 # define HDMI0_ACR_48 3 1110 # define HDMI0_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */ 1111 # define HDMI0_ACR_AUTO_SEND (1 << 12) 1112 #define HDMI0_RAMP_CONTROL0 0x74e0 1113 # define HDMI0_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0) 1114 #define HDMI0_RAMP_CONTROL1 0x74e4 1115 # define HDMI0_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0) 1116 #define HDMI0_RAMP_CONTROL2 0x74e8 1117 # define HDMI0_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0) 1118 #define HDMI0_RAMP_CONTROL3 0x74ec 1119 # define HDMI0_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0) 1120 /* HDMI0_60958_2 is r7xx only */ 1121 #define HDMI0_60958_2 0x74f0 1122 # define HDMI0_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0) 1123 # define HDMI0_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4) 1124 # define HDMI0_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8) 1125 # define HDMI0_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12) 1126 # define HDMI0_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16) 1127 # define HDMI0_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20) 1128 /* r6xx only; second instance starts at 0x7700 */ 1129 #define HDMI1_CONTROL 0x7700 1130 #define HDMI1_STATUS 0x7704 1131 #define HDMI1_AUDIO_PACKET_CONTROL 0x7708 1132 /* DCE3; second instance starts at 0x7800 NOT 0x7700 */ 1133 #define DCE3_HDMI1_CONTROL 0x7800 1134 #define DCE3_HDMI1_STATUS 0x7804 1135 #define DCE3_HDMI1_AUDIO_PACKET_CONTROL 0x7808 1136 /* DCE3.2 (for interrupts) */ 1137 #define AFMT_STATUS 0x7600 1138 # define AFMT_AUDIO_ENABLE (1 << 4) 1139 # define AFMT_AZ_FORMAT_WTRIG (1 << 28) 1140 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29) 1141 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30) 1142 #define AFMT_AUDIO_PACKET_CONTROL 0x7604 1143 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0) 1144 # define AFMT_AUDIO_TEST_EN (1 << 12) 1145 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24) 1146 # define AFMT_60958_CS_UPDATE (1 << 26) 1147 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27) 1148 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28) 1149 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29) 1150 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30) 1151 1152 /* 1153 * PM4 1154 */ 1155 #define PACKET_TYPE0 0 1156 #define PACKET_TYPE1 1 1157 #define PACKET_TYPE2 2 1158 #define PACKET_TYPE3 3 1159 1160 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3) 1161 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF) 1162 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2) 1163 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF) 1164 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \ 1165 (((reg) >> 2) & 0xFFFF) | \ 1166 ((n) & 0x3FFF) << 16) 1167 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \ 1168 (((op) & 0xFF) << 8) | \ 1169 ((n) & 0x3FFF) << 16) 1170 1171 /* Packet 3 types */ 1172 #define PACKET3_NOP 0x10 1173 #define PACKET3_INDIRECT_BUFFER_END 0x17 1174 #define PACKET3_SET_PREDICATION 0x20 1175 #define PACKET3_REG_RMW 0x21 1176 #define PACKET3_COND_EXEC 0x22 1177 #define PACKET3_PRED_EXEC 0x23 1178 #define PACKET3_START_3D_CMDBUF 0x24 1179 #define PACKET3_DRAW_INDEX_2 0x27 1180 #define PACKET3_CONTEXT_CONTROL 0x28 1181 #define PACKET3_DRAW_INDEX_IMMD_BE 0x29 1182 #define PACKET3_INDEX_TYPE 0x2A 1183 #define PACKET3_DRAW_INDEX 0x2B 1184 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1185 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1186 #define PACKET3_NUM_INSTANCES 0x2F 1187 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1188 #define PACKET3_INDIRECT_BUFFER_MP 0x38 1189 #define PACKET3_MEM_SEMAPHORE 0x39 1190 # define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12) 1191 # define PACKET3_SEM_SEL_SIGNAL (0x6 << 29) 1192 # define PACKET3_SEM_SEL_WAIT (0x7 << 29) 1193 #define PACKET3_MPEG_INDEX 0x3A 1194 #define PACKET3_COPY_DW 0x3B 1195 #define PACKET3_WAIT_REG_MEM 0x3C 1196 #define PACKET3_MEM_WRITE 0x3D 1197 #define PACKET3_INDIRECT_BUFFER 0x32 1198 #define PACKET3_CP_DMA 0x41 1199 /* 1. header 1200 * 2. SRC_ADDR_LO [31:0] 1201 * 3. CP_SYNC [31] | SRC_ADDR_HI [7:0] 1202 * 4. DST_ADDR_LO [31:0] 1203 * 5. DST_ADDR_HI [7:0] 1204 * 6. COMMAND [29:22] | BYTE_COUNT [20:0] 1205 */ 1206 # define PACKET3_CP_DMA_CP_SYNC (1U << 31) 1207 /* COMMAND */ 1208 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 23) 1209 /* 0 - none 1210 * 1 - 8 in 16 1211 * 2 - 8 in 32 1212 * 3 - 8 in 64 1213 */ 1214 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1215 /* 0 - none 1216 * 1 - 8 in 16 1217 * 2 - 8 in 32 1218 * 3 - 8 in 64 1219 */ 1220 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1221 /* 0 - memory 1222 * 1 - register 1223 */ 1224 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1225 /* 0 - memory 1226 * 1 - register 1227 */ 1228 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1229 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1230 #define PACKET3_SURFACE_SYNC 0x43 1231 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1232 # define PACKET3_TC_ACTION_ENA (1 << 23) 1233 # define PACKET3_VC_ACTION_ENA (1 << 24) 1234 # define PACKET3_CB_ACTION_ENA (1 << 25) 1235 # define PACKET3_DB_ACTION_ENA (1 << 26) 1236 # define PACKET3_SH_ACTION_ENA (1 << 27) 1237 # define PACKET3_SMX_ACTION_ENA (1 << 28) 1238 #define PACKET3_ME_INITIALIZE 0x44 1239 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1240 #define PACKET3_COND_WRITE 0x45 1241 #define PACKET3_EVENT_WRITE 0x46 1242 #define EVENT_TYPE(x) ((x) << 0) 1243 #define EVENT_INDEX(x) ((x) << 8) 1244 /* 0 - any non-TS event 1245 * 1 - ZPASS_DONE 1246 * 2 - SAMPLE_PIPELINESTAT 1247 * 3 - SAMPLE_STREAMOUTSTAT* 1248 * 4 - *S_PARTIAL_FLUSH 1249 * 5 - TS events 1250 */ 1251 #define PACKET3_EVENT_WRITE_EOP 0x47 1252 #define DATA_SEL(x) ((x) << 29) 1253 /* 0 - discard 1254 * 1 - send low 32bit data 1255 * 2 - send 64bit data 1256 * 3 - send 64bit counter value 1257 */ 1258 #define INT_SEL(x) ((x) << 24) 1259 /* 0 - none 1260 * 1 - interrupt only (DATA_SEL = 0) 1261 * 2 - interrupt when data write is confirmed 1262 */ 1263 #define PACKET3_ONE_REG_WRITE 0x57 1264 #define PACKET3_SET_CONFIG_REG 0x68 1265 #define PACKET3_SET_CONFIG_REG_OFFSET 0x00008000 1266 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00 1267 #define PACKET3_SET_CONTEXT_REG 0x69 1268 #define PACKET3_SET_CONTEXT_REG_OFFSET 0x00028000 1269 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1270 #define PACKET3_SET_ALU_CONST 0x6A 1271 #define PACKET3_SET_ALU_CONST_OFFSET 0x00030000 1272 #define PACKET3_SET_ALU_CONST_END 0x00032000 1273 #define PACKET3_SET_BOOL_CONST 0x6B 1274 #define PACKET3_SET_BOOL_CONST_OFFSET 0x0003e380 1275 #define PACKET3_SET_BOOL_CONST_END 0x00040000 1276 #define PACKET3_SET_LOOP_CONST 0x6C 1277 #define PACKET3_SET_LOOP_CONST_OFFSET 0x0003e200 1278 #define PACKET3_SET_LOOP_CONST_END 0x0003e380 1279 #define PACKET3_SET_RESOURCE 0x6D 1280 #define PACKET3_SET_RESOURCE_OFFSET 0x00038000 1281 #define PACKET3_SET_RESOURCE_END 0x0003c000 1282 #define PACKET3_SET_SAMPLER 0x6E 1283 #define PACKET3_SET_SAMPLER_OFFSET 0x0003c000 1284 #define PACKET3_SET_SAMPLER_END 0x0003cff0 1285 #define PACKET3_SET_CTL_CONST 0x6F 1286 #define PACKET3_SET_CTL_CONST_OFFSET 0x0003cff0 1287 #define PACKET3_SET_CTL_CONST_END 0x0003e200 1288 #define PACKET3_STRMOUT_BASE_UPDATE 0x72 /* r7xx */ 1289 #define PACKET3_SURFACE_BASE_UPDATE 0x73 1290 1291 1292 #define R_008020_GRBM_SOFT_RESET 0x8020 1293 #define S_008020_SOFT_RESET_CP(x) (((x) & 1) << 0) 1294 #define S_008020_SOFT_RESET_CB(x) (((x) & 1) << 1) 1295 #define S_008020_SOFT_RESET_CR(x) (((x) & 1) << 2) 1296 #define S_008020_SOFT_RESET_DB(x) (((x) & 1) << 3) 1297 #define S_008020_SOFT_RESET_PA(x) (((x) & 1) << 5) 1298 #define S_008020_SOFT_RESET_SC(x) (((x) & 1) << 6) 1299 #define S_008020_SOFT_RESET_SMX(x) (((x) & 1) << 7) 1300 #define S_008020_SOFT_RESET_SPI(x) (((x) & 1) << 8) 1301 #define S_008020_SOFT_RESET_SH(x) (((x) & 1) << 9) 1302 #define S_008020_SOFT_RESET_SX(x) (((x) & 1) << 10) 1303 #define S_008020_SOFT_RESET_TC(x) (((x) & 1) << 11) 1304 #define S_008020_SOFT_RESET_TA(x) (((x) & 1) << 12) 1305 #define S_008020_SOFT_RESET_VC(x) (((x) & 1) << 13) 1306 #define S_008020_SOFT_RESET_VGT(x) (((x) & 1) << 14) 1307 #define R_008010_GRBM_STATUS 0x8010 1308 #define S_008010_CMDFIFO_AVAIL(x) (((x) & 0x1F) << 0) 1309 #define S_008010_CP_RQ_PENDING(x) (((x) & 1) << 6) 1310 #define S_008010_CF_RQ_PENDING(x) (((x) & 1) << 7) 1311 #define S_008010_PF_RQ_PENDING(x) (((x) & 1) << 8) 1312 #define S_008010_GRBM_EE_BUSY(x) (((x) & 1) << 10) 1313 #define S_008010_VC_BUSY(x) (((x) & 1) << 11) 1314 #define S_008010_DB03_CLEAN(x) (((x) & 1) << 12) 1315 #define S_008010_CB03_CLEAN(x) (((x) & 1) << 13) 1316 #define S_008010_VGT_BUSY_NO_DMA(x) (((x) & 1) << 16) 1317 #define S_008010_VGT_BUSY(x) (((x) & 1) << 17) 1318 #define S_008010_TA03_BUSY(x) (((x) & 1) << 18) 1319 #define S_008010_TC_BUSY(x) (((x) & 1) << 19) 1320 #define S_008010_SX_BUSY(x) (((x) & 1) << 20) 1321 #define S_008010_SH_BUSY(x) (((x) & 1) << 21) 1322 #define S_008010_SPI03_BUSY(x) (((x) & 1) << 22) 1323 #define S_008010_SMX_BUSY(x) (((x) & 1) << 23) 1324 #define S_008010_SC_BUSY(x) (((x) & 1) << 24) 1325 #define S_008010_PA_BUSY(x) (((x) & 1) << 25) 1326 #define S_008010_DB03_BUSY(x) (((x) & 1) << 26) 1327 #define S_008010_CR_BUSY(x) (((x) & 1) << 27) 1328 #define S_008010_CP_COHERENCY_BUSY(x) (((x) & 1) << 28) 1329 #define S_008010_CP_BUSY(x) (((x) & 1) << 29) 1330 #define S_008010_CB03_BUSY(x) (((x) & 1) << 30) 1331 #define S_008010_GUI_ACTIVE(x) (((x) & 1) << 31) 1332 #define G_008010_CMDFIFO_AVAIL(x) (((x) >> 0) & 0x1F) 1333 #define G_008010_CP_RQ_PENDING(x) (((x) >> 6) & 1) 1334 #define G_008010_CF_RQ_PENDING(x) (((x) >> 7) & 1) 1335 #define G_008010_PF_RQ_PENDING(x) (((x) >> 8) & 1) 1336 #define G_008010_GRBM_EE_BUSY(x) (((x) >> 10) & 1) 1337 #define G_008010_VC_BUSY(x) (((x) >> 11) & 1) 1338 #define G_008010_DB03_CLEAN(x) (((x) >> 12) & 1) 1339 #define G_008010_CB03_CLEAN(x) (((x) >> 13) & 1) 1340 #define G_008010_VGT_BUSY_NO_DMA(x) (((x) >> 16) & 1) 1341 #define G_008010_VGT_BUSY(x) (((x) >> 17) & 1) 1342 #define G_008010_TA03_BUSY(x) (((x) >> 18) & 1) 1343 #define G_008010_TC_BUSY(x) (((x) >> 19) & 1) 1344 #define G_008010_SX_BUSY(x) (((x) >> 20) & 1) 1345 #define G_008010_SH_BUSY(x) (((x) >> 21) & 1) 1346 #define G_008010_SPI03_BUSY(x) (((x) >> 22) & 1) 1347 #define G_008010_SMX_BUSY(x) (((x) >> 23) & 1) 1348 #define G_008010_SC_BUSY(x) (((x) >> 24) & 1) 1349 #define G_008010_PA_BUSY(x) (((x) >> 25) & 1) 1350 #define G_008010_DB03_BUSY(x) (((x) >> 26) & 1) 1351 #define G_008010_CR_BUSY(x) (((x) >> 27) & 1) 1352 #define G_008010_CP_COHERENCY_BUSY(x) (((x) >> 28) & 1) 1353 #define G_008010_CP_BUSY(x) (((x) >> 29) & 1) 1354 #define G_008010_CB03_BUSY(x) (((x) >> 30) & 1) 1355 #define G_008010_GUI_ACTIVE(x) (((x) >> 31) & 1) 1356 #define R_008014_GRBM_STATUS2 0x8014 1357 #define S_008014_CR_CLEAN(x) (((x) & 1) << 0) 1358 #define S_008014_SMX_CLEAN(x) (((x) & 1) << 1) 1359 #define S_008014_SPI0_BUSY(x) (((x) & 1) << 8) 1360 #define S_008014_SPI1_BUSY(x) (((x) & 1) << 9) 1361 #define S_008014_SPI2_BUSY(x) (((x) & 1) << 10) 1362 #define S_008014_SPI3_BUSY(x) (((x) & 1) << 11) 1363 #define S_008014_TA0_BUSY(x) (((x) & 1) << 12) 1364 #define S_008014_TA1_BUSY(x) (((x) & 1) << 13) 1365 #define S_008014_TA2_BUSY(x) (((x) & 1) << 14) 1366 #define S_008014_TA3_BUSY(x) (((x) & 1) << 15) 1367 #define S_008014_DB0_BUSY(x) (((x) & 1) << 16) 1368 #define S_008014_DB1_BUSY(x) (((x) & 1) << 17) 1369 #define S_008014_DB2_BUSY(x) (((x) & 1) << 18) 1370 #define S_008014_DB3_BUSY(x) (((x) & 1) << 19) 1371 #define S_008014_CB0_BUSY(x) (((x) & 1) << 20) 1372 #define S_008014_CB1_BUSY(x) (((x) & 1) << 21) 1373 #define S_008014_CB2_BUSY(x) (((x) & 1) << 22) 1374 #define S_008014_CB3_BUSY(x) (((x) & 1) << 23) 1375 #define G_008014_CR_CLEAN(x) (((x) >> 0) & 1) 1376 #define G_008014_SMX_CLEAN(x) (((x) >> 1) & 1) 1377 #define G_008014_SPI0_BUSY(x) (((x) >> 8) & 1) 1378 #define G_008014_SPI1_BUSY(x) (((x) >> 9) & 1) 1379 #define G_008014_SPI2_BUSY(x) (((x) >> 10) & 1) 1380 #define G_008014_SPI3_BUSY(x) (((x) >> 11) & 1) 1381 #define G_008014_TA0_BUSY(x) (((x) >> 12) & 1) 1382 #define G_008014_TA1_BUSY(x) (((x) >> 13) & 1) 1383 #define G_008014_TA2_BUSY(x) (((x) >> 14) & 1) 1384 #define G_008014_TA3_BUSY(x) (((x) >> 15) & 1) 1385 #define G_008014_DB0_BUSY(x) (((x) >> 16) & 1) 1386 #define G_008014_DB1_BUSY(x) (((x) >> 17) & 1) 1387 #define G_008014_DB2_BUSY(x) (((x) >> 18) & 1) 1388 #define G_008014_DB3_BUSY(x) (((x) >> 19) & 1) 1389 #define G_008014_CB0_BUSY(x) (((x) >> 20) & 1) 1390 #define G_008014_CB1_BUSY(x) (((x) >> 21) & 1) 1391 #define G_008014_CB2_BUSY(x) (((x) >> 22) & 1) 1392 #define G_008014_CB3_BUSY(x) (((x) >> 23) & 1) 1393 #define R_000E50_SRBM_STATUS 0x0E50 1394 #define G_000E50_RLC_RQ_PENDING(x) (((x) >> 3) & 1) 1395 #define G_000E50_RCU_RQ_PENDING(x) (((x) >> 4) & 1) 1396 #define G_000E50_GRBM_RQ_PENDING(x) (((x) >> 5) & 1) 1397 #define G_000E50_HI_RQ_PENDING(x) (((x) >> 6) & 1) 1398 #define G_000E50_IO_EXTERN_SIGNAL(x) (((x) >> 7) & 1) 1399 #define G_000E50_VMC_BUSY(x) (((x) >> 8) & 1) 1400 #define G_000E50_MCB_BUSY(x) (((x) >> 9) & 1) 1401 #define G_000E50_MCDZ_BUSY(x) (((x) >> 10) & 1) 1402 #define G_000E50_MCDY_BUSY(x) (((x) >> 11) & 1) 1403 #define G_000E50_MCDX_BUSY(x) (((x) >> 12) & 1) 1404 #define G_000E50_MCDW_BUSY(x) (((x) >> 13) & 1) 1405 #define G_000E50_SEM_BUSY(x) (((x) >> 14) & 1) 1406 #define G_000E50_RLC_BUSY(x) (((x) >> 15) & 1) 1407 #define G_000E50_BIF_BUSY(x) (((x) >> 29) & 1) 1408 #define R_000E60_SRBM_SOFT_RESET 0x0E60 1409 #define S_000E60_SOFT_RESET_BIF(x) (((x) & 1) << 1) 1410 #define S_000E60_SOFT_RESET_CG(x) (((x) & 1) << 2) 1411 #define S_000E60_SOFT_RESET_CMC(x) (((x) & 1) << 3) 1412 #define S_000E60_SOFT_RESET_CSC(x) (((x) & 1) << 4) 1413 #define S_000E60_SOFT_RESET_DC(x) (((x) & 1) << 5) 1414 #define S_000E60_SOFT_RESET_GRBM(x) (((x) & 1) << 8) 1415 #define S_000E60_SOFT_RESET_HDP(x) (((x) & 1) << 9) 1416 #define S_000E60_SOFT_RESET_IH(x) (((x) & 1) << 10) 1417 #define S_000E60_SOFT_RESET_MC(x) (((x) & 1) << 11) 1418 #define S_000E60_SOFT_RESET_RLC(x) (((x) & 1) << 13) 1419 #define S_000E60_SOFT_RESET_ROM(x) (((x) & 1) << 14) 1420 #define S_000E60_SOFT_RESET_SEM(x) (((x) & 1) << 15) 1421 #define S_000E60_SOFT_RESET_TSC(x) (((x) & 1) << 16) 1422 #define S_000E60_SOFT_RESET_VMC(x) (((x) & 1) << 17) 1423 1424 #define R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 1425 1426 #define R_028C04_PA_SC_AA_CONFIG 0x028C04 1427 #define S_028C04_MSAA_NUM_SAMPLES(x) (((x) & 0x3) << 0) 1428 #define G_028C04_MSAA_NUM_SAMPLES(x) (((x) >> 0) & 0x3) 1429 #define C_028C04_MSAA_NUM_SAMPLES 0xFFFFFFFC 1430 #define S_028C04_AA_MASK_CENTROID_DTMN(x) (((x) & 0x1) << 4) 1431 #define G_028C04_AA_MASK_CENTROID_DTMN(x) (((x) >> 4) & 0x1) 1432 #define C_028C04_AA_MASK_CENTROID_DTMN 0xFFFFFFEF 1433 #define S_028C04_MAX_SAMPLE_DIST(x) (((x) & 0xF) << 13) 1434 #define G_028C04_MAX_SAMPLE_DIST(x) (((x) >> 13) & 0xF) 1435 #define C_028C04_MAX_SAMPLE_DIST 0xFFFE1FFF 1436 #define R_0280E0_CB_COLOR0_FRAG 0x0280E0 1437 #define S_0280E0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1438 #define G_0280E0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1439 #define C_0280E0_BASE_256B 0x00000000 1440 #define R_0280E4_CB_COLOR1_FRAG 0x0280E4 1441 #define R_0280E8_CB_COLOR2_FRAG 0x0280E8 1442 #define R_0280EC_CB_COLOR3_FRAG 0x0280EC 1443 #define R_0280F0_CB_COLOR4_FRAG 0x0280F0 1444 #define R_0280F4_CB_COLOR5_FRAG 0x0280F4 1445 #define R_0280F8_CB_COLOR6_FRAG 0x0280F8 1446 #define R_0280FC_CB_COLOR7_FRAG 0x0280FC 1447 #define R_0280C0_CB_COLOR0_TILE 0x0280C0 1448 #define S_0280C0_BASE_256B(x) (((x) & 0xFFFFFFFF) << 0) 1449 #define G_0280C0_BASE_256B(x) (((x) >> 0) & 0xFFFFFFFF) 1450 #define C_0280C0_BASE_256B 0x00000000 1451 #define R_0280C4_CB_COLOR1_TILE 0x0280C4 1452 #define R_0280C8_CB_COLOR2_TILE 0x0280C8 1453 #define R_0280CC_CB_COLOR3_TILE 0x0280CC 1454 #define R_0280D0_CB_COLOR4_TILE 0x0280D0 1455 #define R_0280D4_CB_COLOR5_TILE 0x0280D4 1456 #define R_0280D8_CB_COLOR6_TILE 0x0280D8 1457 #define R_0280DC_CB_COLOR7_TILE 0x0280DC 1458 #define R_0280A0_CB_COLOR0_INFO 0x0280A0 1459 #define S_0280A0_ENDIAN(x) (((x) & 0x3) << 0) 1460 #define G_0280A0_ENDIAN(x) (((x) >> 0) & 0x3) 1461 #define C_0280A0_ENDIAN 0xFFFFFFFC 1462 #define S_0280A0_FORMAT(x) (((x) & 0x3F) << 2) 1463 #define G_0280A0_FORMAT(x) (((x) >> 2) & 0x3F) 1464 #define C_0280A0_FORMAT 0xFFFFFF03 1465 #define V_0280A0_COLOR_INVALID 0x00000000 1466 #define V_0280A0_COLOR_8 0x00000001 1467 #define V_0280A0_COLOR_4_4 0x00000002 1468 #define V_0280A0_COLOR_3_3_2 0x00000003 1469 #define V_0280A0_COLOR_16 0x00000005 1470 #define V_0280A0_COLOR_16_FLOAT 0x00000006 1471 #define V_0280A0_COLOR_8_8 0x00000007 1472 #define V_0280A0_COLOR_5_6_5 0x00000008 1473 #define V_0280A0_COLOR_6_5_5 0x00000009 1474 #define V_0280A0_COLOR_1_5_5_5 0x0000000A 1475 #define V_0280A0_COLOR_4_4_4_4 0x0000000B 1476 #define V_0280A0_COLOR_5_5_5_1 0x0000000C 1477 #define V_0280A0_COLOR_32 0x0000000D 1478 #define V_0280A0_COLOR_32_FLOAT 0x0000000E 1479 #define V_0280A0_COLOR_16_16 0x0000000F 1480 #define V_0280A0_COLOR_16_16_FLOAT 0x00000010 1481 #define V_0280A0_COLOR_8_24 0x00000011 1482 #define V_0280A0_COLOR_8_24_FLOAT 0x00000012 1483 #define V_0280A0_COLOR_24_8 0x00000013 1484 #define V_0280A0_COLOR_24_8_FLOAT 0x00000014 1485 #define V_0280A0_COLOR_10_11_11 0x00000015 1486 #define V_0280A0_COLOR_10_11_11_FLOAT 0x00000016 1487 #define V_0280A0_COLOR_11_11_10 0x00000017 1488 #define V_0280A0_COLOR_11_11_10_FLOAT 0x00000018 1489 #define V_0280A0_COLOR_2_10_10_10 0x00000019 1490 #define V_0280A0_COLOR_8_8_8_8 0x0000001A 1491 #define V_0280A0_COLOR_10_10_10_2 0x0000001B 1492 #define V_0280A0_COLOR_X24_8_32_FLOAT 0x0000001C 1493 #define V_0280A0_COLOR_32_32 0x0000001D 1494 #define V_0280A0_COLOR_32_32_FLOAT 0x0000001E 1495 #define V_0280A0_COLOR_16_16_16_16 0x0000001F 1496 #define V_0280A0_COLOR_16_16_16_16_FLOAT 0x00000020 1497 #define V_0280A0_COLOR_32_32_32_32 0x00000022 1498 #define V_0280A0_COLOR_32_32_32_32_FLOAT 0x00000023 1499 #define S_0280A0_ARRAY_MODE(x) (((x) & 0xF) << 8) 1500 #define G_0280A0_ARRAY_MODE(x) (((x) >> 8) & 0xF) 1501 #define C_0280A0_ARRAY_MODE 0xFFFFF0FF 1502 #define V_0280A0_ARRAY_LINEAR_GENERAL 0x00000000 1503 #define V_0280A0_ARRAY_LINEAR_ALIGNED 0x00000001 1504 #define V_0280A0_ARRAY_1D_TILED_THIN1 0x00000002 1505 #define V_0280A0_ARRAY_2D_TILED_THIN1 0x00000004 1506 #define S_0280A0_NUMBER_TYPE(x) (((x) & 0x7) << 12) 1507 #define G_0280A0_NUMBER_TYPE(x) (((x) >> 12) & 0x7) 1508 #define C_0280A0_NUMBER_TYPE 0xFFFF8FFF 1509 #define S_0280A0_READ_SIZE(x) (((x) & 0x1) << 15) 1510 #define G_0280A0_READ_SIZE(x) (((x) >> 15) & 0x1) 1511 #define C_0280A0_READ_SIZE 0xFFFF7FFF 1512 #define S_0280A0_COMP_SWAP(x) (((x) & 0x3) << 16) 1513 #define G_0280A0_COMP_SWAP(x) (((x) >> 16) & 0x3) 1514 #define C_0280A0_COMP_SWAP 0xFFFCFFFF 1515 #define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1516 #define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1517 #define C_0280A0_TILE_MODE 0xFFF3FFFF 1518 #define V_0280A0_TILE_DISABLE 0 1519 #define V_0280A0_CLEAR_ENABLE 1 1520 #define V_0280A0_FRAG_ENABLE 2 1521 #define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1522 #define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1523 #define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1524 #define S_0280A0_CLEAR_COLOR(x) (((x) & 0x1) << 21) 1525 #define G_0280A0_CLEAR_COLOR(x) (((x) >> 21) & 0x1) 1526 #define C_0280A0_CLEAR_COLOR 0xFFDFFFFF 1527 #define S_0280A0_BLEND_BYPASS(x) (((x) & 0x1) << 22) 1528 #define G_0280A0_BLEND_BYPASS(x) (((x) >> 22) & 0x1) 1529 #define C_0280A0_BLEND_BYPASS 0xFFBFFFFF 1530 #define S_0280A0_BLEND_FLOAT32(x) (((x) & 0x1) << 23) 1531 #define G_0280A0_BLEND_FLOAT32(x) (((x) >> 23) & 0x1) 1532 #define C_0280A0_BLEND_FLOAT32 0xFF7FFFFF 1533 #define S_0280A0_SIMPLE_FLOAT(x) (((x) & 0x1) << 24) 1534 #define G_0280A0_SIMPLE_FLOAT(x) (((x) >> 24) & 0x1) 1535 #define C_0280A0_SIMPLE_FLOAT 0xFEFFFFFF 1536 #define S_0280A0_ROUND_MODE(x) (((x) & 0x1) << 25) 1537 #define G_0280A0_ROUND_MODE(x) (((x) >> 25) & 0x1) 1538 #define C_0280A0_ROUND_MODE 0xFDFFFFFF 1539 #define S_0280A0_TILE_COMPACT(x) (((x) & 0x1) << 26) 1540 #define G_0280A0_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1541 #define C_0280A0_TILE_COMPACT 0xFBFFFFFF 1542 #define S_0280A0_SOURCE_FORMAT(x) (((x) & 0x1) << 27) 1543 #define G_0280A0_SOURCE_FORMAT(x) (((x) >> 27) & 0x1) 1544 #define C_0280A0_SOURCE_FORMAT 0xF7FFFFFF 1545 #define R_0280A4_CB_COLOR1_INFO 0x0280A4 1546 #define R_0280A8_CB_COLOR2_INFO 0x0280A8 1547 #define R_0280AC_CB_COLOR3_INFO 0x0280AC 1548 #define R_0280B0_CB_COLOR4_INFO 0x0280B0 1549 #define R_0280B4_CB_COLOR5_INFO 0x0280B4 1550 #define R_0280B8_CB_COLOR6_INFO 0x0280B8 1551 #define R_0280BC_CB_COLOR7_INFO 0x0280BC 1552 #define R_028060_CB_COLOR0_SIZE 0x028060 1553 #define S_028060_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1554 #define G_028060_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1555 #define C_028060_PITCH_TILE_MAX 0xFFFFFC00 1556 #define S_028060_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1557 #define G_028060_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1558 #define C_028060_SLICE_TILE_MAX 0xC00003FF 1559 #define R_028064_CB_COLOR1_SIZE 0x028064 1560 #define R_028068_CB_COLOR2_SIZE 0x028068 1561 #define R_02806C_CB_COLOR3_SIZE 0x02806C 1562 #define R_028070_CB_COLOR4_SIZE 0x028070 1563 #define R_028074_CB_COLOR5_SIZE 0x028074 1564 #define R_028078_CB_COLOR6_SIZE 0x028078 1565 #define R_02807C_CB_COLOR7_SIZE 0x02807C 1566 #define R_028238_CB_TARGET_MASK 0x028238 1567 #define S_028238_TARGET0_ENABLE(x) (((x) & 0xF) << 0) 1568 #define G_028238_TARGET0_ENABLE(x) (((x) >> 0) & 0xF) 1569 #define C_028238_TARGET0_ENABLE 0xFFFFFFF0 1570 #define S_028238_TARGET1_ENABLE(x) (((x) & 0xF) << 4) 1571 #define G_028238_TARGET1_ENABLE(x) (((x) >> 4) & 0xF) 1572 #define C_028238_TARGET1_ENABLE 0xFFFFFF0F 1573 #define S_028238_TARGET2_ENABLE(x) (((x) & 0xF) << 8) 1574 #define G_028238_TARGET2_ENABLE(x) (((x) >> 8) & 0xF) 1575 #define C_028238_TARGET2_ENABLE 0xFFFFF0FF 1576 #define S_028238_TARGET3_ENABLE(x) (((x) & 0xF) << 12) 1577 #define G_028238_TARGET3_ENABLE(x) (((x) >> 12) & 0xF) 1578 #define C_028238_TARGET3_ENABLE 0xFFFF0FFF 1579 #define S_028238_TARGET4_ENABLE(x) (((x) & 0xF) << 16) 1580 #define G_028238_TARGET4_ENABLE(x) (((x) >> 16) & 0xF) 1581 #define C_028238_TARGET4_ENABLE 0xFFF0FFFF 1582 #define S_028238_TARGET5_ENABLE(x) (((x) & 0xF) << 20) 1583 #define G_028238_TARGET5_ENABLE(x) (((x) >> 20) & 0xF) 1584 #define C_028238_TARGET5_ENABLE 0xFF0FFFFF 1585 #define S_028238_TARGET6_ENABLE(x) (((x) & 0xF) << 24) 1586 #define G_028238_TARGET6_ENABLE(x) (((x) >> 24) & 0xF) 1587 #define C_028238_TARGET6_ENABLE 0xF0FFFFFF 1588 #define S_028238_TARGET7_ENABLE(x) (((x) & 0xF) << 28) 1589 #define G_028238_TARGET7_ENABLE(x) (((x) >> 28) & 0xF) 1590 #define C_028238_TARGET7_ENABLE 0x0FFFFFFF 1591 #define R_02823C_CB_SHADER_MASK 0x02823C 1592 #define S_02823C_OUTPUT0_ENABLE(x) (((x) & 0xF) << 0) 1593 #define G_02823C_OUTPUT0_ENABLE(x) (((x) >> 0) & 0xF) 1594 #define C_02823C_OUTPUT0_ENABLE 0xFFFFFFF0 1595 #define S_02823C_OUTPUT1_ENABLE(x) (((x) & 0xF) << 4) 1596 #define G_02823C_OUTPUT1_ENABLE(x) (((x) >> 4) & 0xF) 1597 #define C_02823C_OUTPUT1_ENABLE 0xFFFFFF0F 1598 #define S_02823C_OUTPUT2_ENABLE(x) (((x) & 0xF) << 8) 1599 #define G_02823C_OUTPUT2_ENABLE(x) (((x) >> 8) & 0xF) 1600 #define C_02823C_OUTPUT2_ENABLE 0xFFFFF0FF 1601 #define S_02823C_OUTPUT3_ENABLE(x) (((x) & 0xF) << 12) 1602 #define G_02823C_OUTPUT3_ENABLE(x) (((x) >> 12) & 0xF) 1603 #define C_02823C_OUTPUT3_ENABLE 0xFFFF0FFF 1604 #define S_02823C_OUTPUT4_ENABLE(x) (((x) & 0xF) << 16) 1605 #define G_02823C_OUTPUT4_ENABLE(x) (((x) >> 16) & 0xF) 1606 #define C_02823C_OUTPUT4_ENABLE 0xFFF0FFFF 1607 #define S_02823C_OUTPUT5_ENABLE(x) (((x) & 0xF) << 20) 1608 #define G_02823C_OUTPUT5_ENABLE(x) (((x) >> 20) & 0xF) 1609 #define C_02823C_OUTPUT5_ENABLE 0xFF0FFFFF 1610 #define S_02823C_OUTPUT6_ENABLE(x) (((x) & 0xF) << 24) 1611 #define G_02823C_OUTPUT6_ENABLE(x) (((x) >> 24) & 0xF) 1612 #define C_02823C_OUTPUT6_ENABLE 0xF0FFFFFF 1613 #define S_02823C_OUTPUT7_ENABLE(x) (((x) & 0xF) << 28) 1614 #define G_02823C_OUTPUT7_ENABLE(x) (((x) >> 28) & 0xF) 1615 #define C_02823C_OUTPUT7_ENABLE 0x0FFFFFFF 1616 #define R_028AB0_VGT_STRMOUT_EN 0x028AB0 1617 #define S_028AB0_STREAMOUT(x) (((x) & 0x1) << 0) 1618 #define G_028AB0_STREAMOUT(x) (((x) >> 0) & 0x1) 1619 #define C_028AB0_STREAMOUT 0xFFFFFFFE 1620 #define R_028B20_VGT_STRMOUT_BUFFER_EN 0x028B20 1621 #define S_028B20_BUFFER_0_EN(x) (((x) & 0x1) << 0) 1622 #define G_028B20_BUFFER_0_EN(x) (((x) >> 0) & 0x1) 1623 #define C_028B20_BUFFER_0_EN 0xFFFFFFFE 1624 #define S_028B20_BUFFER_1_EN(x) (((x) & 0x1) << 1) 1625 #define G_028B20_BUFFER_1_EN(x) (((x) >> 1) & 0x1) 1626 #define C_028B20_BUFFER_1_EN 0xFFFFFFFD 1627 #define S_028B20_BUFFER_2_EN(x) (((x) & 0x1) << 2) 1628 #define G_028B20_BUFFER_2_EN(x) (((x) >> 2) & 0x1) 1629 #define C_028B20_BUFFER_2_EN 0xFFFFFFFB 1630 #define S_028B20_BUFFER_3_EN(x) (((x) & 0x1) << 3) 1631 #define G_028B20_BUFFER_3_EN(x) (((x) >> 3) & 0x1) 1632 #define C_028B20_BUFFER_3_EN 0xFFFFFFF7 1633 #define S_028B20_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1634 #define G_028B20_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1635 #define C_028B20_SIZE 0x00000000 1636 #define R_038000_SQ_TEX_RESOURCE_WORD0_0 0x038000 1637 #define S_038000_DIM(x) (((x) & 0x7) << 0) 1638 #define G_038000_DIM(x) (((x) >> 0) & 0x7) 1639 #define C_038000_DIM 0xFFFFFFF8 1640 #define V_038000_SQ_TEX_DIM_1D 0x00000000 1641 #define V_038000_SQ_TEX_DIM_2D 0x00000001 1642 #define V_038000_SQ_TEX_DIM_3D 0x00000002 1643 #define V_038000_SQ_TEX_DIM_CUBEMAP 0x00000003 1644 #define V_038000_SQ_TEX_DIM_1D_ARRAY 0x00000004 1645 #define V_038000_SQ_TEX_DIM_2D_ARRAY 0x00000005 1646 #define V_038000_SQ_TEX_DIM_2D_MSAA 0x00000006 1647 #define V_038000_SQ_TEX_DIM_2D_ARRAY_MSAA 0x00000007 1648 #define S_038000_TILE_MODE(x) (((x) & 0xF) << 3) 1649 #define G_038000_TILE_MODE(x) (((x) >> 3) & 0xF) 1650 #define C_038000_TILE_MODE 0xFFFFFF87 1651 #define V_038000_ARRAY_LINEAR_GENERAL 0x00000000 1652 #define V_038000_ARRAY_LINEAR_ALIGNED 0x00000001 1653 #define V_038000_ARRAY_1D_TILED_THIN1 0x00000002 1654 #define V_038000_ARRAY_2D_TILED_THIN1 0x00000004 1655 #define S_038000_TILE_TYPE(x) (((x) & 0x1) << 7) 1656 #define G_038000_TILE_TYPE(x) (((x) >> 7) & 0x1) 1657 #define C_038000_TILE_TYPE 0xFFFFFF7F 1658 #define S_038000_PITCH(x) (((x) & 0x7FF) << 8) 1659 #define G_038000_PITCH(x) (((x) >> 8) & 0x7FF) 1660 #define C_038000_PITCH 0xFFF800FF 1661 #define S_038000_TEX_WIDTH(x) (((x) & 0x1FFF) << 19) 1662 #define G_038000_TEX_WIDTH(x) (((x) >> 19) & 0x1FFF) 1663 #define C_038000_TEX_WIDTH 0x0007FFFF 1664 #define R_038004_SQ_TEX_RESOURCE_WORD1_0 0x038004 1665 #define S_038004_TEX_HEIGHT(x) (((x) & 0x1FFF) << 0) 1666 #define G_038004_TEX_HEIGHT(x) (((x) >> 0) & 0x1FFF) 1667 #define C_038004_TEX_HEIGHT 0xFFFFE000 1668 #define S_038004_TEX_DEPTH(x) (((x) & 0x1FFF) << 13) 1669 #define G_038004_TEX_DEPTH(x) (((x) >> 13) & 0x1FFF) 1670 #define C_038004_TEX_DEPTH 0xFC001FFF 1671 #define S_038004_DATA_FORMAT(x) (((x) & 0x3F) << 26) 1672 #define G_038004_DATA_FORMAT(x) (((x) >> 26) & 0x3F) 1673 #define C_038004_DATA_FORMAT 0x03FFFFFF 1674 #define V_038004_COLOR_INVALID 0x00000000 1675 #define V_038004_COLOR_8 0x00000001 1676 #define V_038004_COLOR_4_4 0x00000002 1677 #define V_038004_COLOR_3_3_2 0x00000003 1678 #define V_038004_COLOR_16 0x00000005 1679 #define V_038004_COLOR_16_FLOAT 0x00000006 1680 #define V_038004_COLOR_8_8 0x00000007 1681 #define V_038004_COLOR_5_6_5 0x00000008 1682 #define V_038004_COLOR_6_5_5 0x00000009 1683 #define V_038004_COLOR_1_5_5_5 0x0000000A 1684 #define V_038004_COLOR_4_4_4_4 0x0000000B 1685 #define V_038004_COLOR_5_5_5_1 0x0000000C 1686 #define V_038004_COLOR_32 0x0000000D 1687 #define V_038004_COLOR_32_FLOAT 0x0000000E 1688 #define V_038004_COLOR_16_16 0x0000000F 1689 #define V_038004_COLOR_16_16_FLOAT 0x00000010 1690 #define V_038004_COLOR_8_24 0x00000011 1691 #define V_038004_COLOR_8_24_FLOAT 0x00000012 1692 #define V_038004_COLOR_24_8 0x00000013 1693 #define V_038004_COLOR_24_8_FLOAT 0x00000014 1694 #define V_038004_COLOR_10_11_11 0x00000015 1695 #define V_038004_COLOR_10_11_11_FLOAT 0x00000016 1696 #define V_038004_COLOR_11_11_10 0x00000017 1697 #define V_038004_COLOR_11_11_10_FLOAT 0x00000018 1698 #define V_038004_COLOR_2_10_10_10 0x00000019 1699 #define V_038004_COLOR_8_8_8_8 0x0000001A 1700 #define V_038004_COLOR_10_10_10_2 0x0000001B 1701 #define V_038004_COLOR_X24_8_32_FLOAT 0x0000001C 1702 #define V_038004_COLOR_32_32 0x0000001D 1703 #define V_038004_COLOR_32_32_FLOAT 0x0000001E 1704 #define V_038004_COLOR_16_16_16_16 0x0000001F 1705 #define V_038004_COLOR_16_16_16_16_FLOAT 0x00000020 1706 #define V_038004_COLOR_32_32_32_32 0x00000022 1707 #define V_038004_COLOR_32_32_32_32_FLOAT 0x00000023 1708 #define V_038004_FMT_1 0x00000025 1709 #define V_038004_FMT_GB_GR 0x00000027 1710 #define V_038004_FMT_BG_RG 0x00000028 1711 #define V_038004_FMT_32_AS_8 0x00000029 1712 #define V_038004_FMT_32_AS_8_8 0x0000002A 1713 #define V_038004_FMT_5_9_9_9_SHAREDEXP 0x0000002B 1714 #define V_038004_FMT_8_8_8 0x0000002C 1715 #define V_038004_FMT_16_16_16 0x0000002D 1716 #define V_038004_FMT_16_16_16_FLOAT 0x0000002E 1717 #define V_038004_FMT_32_32_32 0x0000002F 1718 #define V_038004_FMT_32_32_32_FLOAT 0x00000030 1719 #define V_038004_FMT_BC1 0x00000031 1720 #define V_038004_FMT_BC2 0x00000032 1721 #define V_038004_FMT_BC3 0x00000033 1722 #define V_038004_FMT_BC4 0x00000034 1723 #define V_038004_FMT_BC5 0x00000035 1724 #define V_038004_FMT_BC6 0x00000036 1725 #define V_038004_FMT_BC7 0x00000037 1726 #define V_038004_FMT_32_AS_32_32_32_32 0x00000038 1727 #define R_038010_SQ_TEX_RESOURCE_WORD4_0 0x038010 1728 #define S_038010_FORMAT_COMP_X(x) (((x) & 0x3) << 0) 1729 #define G_038010_FORMAT_COMP_X(x) (((x) >> 0) & 0x3) 1730 #define C_038010_FORMAT_COMP_X 0xFFFFFFFC 1731 #define S_038010_FORMAT_COMP_Y(x) (((x) & 0x3) << 2) 1732 #define G_038010_FORMAT_COMP_Y(x) (((x) >> 2) & 0x3) 1733 #define C_038010_FORMAT_COMP_Y 0xFFFFFFF3 1734 #define S_038010_FORMAT_COMP_Z(x) (((x) & 0x3) << 4) 1735 #define G_038010_FORMAT_COMP_Z(x) (((x) >> 4) & 0x3) 1736 #define C_038010_FORMAT_COMP_Z 0xFFFFFFCF 1737 #define S_038010_FORMAT_COMP_W(x) (((x) & 0x3) << 6) 1738 #define G_038010_FORMAT_COMP_W(x) (((x) >> 6) & 0x3) 1739 #define C_038010_FORMAT_COMP_W 0xFFFFFF3F 1740 #define S_038010_NUM_FORMAT_ALL(x) (((x) & 0x3) << 8) 1741 #define G_038010_NUM_FORMAT_ALL(x) (((x) >> 8) & 0x3) 1742 #define C_038010_NUM_FORMAT_ALL 0xFFFFFCFF 1743 #define S_038010_SRF_MODE_ALL(x) (((x) & 0x1) << 10) 1744 #define G_038010_SRF_MODE_ALL(x) (((x) >> 10) & 0x1) 1745 #define C_038010_SRF_MODE_ALL 0xFFFFFBFF 1746 #define S_038010_FORCE_DEGAMMA(x) (((x) & 0x1) << 11) 1747 #define G_038010_FORCE_DEGAMMA(x) (((x) >> 11) & 0x1) 1748 #define C_038010_FORCE_DEGAMMA 0xFFFFF7FF 1749 #define S_038010_ENDIAN_SWAP(x) (((x) & 0x3) << 12) 1750 #define G_038010_ENDIAN_SWAP(x) (((x) >> 12) & 0x3) 1751 #define C_038010_ENDIAN_SWAP 0xFFFFCFFF 1752 #define S_038010_REQUEST_SIZE(x) (((x) & 0x3) << 14) 1753 #define G_038010_REQUEST_SIZE(x) (((x) >> 14) & 0x3) 1754 #define C_038010_REQUEST_SIZE 0xFFFF3FFF 1755 #define S_038010_DST_SEL_X(x) (((x) & 0x7) << 16) 1756 #define G_038010_DST_SEL_X(x) (((x) >> 16) & 0x7) 1757 #define C_038010_DST_SEL_X 0xFFF8FFFF 1758 #define S_038010_DST_SEL_Y(x) (((x) & 0x7) << 19) 1759 #define G_038010_DST_SEL_Y(x) (((x) >> 19) & 0x7) 1760 #define C_038010_DST_SEL_Y 0xFFC7FFFF 1761 #define S_038010_DST_SEL_Z(x) (((x) & 0x7) << 22) 1762 #define G_038010_DST_SEL_Z(x) (((x) >> 22) & 0x7) 1763 #define C_038010_DST_SEL_Z 0xFE3FFFFF 1764 #define S_038010_DST_SEL_W(x) (((x) & 0x7) << 25) 1765 #define G_038010_DST_SEL_W(x) (((x) >> 25) & 0x7) 1766 #define C_038010_DST_SEL_W 0xF1FFFFFF 1767 # define SQ_SEL_X 0 1768 # define SQ_SEL_Y 1 1769 # define SQ_SEL_Z 2 1770 # define SQ_SEL_W 3 1771 # define SQ_SEL_0 4 1772 # define SQ_SEL_1 5 1773 #define S_038010_BASE_LEVEL(x) (((x) & 0xF) << 28) 1774 #define G_038010_BASE_LEVEL(x) (((x) >> 28) & 0xF) 1775 #define C_038010_BASE_LEVEL 0x0FFFFFFF 1776 #define R_038014_SQ_TEX_RESOURCE_WORD5_0 0x038014 1777 #define S_038014_LAST_LEVEL(x) (((x) & 0xF) << 0) 1778 #define G_038014_LAST_LEVEL(x) (((x) >> 0) & 0xF) 1779 #define C_038014_LAST_LEVEL 0xFFFFFFF0 1780 #define S_038014_BASE_ARRAY(x) (((x) & 0x1FFF) << 4) 1781 #define G_038014_BASE_ARRAY(x) (((x) >> 4) & 0x1FFF) 1782 #define C_038014_BASE_ARRAY 0xFFFE000F 1783 #define S_038014_LAST_ARRAY(x) (((x) & 0x1FFF) << 17) 1784 #define G_038014_LAST_ARRAY(x) (((x) >> 17) & 0x1FFF) 1785 #define C_038014_LAST_ARRAY 0xC001FFFF 1786 #define R_0288A8_SQ_ESGS_RING_ITEMSIZE 0x0288A8 1787 #define S_0288A8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1788 #define G_0288A8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1789 #define C_0288A8_ITEMSIZE 0xFFFF8000 1790 #define R_008C44_SQ_ESGS_RING_SIZE 0x008C44 1791 #define S_008C44_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1792 #define G_008C44_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1793 #define C_008C44_MEM_SIZE 0x00000000 1794 #define R_0288B0_SQ_ESTMP_RING_ITEMSIZE 0x0288B0 1795 #define S_0288B0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1796 #define G_0288B0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1797 #define C_0288B0_ITEMSIZE 0xFFFF8000 1798 #define R_008C54_SQ_ESTMP_RING_SIZE 0x008C54 1799 #define S_008C54_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1800 #define G_008C54_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1801 #define C_008C54_MEM_SIZE 0x00000000 1802 #define R_0288C0_SQ_FBUF_RING_ITEMSIZE 0x0288C0 1803 #define S_0288C0_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1804 #define G_0288C0_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1805 #define C_0288C0_ITEMSIZE 0xFFFF8000 1806 #define R_008C74_SQ_FBUF_RING_SIZE 0x008C74 1807 #define S_008C74_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1808 #define G_008C74_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1809 #define C_008C74_MEM_SIZE 0x00000000 1810 #define R_0288B4_SQ_GSTMP_RING_ITEMSIZE 0x0288B4 1811 #define S_0288B4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1812 #define G_0288B4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1813 #define C_0288B4_ITEMSIZE 0xFFFF8000 1814 #define R_008C5C_SQ_GSTMP_RING_SIZE 0x008C5C 1815 #define S_008C5C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1816 #define G_008C5C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1817 #define C_008C5C_MEM_SIZE 0x00000000 1818 #define R_0288AC_SQ_GSVS_RING_ITEMSIZE 0x0288AC 1819 #define S_0288AC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1820 #define G_0288AC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1821 #define C_0288AC_ITEMSIZE 0xFFFF8000 1822 #define R_008C4C_SQ_GSVS_RING_SIZE 0x008C4C 1823 #define S_008C4C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1824 #define G_008C4C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1825 #define C_008C4C_MEM_SIZE 0x00000000 1826 #define R_0288BC_SQ_PSTMP_RING_ITEMSIZE 0x0288BC 1827 #define S_0288BC_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1828 #define G_0288BC_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1829 #define C_0288BC_ITEMSIZE 0xFFFF8000 1830 #define R_008C6C_SQ_PSTMP_RING_SIZE 0x008C6C 1831 #define S_008C6C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1832 #define G_008C6C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1833 #define C_008C6C_MEM_SIZE 0x00000000 1834 #define R_0288C4_SQ_REDUC_RING_ITEMSIZE 0x0288C4 1835 #define S_0288C4_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1836 #define G_0288C4_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1837 #define C_0288C4_ITEMSIZE 0xFFFF8000 1838 #define R_008C7C_SQ_REDUC_RING_SIZE 0x008C7C 1839 #define S_008C7C_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1840 #define G_008C7C_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1841 #define C_008C7C_MEM_SIZE 0x00000000 1842 #define R_0288B8_SQ_VSTMP_RING_ITEMSIZE 0x0288B8 1843 #define S_0288B8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1844 #define G_0288B8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1845 #define C_0288B8_ITEMSIZE 0xFFFF8000 1846 #define R_008C64_SQ_VSTMP_RING_SIZE 0x008C64 1847 #define S_008C64_MEM_SIZE(x) (((x) & 0xFFFFFFFF) << 0) 1848 #define G_008C64_MEM_SIZE(x) (((x) >> 0) & 0xFFFFFFFF) 1849 #define C_008C64_MEM_SIZE 0x00000000 1850 #define R_0288C8_SQ_GS_VERT_ITEMSIZE 0x0288C8 1851 #define S_0288C8_ITEMSIZE(x) (((x) & 0x7FFF) << 0) 1852 #define G_0288C8_ITEMSIZE(x) (((x) >> 0) & 0x7FFF) 1853 #define C_0288C8_ITEMSIZE 0xFFFF8000 1854 #define R_028010_DB_DEPTH_INFO 0x028010 1855 #define S_028010_FORMAT(x) (((x) & 0x7) << 0) 1856 #define G_028010_FORMAT(x) (((x) >> 0) & 0x7) 1857 #define C_028010_FORMAT 0xFFFFFFF8 1858 #define V_028010_DEPTH_INVALID 0x00000000 1859 #define V_028010_DEPTH_16 0x00000001 1860 #define V_028010_DEPTH_X8_24 0x00000002 1861 #define V_028010_DEPTH_8_24 0x00000003 1862 #define V_028010_DEPTH_X8_24_FLOAT 0x00000004 1863 #define V_028010_DEPTH_8_24_FLOAT 0x00000005 1864 #define V_028010_DEPTH_32_FLOAT 0x00000006 1865 #define V_028010_DEPTH_X24_8_32_FLOAT 0x00000007 1866 #define S_028010_READ_SIZE(x) (((x) & 0x1) << 3) 1867 #define G_028010_READ_SIZE(x) (((x) >> 3) & 0x1) 1868 #define C_028010_READ_SIZE 0xFFFFFFF7 1869 #define S_028010_ARRAY_MODE(x) (((x) & 0xF) << 15) 1870 #define G_028010_ARRAY_MODE(x) (((x) >> 15) & 0xF) 1871 #define C_028010_ARRAY_MODE 0xFFF87FFF 1872 #define V_028010_ARRAY_1D_TILED_THIN1 0x00000002 1873 #define V_028010_ARRAY_2D_TILED_THIN1 0x00000004 1874 #define S_028010_TILE_SURFACE_ENABLE(x) (((x) & 0x1) << 25) 1875 #define G_028010_TILE_SURFACE_ENABLE(x) (((x) >> 25) & 0x1) 1876 #define C_028010_TILE_SURFACE_ENABLE 0xFDFFFFFF 1877 #define S_028010_TILE_COMPACT(x) (((x) & 0x1) << 26) 1878 #define G_028010_TILE_COMPACT(x) (((x) >> 26) & 0x1) 1879 #define C_028010_TILE_COMPACT 0xFBFFFFFF 1880 #define S_028010_ZRANGE_PRECISION(x) (((x) & 0x1) << 31) 1881 #define G_028010_ZRANGE_PRECISION(x) (((x) >> 31) & 0x1) 1882 #define C_028010_ZRANGE_PRECISION 0x7FFFFFFF 1883 #define R_028000_DB_DEPTH_SIZE 0x028000 1884 #define S_028000_PITCH_TILE_MAX(x) (((x) & 0x3FF) << 0) 1885 #define G_028000_PITCH_TILE_MAX(x) (((x) >> 0) & 0x3FF) 1886 #define C_028000_PITCH_TILE_MAX 0xFFFFFC00 1887 #define S_028000_SLICE_TILE_MAX(x) (((x) & 0xFFFFF) << 10) 1888 #define G_028000_SLICE_TILE_MAX(x) (((x) >> 10) & 0xFFFFF) 1889 #define C_028000_SLICE_TILE_MAX 0xC00003FF 1890 #define R_028004_DB_DEPTH_VIEW 0x028004 1891 #define S_028004_SLICE_START(x) (((x) & 0x7FF) << 0) 1892 #define G_028004_SLICE_START(x) (((x) >> 0) & 0x7FF) 1893 #define C_028004_SLICE_START 0xFFFFF800 1894 #define S_028004_SLICE_MAX(x) (((x) & 0x7FF) << 13) 1895 #define G_028004_SLICE_MAX(x) (((x) >> 13) & 0x7FF) 1896 #define C_028004_SLICE_MAX 0xFF001FFF 1897 #define R_028800_DB_DEPTH_CONTROL 0x028800 1898 #define S_028800_STENCIL_ENABLE(x) (((x) & 0x1) << 0) 1899 #define G_028800_STENCIL_ENABLE(x) (((x) >> 0) & 0x1) 1900 #define C_028800_STENCIL_ENABLE 0xFFFFFFFE 1901 #define S_028800_Z_ENABLE(x) (((x) & 0x1) << 1) 1902 #define G_028800_Z_ENABLE(x) (((x) >> 1) & 0x1) 1903 #define C_028800_Z_ENABLE 0xFFFFFFFD 1904 #define S_028800_Z_WRITE_ENABLE(x) (((x) & 0x1) << 2) 1905 #define G_028800_Z_WRITE_ENABLE(x) (((x) >> 2) & 0x1) 1906 #define C_028800_Z_WRITE_ENABLE 0xFFFFFFFB 1907 #define S_028800_ZFUNC(x) (((x) & 0x7) << 4) 1908 #define G_028800_ZFUNC(x) (((x) >> 4) & 0x7) 1909 #define C_028800_ZFUNC 0xFFFFFF8F 1910 #define S_028800_BACKFACE_ENABLE(x) (((x) & 0x1) << 7) 1911 #define G_028800_BACKFACE_ENABLE(x) (((x) >> 7) & 0x1) 1912 #define C_028800_BACKFACE_ENABLE 0xFFFFFF7F 1913 #define S_028800_STENCILFUNC(x) (((x) & 0x7) << 8) 1914 #define G_028800_STENCILFUNC(x) (((x) >> 8) & 0x7) 1915 #define C_028800_STENCILFUNC 0xFFFFF8FF 1916 #define S_028800_STENCILFAIL(x) (((x) & 0x7) << 11) 1917 #define G_028800_STENCILFAIL(x) (((x) >> 11) & 0x7) 1918 #define C_028800_STENCILFAIL 0xFFFFC7FF 1919 #define S_028800_STENCILZPASS(x) (((x) & 0x7) << 14) 1920 #define G_028800_STENCILZPASS(x) (((x) >> 14) & 0x7) 1921 #define C_028800_STENCILZPASS 0xFFFE3FFF 1922 #define S_028800_STENCILZFAIL(x) (((x) & 0x7) << 17) 1923 #define G_028800_STENCILZFAIL(x) (((x) >> 17) & 0x7) 1924 #define C_028800_STENCILZFAIL 0xFFF1FFFF 1925 #define S_028800_STENCILFUNC_BF(x) (((x) & 0x7) << 20) 1926 #define G_028800_STENCILFUNC_BF(x) (((x) >> 20) & 0x7) 1927 #define C_028800_STENCILFUNC_BF 0xFF8FFFFF 1928 #define S_028800_STENCILFAIL_BF(x) (((x) & 0x7) << 23) 1929 #define G_028800_STENCILFAIL_BF(x) (((x) >> 23) & 0x7) 1930 #define C_028800_STENCILFAIL_BF 0xFC7FFFFF 1931 #define S_028800_STENCILZPASS_BF(x) (((x) & 0x7) << 26) 1932 #define G_028800_STENCILZPASS_BF(x) (((x) >> 26) & 0x7) 1933 #define C_028800_STENCILZPASS_BF 0xE3FFFFFF 1934 #define S_028800_STENCILZFAIL_BF(x) (((x) & 0x7) << 29) 1935 #define G_028800_STENCILZFAIL_BF(x) (((x) >> 29) & 0x7) 1936 #define C_028800_STENCILZFAIL_BF 0x1FFFFFFF 1937 1938 #endif 1939